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source: rtems-libbsd/freebsd/sys/dev/ffec/if_ffec.c @ a70edfc

55-freebsd-126-freebsd-12

Last change on this file since a70edfc was a70edfc, checked in by Sebastian Huber <sebastian.huber@…>, on 09/27/17 at 07:37:38
ffec: Add wmb() to descriptor updates
Property mode set to `100644`
File size: 48.0 KB

Line
1	#include <machine/rtems-bsd-kernel-space.h>
2
3	/*-
4	* Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
5	* All rights reserved.
6	*
7	* Redistribution and use in source and binary forms, with or without
8	* modification, are permitted provided that the following conditions
9	* are met:
10	* 1. Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.
12	* 2. Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.
15	*
16	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26	* SUCH DAMAGE.
27	*
28	*/
29
30	#include <sys/cdefs.h>
31	__FBSDID("$FreeBSD$");
32
33	/*
34	* Driver for Freescale Fast Ethernet Controller, found on imx-series SoCs among
35	* others. Also works for the ENET Gigibit controller found on imx6 and imx28,
36	* but the driver doesn't currently use any of the ENET advanced features other
37	* than enabling gigabit.
38	*
39	* The interface name 'fec' is already taken by netgraph's Fast Etherchannel
40	* (netgraph/ng_fec.c), so we use 'ffec'.
41	*
42	* Requires an FDT entry with at least these properties:
43	* fec: ethernet@02188000 {
44	* compatible = "fsl,imxNN-fec";
45	* reg = <0x02188000 0x4000>;
46	* interrupts = <150 151>;
47	* phy-mode = "rgmii";
48	* phy-disable-preamble; // optional
49	* };
50	* The second interrupt number is for IEEE-1588, and is not currently used; it
51	* need not be present. phy-mode must be one of: "mii", "rmii", "rgmii".
52	* There is also an optional property, phy-disable-preamble, which if present
53	* will disable the preamble bits, cutting the size of each mdio transaction
54	* (and thus the busy-wait time) in half.
55	*/
56
57	#include <sys/param.h>
58	#include <sys/systm.h>
59	#include <sys/bus.h>
60	#include <sys/endian.h>
61	#include <sys/kernel.h>
62	#include <sys/lock.h>
63	#include <sys/malloc.h>
64	#include <sys/mbuf.h>
65	#include <sys/module.h>
66	#include <sys/mutex.h>
67	#include <sys/rman.h>
68	#include <sys/socket.h>
69	#include <sys/sockio.h>
70	#include <sys/sysctl.h>
71
72	#include <machine/bus.h>
73
74	#include <net/bpf.h>
75	#include <net/if.h>
76	#include <net/ethernet.h>
77	#include <net/if_dl.h>
78	#include <net/if_media.h>
79	#include <net/if_types.h>
80	#include <net/if_var.h>
81	#include <net/if_vlan_var.h>
82
83	#include <dev/ffec/if_ffecreg.h>
84	#include <dev/ofw/ofw_bus.h>
85	#include <dev/ofw/ofw_bus_subr.h>
86	#include <dev/mii/mii.h>
87	#include <dev/mii/miivar.h>
88	#include <rtems/bsd/local/miibus_if.h>
89
90	/*
91	* There are small differences in the hardware on various SoCs. Not every SoC
92	* we support has its own FECTYPE; most work as GENERIC and only the ones that
93	* need different handling get their own entry. In addition to the types in
94	* this list, there are some flags below that can be ORed into the upper bits.
95	*/
96	enum {
97	FECTYPE_NONE,
98	FECTYPE_GENERIC,
99	FECTYPE_IMX53,
100	FECTYPE_IMX6,
101	FECTYPE_MVF,
102	};
103
104	/*
105	* Flags that describe general differences between the FEC hardware in various
106	* SoCs. These are ORed into the FECTYPE enum values.
107	*/
108	#define FECTYPE_MASK 0x0000ffff
109	#define FECFLAG_GBE (1 << 16)
110	#define FECFLAG_AVB (1 << 17)
111
112	/*
113	* Table of supported FDT compat strings and their associated FECTYPE values.
114	*/
115	static struct ofw_compat_data compat_data[] = {
116	{"fsl,imx51-fec", FECTYPE_GENERIC},
117	{"fsl,imx53-fec", FECTYPE_IMX53},
118	{"fsl,imx6q-fec", FECTYPE_IMX6 \| FECFLAG_GBE},
119	{"fsl,mvf600-fec", FECTYPE_MVF},
120	{"fsl,mvf-fec", FECTYPE_MVF},
121	{"fsl,imx7d-fec", FECTYPE_IMX6 \| FECFLAG_GBE \| FECFLAG_AVB},
122	{NULL, FECTYPE_NONE},
123	};
124
125	/*
126	* Driver data and defines.
127	*/
128	#define RX_DESC_COUNT 64
129	#define RX_DESC_SIZE (sizeof(struct ffec_hwdesc) * RX_DESC_COUNT)
130	#define TX_DESC_COUNT 64
131	#define TX_DESC_SIZE (sizeof(struct ffec_hwdesc) * TX_DESC_COUNT)
132
133	#define WATCHDOG_TIMEOUT_SECS 5
134	#define STATS_HARVEST_INTERVAL 3
135
136	#define MAX_IRQ_COUNT 3
137
138	struct ffec_bufmap {
139	struct mbuf *mbuf;
140	bus_dmamap_t map;
141	};
142
143	enum {
144	PHY_CONN_UNKNOWN,
145	PHY_CONN_MII,
146	PHY_CONN_RMII,
147	PHY_CONN_RGMII
148	};
149
150	struct ffec_softc {
151	device_t dev;
152	device_t miibus;
153	struct mii_data * mii_softc;
154	struct ifnet *ifp;
155	int if_flags;
156	struct mtx mtx;
157	struct resource *irq_res[MAX_IRQ_COUNT];
158	int irq_count;
159	struct resource *mem_res;
160	void * intr_cookie[MAX_IRQ_COUNT];
161	struct callout ffec_callout;
162	uint8_t phy_conn_type;
163	uintptr_t fectype;
164	boolean_t link_is_up;
165	boolean_t is_attached;
166	boolean_t is_detaching;
167	int tx_watchdog_count;
168	int stats_harvest_count;
169	int rxbuf_align;
170	int txbuf_align;
171
172	bus_dma_tag_t rxdesc_tag;
173	bus_dmamap_t rxdesc_map;
174	struct ffec_hwdesc *rxdesc_ring;
175	bus_addr_t rxdesc_ring_paddr;
176	bus_dma_tag_t rxbuf_tag;
177	struct ffec_bufmap rxbuf_map[RX_DESC_COUNT];
178	uint32_t rx_idx;
179
180	bus_dma_tag_t txdesc_tag;
181	bus_dmamap_t txdesc_map;
182	struct ffec_hwdesc *txdesc_ring;
183	bus_addr_t txdesc_ring_paddr;
184	bus_dma_tag_t txbuf_tag;
185	struct ffec_bufmap txbuf_map[TX_DESC_COUNT];
186	uint32_t tx_idx_head;
187	uint32_t tx_idx_tail;
188	int txcount;
189	};
190
191	#define FFEC_LOCK(sc) mtx_lock(&(sc)->mtx)
192	#define FFEC_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
193	#define FFEC_LOCK_INIT(sc) mtx_init(&(sc)->mtx, \
194	device_get_nameunit((sc)->dev), MTX_NETWORK_LOCK, MTX_DEF)
195	#define FFEC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx);
196	#define FFEC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED);
197	#define FFEC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED);
198
199	static void ffec_init_locked(struct ffec_softc *sc);
200	static void ffec_stop_locked(struct ffec_softc *sc);
201	static void ffec_txstart_locked(struct ffec_softc *sc);
202	static void ffec_txfinish_locked(struct ffec_softc *sc);
203
204	static inline uint16_t
205	RD2(struct ffec_softc *sc, bus_size_t off)
206	{
207
208	return (bus_read_2(sc->mem_res, off));
209	}
210
211	static inline void
212	WR2(struct ffec_softc *sc, bus_size_t off, uint16_t val)
213	{
214
215	bus_write_2(sc->mem_res, off, val);
216	}
217
218	static inline uint32_t
219	RD4(struct ffec_softc *sc, bus_size_t off)
220	{
221
222	return (bus_read_4(sc->mem_res, off));
223	}
224
225	static inline void
226	WR4(struct ffec_softc *sc, bus_size_t off, uint32_t val)
227	{
228
229	bus_write_4(sc->mem_res, off, val);
230	}
231
232	static inline uint32_t
233	next_rxidx(struct ffec_softc *sc, uint32_t curidx)
234	{
235
236	return ((curidx == RX_DESC_COUNT - 1) ? 0 : curidx + 1);
237	}
238
239	static inline uint32_t
240	next_txidx(struct ffec_softc *sc, uint32_t curidx)
241	{
242
243	return ((curidx == TX_DESC_COUNT - 1) ? 0 : curidx + 1);
244	}
245
246	static void
247	ffec_get1paddr(void arg, bus_dma_segment_t segs, int nsegs, int error)
248	{
249
250	if (error != 0)
251	return;
252	(bus_addr_t )arg = segs[0].ds_addr;
253	}
254
255	static void
256	ffec_miigasket_setup(struct ffec_softc *sc)
257	{
258	uint32_t ifmode;
259
260	/*
261	* We only need the gasket for MII and RMII connections on certain SoCs.
262	*/
263
264	switch (sc->fectype & FECTYPE_MASK)
265	{
266	case FECTYPE_IMX53:
267	break;
268	default:
269	return;
270	}
271
272	switch (sc->phy_conn_type)
273	{
274	case PHY_CONN_MII:
275	ifmode = 0;
276	break;
277	case PHY_CONN_RMII:
278	ifmode = FEC_MIIGSK_CFGR_IF_MODE_RMII;
279	break;
280	default:
281	return;
282	}
283
284	/*
285	* Disable the gasket, configure for either MII or RMII, then enable.
286	*/
287
288	WR2(sc, FEC_MIIGSK_ENR, 0);
289	while (RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY)
290	continue;
291
292	WR2(sc, FEC_MIIGSK_CFGR, ifmode);
293
294	WR2(sc, FEC_MIIGSK_ENR, FEC_MIIGSK_ENR_EN);
295	while (!(RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY))
296	continue;
297	}
298
299	static boolean_t
300	ffec_miibus_iowait(struct ffec_softc *sc)
301	{
302	uint32_t timeout;
303
304	for (timeout = 10000; timeout != 0; --timeout)
305	if (RD4(sc, FEC_IER_REG) & FEC_IER_MII)
306	return (true);
307
308	return (false);
309	}
310
311	static int
312	ffec_miibus_readreg(device_t dev, int phy, int reg)
313	{
314	struct ffec_softc *sc;
315	int val;
316
317	sc = device_get_softc(dev);
318
319	WR4(sc, FEC_IER_REG, FEC_IER_MII);
320
321	WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_READ \|
322	FEC_MMFR_ST_VALUE \| FEC_MMFR_TA_VALUE \|
323	((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) \|
324	((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK));
325
326	if (!ffec_miibus_iowait(sc)) {
327	device_printf(dev, "timeout waiting for mii read\n");
328	return (-1); /* All-ones is a symptom of bad mdio. */
329	}
330
331	val = RD4(sc, FEC_MMFR_REG) & FEC_MMFR_DATA_MASK;
332
333	return (val);
334	}
335
336	static int
337	ffec_miibus_writereg(device_t dev, int phy, int reg, int val)
338	{
339	struct ffec_softc *sc;
340
341	sc = device_get_softc(dev);
342
343	WR4(sc, FEC_IER_REG, FEC_IER_MII);
344
345	WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_WRITE \|
346	FEC_MMFR_ST_VALUE \| FEC_MMFR_TA_VALUE \|
347	((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) \|
348	((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK) \|
349	(val & FEC_MMFR_DATA_MASK));
350
351	if (!ffec_miibus_iowait(sc)) {
352	device_printf(dev, "timeout waiting for mii write\n");
353	return (-1);
354	}
355
356	return (0);
357	}
358
359	static void
360	ffec_miibus_statchg(device_t dev)
361	{
362	struct ffec_softc *sc;
363	struct mii_data *mii;
364	uint32_t ecr, rcr, tcr;
365
366	/*
367	* Called by the MII bus driver when the PHY establishes link to set the
368	* MAC interface registers.
369	*/
370
371	sc = device_get_softc(dev);
372
373	FFEC_ASSERT_LOCKED(sc);
374
375	mii = sc->mii_softc;
376
377	if (mii->mii_media_status & IFM_ACTIVE)
378	sc->link_is_up = true;
379	else
380	sc->link_is_up = false;
381
382	ecr = RD4(sc, FEC_ECR_REG) & ~FEC_ECR_SPEED;
383	rcr = RD4(sc, FEC_RCR_REG) & ~(FEC_RCR_RMII_10T \| FEC_RCR_RMII_MODE \|
384	FEC_RCR_RGMII_EN \| FEC_RCR_DRT \| FEC_RCR_FCE);
385	tcr = RD4(sc, FEC_TCR_REG) & ~FEC_TCR_FDEN;
386
387	rcr \|= FEC_RCR_MII_MODE; /* Must always be on even for R[G]MII. */
388	switch (sc->phy_conn_type) {
389	case PHY_CONN_MII:
390	break;
391	case PHY_CONN_RMII:
392	rcr \|= FEC_RCR_RMII_MODE;
393	break;
394	case PHY_CONN_RGMII:
395	rcr \|= FEC_RCR_RGMII_EN;
396	break;
397	}
398
399	switch (IFM_SUBTYPE(mii->mii_media_active)) {
400	case IFM_1000_T:
401	case IFM_1000_SX:
402	ecr \|= FEC_ECR_SPEED;
403	break;
404	case IFM_100_TX:
405	/* Not-FEC_ECR_SPEED + not-FEC_RCR_RMII_10T means 100TX */
406	break;
407	case IFM_10_T:
408	rcr \|= FEC_RCR_RMII_10T;
409	break;
410	case IFM_NONE:
411	sc->link_is_up = false;
412	return;
413	default:
414	sc->link_is_up = false;
415	device_printf(dev, "Unsupported media %u\n",
416	IFM_SUBTYPE(mii->mii_media_active));
417	return;
418	}
419
420	if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
421	tcr \|= FEC_TCR_FDEN;
422	else
423	rcr \|= FEC_RCR_DRT;
424
425	if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLOW) != 0)
426	rcr \|= FEC_RCR_FCE;
427
428	WR4(sc, FEC_RCR_REG, rcr);
429	WR4(sc, FEC_TCR_REG, tcr);
430	WR4(sc, FEC_ECR_REG, ecr);
431	}
432
433	static void
434	ffec_media_status(struct ifnet * ifp, struct ifmediareq *ifmr)
435	{
436	struct ffec_softc *sc;
437	struct mii_data *mii;
438
439
440	sc = ifp->if_softc;
441	mii = sc->mii_softc;
442	FFEC_LOCK(sc);
443	mii_pollstat(mii);
444	ifmr->ifm_active = mii->mii_media_active;
445	ifmr->ifm_status = mii->mii_media_status;
446	FFEC_UNLOCK(sc);
447	}
448
449	static int
450	ffec_media_change_locked(struct ffec_softc *sc)
451	{
452
453	return (mii_mediachg(sc->mii_softc));
454	}
455
456	static int
457	ffec_media_change(struct ifnet * ifp)
458	{
459	struct ffec_softc *sc;
460	int error;
461
462	sc = ifp->if_softc;
463
464	FFEC_LOCK(sc);
465	error = ffec_media_change_locked(sc);
466	FFEC_UNLOCK(sc);
467	return (error);
468	}
469
470	static void ffec_clear_stats(struct ffec_softc *sc)
471	{
472
473	WR4(sc, FEC_RMON_R_PACKETS, 0);
474	WR4(sc, FEC_RMON_R_MC_PKT, 0);
475	WR4(sc, FEC_RMON_R_CRC_ALIGN, 0);
476	WR4(sc, FEC_RMON_R_UNDERSIZE, 0);
477	WR4(sc, FEC_RMON_R_OVERSIZE, 0);
478	WR4(sc, FEC_RMON_R_FRAG, 0);
479	WR4(sc, FEC_RMON_R_JAB, 0);
480	WR4(sc, FEC_RMON_T_PACKETS, 0);
481	WR4(sc, FEC_RMON_T_MC_PKT, 0);
482	WR4(sc, FEC_RMON_T_CRC_ALIGN, 0);
483	WR4(sc, FEC_RMON_T_UNDERSIZE, 0);
484	WR4(sc, FEC_RMON_T_OVERSIZE , 0);
485	WR4(sc, FEC_RMON_T_FRAG, 0);
486	WR4(sc, FEC_RMON_T_JAB, 0);
487	WR4(sc, FEC_RMON_T_COL, 0);
488	}
489
490	static void
491	ffec_harvest_stats(struct ffec_softc *sc)
492	{
493	struct ifnet *ifp;
494
495	/* We don't need to harvest too often. */
496	if (++sc->stats_harvest_count < STATS_HARVEST_INTERVAL)
497	return;
498
499	/*
500	* Try to avoid harvesting unless the IDLE flag is on, but if it has
501	* been too long just go ahead and do it anyway, the worst that'll
502	* happen is we'll lose a packet count or two as we clear at the end.
503	*/
504	if (sc->stats_harvest_count < (2 * STATS_HARVEST_INTERVAL) &&
505	((RD4(sc, FEC_MIBC_REG) & FEC_MIBC_IDLE) == 0))
506	return;
507
508	sc->stats_harvest_count = 0;
509	ifp = sc->ifp;
510
511	if_inc_counter(ifp, IFCOUNTER_IPACKETS, RD4(sc, FEC_RMON_R_PACKETS));
512	if_inc_counter(ifp, IFCOUNTER_IMCASTS, RD4(sc, FEC_RMON_R_MC_PKT));
513	if_inc_counter(ifp, IFCOUNTER_IERRORS,
514	RD4(sc, FEC_RMON_R_CRC_ALIGN) + RD4(sc, FEC_RMON_R_UNDERSIZE) +
515	RD4(sc, FEC_RMON_R_OVERSIZE) + RD4(sc, FEC_RMON_R_FRAG) +
516	RD4(sc, FEC_RMON_R_JAB));
517
518	if_inc_counter(ifp, IFCOUNTER_OPACKETS, RD4(sc, FEC_RMON_T_PACKETS));
519	if_inc_counter(ifp, IFCOUNTER_OMCASTS, RD4(sc, FEC_RMON_T_MC_PKT));
520	if_inc_counter(ifp, IFCOUNTER_OERRORS,
521	RD4(sc, FEC_RMON_T_CRC_ALIGN) + RD4(sc, FEC_RMON_T_UNDERSIZE) +
522	RD4(sc, FEC_RMON_T_OVERSIZE) + RD4(sc, FEC_RMON_T_FRAG) +
523	RD4(sc, FEC_RMON_T_JAB));
524
525	if_inc_counter(ifp, IFCOUNTER_COLLISIONS, RD4(sc, FEC_RMON_T_COL));
526
527	ffec_clear_stats(sc);
528	}
529
530	static void
531	ffec_tick(void *arg)
532	{
533	struct ffec_softc *sc;
534	struct ifnet *ifp;
535	int link_was_up;
536
537	sc = arg;
538
539	FFEC_ASSERT_LOCKED(sc);
540
541	ifp = sc->ifp;
542
543	if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
544	return;
545
546	/*
547	* Typical tx watchdog. If this fires it indicates that we enqueued
548	* packets for output and never got a txdone interrupt for them. Maybe
549	* it's a missed interrupt somehow, just pretend we got one.
550	*/
551	if (sc->tx_watchdog_count > 0) {
552	if (--sc->tx_watchdog_count == 0) {
553	ffec_txfinish_locked(sc);
554	}
555	}
556
557	/* Gather stats from hardware counters. */
558	ffec_harvest_stats(sc);
559
560	/* Check the media status. */
561	link_was_up = sc->link_is_up;
562	mii_tick(sc->mii_softc);
563	if (sc->link_is_up && !link_was_up)
564	ffec_txstart_locked(sc);
565
566	/* Schedule another check one second from now. */
567	callout_reset(&sc->ffec_callout, hz, ffec_tick, sc);
568	}
569
570	inline static uint32_t
571	ffec_setup_txdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr,
572	uint32_t len)
573	{
574	uint32_t nidx;
575	uint32_t flags;
576
577	nidx = next_txidx(sc, idx);
578
579	/* Addr/len 0 means we're clearing the descriptor after xmit done. */
580	if (paddr == 0 \|\| len == 0) {
581	flags = 0;
582	--sc->txcount;
583	} else {
584	flags = FEC_TXDESC_READY \| FEC_TXDESC_L \| FEC_TXDESC_TC;
585	++sc->txcount;
586	}
587	if (nidx == 0)
588	flags \|= FEC_TXDESC_WRAP;
589
590	/*
591	* The hardware requires 32-bit physical addresses. We set up the dma
592	* tag to indicate that, so the cast to uint32_t should never lose
593	* significant bits.
594	*/
595	sc->txdesc_ring[idx].buf_paddr = (uint32_t)paddr;
596	wmb();
597	sc->txdesc_ring[idx].flags_len = flags \| len; /* Must be set last! */
598
599	return (nidx);
600	}
601
602	static int
603	ffec_setup_txbuf(struct ffec_softc sc, int idx, struct mbuf *mp)
604	{
605	struct mbuf * m;
606	int error, nsegs;
607	struct bus_dma_segment seg;
608
609	if ((m = m_defrag(*mp, M_NOWAIT)) == NULL)
610	return (ENOMEM);
611	*mp = m;
612
613	error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map,
614	m, &seg, &nsegs, 0);
615	if (error != 0) {
616	return (ENOMEM);
617	}
618	#ifndef __rtems__
619	bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map,
620	BUS_DMASYNC_PREWRITE);
621	#else /* __rtems__ */
622	rtems_cache_flush_multiple_data_lines((void *)seg.ds_addr, seg.ds_len);
623	#endif /* __rtems__ */
624
625	sc->txbuf_map[idx].mbuf = m;
626	ffec_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len);
627
628	return (0);
629
630	}
631
632	static void
633	ffec_txstart_locked(struct ffec_softc *sc)
634	{
635	struct ifnet *ifp;
636	struct mbuf *m;
637	int enqueued;
638
639	FFEC_ASSERT_LOCKED(sc);
640
641	if (!sc->link_is_up)
642	return;
643
644	ifp = sc->ifp;
645
646	if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
647	return;
648
649	enqueued = 0;
650
651	for (;;) {
652	if (sc->txcount == (TX_DESC_COUNT-1)) {
653	ifp->if_drv_flags \|= IFF_DRV_OACTIVE;
654	break;
655	}
656	IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
657	if (m == NULL)
658	break;
659	if (ffec_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) {
660	IFQ_DRV_PREPEND(&ifp->if_snd, m);
661	break;
662	}
663	BPF_MTAP(ifp, m);
664	sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head);
665	++enqueued;
666	}
667
668	if (enqueued != 0) {
669	bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREWRITE);
670	WR4(sc, FEC_TDAR_REG, FEC_TDAR_TDAR);
671	bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTWRITE);
672	sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS;
673	}
674	}
675
676	static void
677	ffec_txstart(struct ifnet *ifp)
678	{
679	struct ffec_softc *sc = ifp->if_softc;
680
681	FFEC_LOCK(sc);
682	ffec_txstart_locked(sc);
683	FFEC_UNLOCK(sc);
684	}
685
686	static void
687	ffec_txfinish_locked(struct ffec_softc *sc)
688	{
689	struct ifnet *ifp;
690	struct ffec_hwdesc *desc;
691	struct ffec_bufmap *bmap;
692	boolean_t retired_buffer;
693
694	FFEC_ASSERT_LOCKED(sc);
695
696	/* XXX Can't set PRE\|POST right now, but we need both. */
697	bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREREAD);
698	bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTREAD);
699	ifp = sc->ifp;
700	retired_buffer = false;
701	while (sc->tx_idx_tail != sc->tx_idx_head) {
702	desc = &sc->txdesc_ring[sc->tx_idx_tail];
703	if (desc->flags_len & FEC_TXDESC_READY)
704	break;
705	retired_buffer = true;
706	bmap = &sc->txbuf_map[sc->tx_idx_tail];
707	bus_dmamap_sync(sc->txbuf_tag, bmap->map,
708	BUS_DMASYNC_POSTWRITE);
709	bus_dmamap_unload(sc->txbuf_tag, bmap->map);
710	m_freem(bmap->mbuf);
711	bmap->mbuf = NULL;
712	ffec_setup_txdesc(sc, sc->tx_idx_tail, 0, 0);
713	sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail);
714	}
715
716	/*
717	* If we retired any buffers, there will be open tx slots available in
718	* the descriptor ring, go try to start some new output.
719	*/
720	if (retired_buffer) {
721	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
722	ffec_txstart_locked(sc);
723	}
724
725	/* If there are no buffers outstanding, muzzle the watchdog. */
726	if (sc->tx_idx_tail == sc->tx_idx_head) {
727	sc->tx_watchdog_count = 0;
728	}
729	}
730
731	inline static uint32_t
732	ffec_setup_rxdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr)
733	{
734	uint32_t nidx;
735
736	/*
737	* The hardware requires 32-bit physical addresses. We set up the dma
738	* tag to indicate that, so the cast to uint32_t should never lose
739	* significant bits.
740	*/
741	nidx = next_rxidx(sc, idx);
742	sc->rxdesc_ring[idx].buf_paddr = (uint32_t)paddr;
743	wmb();
744	sc->rxdesc_ring[idx].flags_len = FEC_RXDESC_EMPTY \|
745	((nidx == 0) ? FEC_RXDESC_WRAP : 0);
746
747	return (nidx);
748	}
749
750	static int
751	ffec_setup_rxbuf(struct ffec_softc sc, int idx, struct mbuf m)
752	{
753	int error, nsegs;
754	struct bus_dma_segment seg;
755
756	/*
757	* We need to leave at least ETHER_ALIGN bytes free at the beginning of
758	* the buffer to allow the data to be re-aligned after receiving it (by
759	* copying it backwards ETHER_ALIGN bytes in the same buffer). We also
760	* have to ensure that the beginning of the buffer is aligned to the
761	* hardware's requirements.
762	*/
763	m_adj(m, roundup(ETHER_ALIGN, sc->rxbuf_align));
764
765	error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
766	m, &seg, &nsegs, 0);
767	if (error != 0) {
768	return (error);
769	}
770
771	bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
772	BUS_DMASYNC_PREREAD);
773
774	sc->rxbuf_map[idx].mbuf = m;
775	ffec_setup_rxdesc(sc, idx, seg.ds_addr);
776
777	return (0);
778	}
779
780	static struct mbuf *
781	ffec_alloc_mbufcl(struct ffec_softc *sc)
782	{
783	struct mbuf *m;
784
785	m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
786	m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
787	#ifdef __rtems__
788	rtems_cache_invalidate_multiple_data_lines(m->m_data, m->m_len);
789	#endif /* __rtems__ */
790
791	return (m);
792	}
793
794	static void
795	ffec_rxfinish_onebuf(struct ffec_softc *sc, int len)
796	{
797	struct mbuf m, newmbuf;
798	struct ffec_bufmap *bmap;
799	uint8_t dst, src;
800	int error;
801
802	/*
803	* First try to get a new mbuf to plug into this slot in the rx ring.
804	* If that fails, drop the current packet and recycle the current
805	* mbuf, which is still mapped and loaded.
806	*/
807	if ((newmbuf = ffec_alloc_mbufcl(sc)) == NULL) {
808	if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1);
809	ffec_setup_rxdesc(sc, sc->rx_idx,
810	sc->rxdesc_ring[sc->rx_idx].buf_paddr);
811	return;
812	}
813
814	/*
815	* Unfortunately, the protocol headers need to be aligned on a 32-bit
816	* boundary for the upper layers. The hardware requires receive
817	* buffers to be 16-byte aligned. The ethernet header is 14 bytes,
818	* leaving the protocol header unaligned. We used m_adj() after
819	* allocating the buffer to leave empty space at the start of the
820	* buffer, now we'll use the alignment agnostic bcopy() routine to
821	* shuffle all the data backwards 2 bytes and adjust m_data.
822	*
823	* XXX imx6 hardware is able to do this 2-byte alignment by setting the
824	* SHIFT16 bit in the RACC register. Older hardware doesn't have that
825	* feature, but for them could we speed this up by copying just the
826	* protocol headers into their own small mbuf then chaining the cluster
827	* to it? That way we'd only need to copy like 64 bytes or whatever
828	* the biggest header is, instead of the whole 1530ish-byte frame.
829	*/
830
831	FFEC_UNLOCK(sc);
832
833	bmap = &sc->rxbuf_map[sc->rx_idx];
834	len -= ETHER_CRC_LEN;
835	bus_dmamap_sync(sc->rxbuf_tag, bmap->map, BUS_DMASYNC_POSTREAD);
836	bus_dmamap_unload(sc->rxbuf_tag, bmap->map);
837	m = bmap->mbuf;
838	bmap->mbuf = NULL;
839	m->m_len = len;
840	m->m_pkthdr.len = len;
841	m->m_pkthdr.rcvif = sc->ifp;
842
843	src = mtod(m, uint8_t*);
844	dst = src - ETHER_ALIGN;
845	bcopy(src, dst, len);
846	m->m_data = dst;
847	sc->ifp->if_input(sc->ifp, m);
848
849	FFEC_LOCK(sc);
850
851	if ((error = ffec_setup_rxbuf(sc, sc->rx_idx, newmbuf)) != 0) {
852	device_printf(sc->dev, "ffec_setup_rxbuf error %d\n", error);
853	/* XXX Now what? We've got a hole in the rx ring. */
854	}
855
856	}
857
858	static void
859	ffec_rxfinish_locked(struct ffec_softc *sc)
860	{
861	struct ffec_hwdesc *desc;
862	int len;
863	boolean_t produced_empty_buffer;
864
865	FFEC_ASSERT_LOCKED(sc);
866
867	/* XXX Can't set PRE\|POST right now, but we need both. */
868	bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_PREREAD);
869	bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_POSTREAD);
870	produced_empty_buffer = false;
871	for (;;) {
872	desc = &sc->rxdesc_ring[sc->rx_idx];
873	if (desc->flags_len & FEC_RXDESC_EMPTY)
874	break;
875	produced_empty_buffer = true;
876	len = (desc->flags_len & FEC_RXDESC_LEN_MASK);
877	if (len < 64) {
878	/*
879	* Just recycle the descriptor and continue. .
880	*/
881	ffec_setup_rxdesc(sc, sc->rx_idx,
882	sc->rxdesc_ring[sc->rx_idx].buf_paddr);
883	} else if ((desc->flags_len & FEC_RXDESC_L) == 0) {
884	/*
885	* The entire frame is not in this buffer. Impossible.
886	* Recycle the descriptor and continue.
887	*
888	* XXX what's the right way to handle this? Probably we
889	* should stop/init the hardware because this should
890	* just really never happen when we have buffers bigger
891	* than the maximum frame size.
892	*/
893	device_printf(sc->dev,
894	"fec_rxfinish: received frame without LAST bit set");
895	ffec_setup_rxdesc(sc, sc->rx_idx,
896	sc->rxdesc_ring[sc->rx_idx].buf_paddr);
897	} else if (desc->flags_len & FEC_RXDESC_ERROR_BITS) {
898	/*
899	* Something went wrong with receiving the frame, we
900	* don't care what (the hardware has counted the error
901	* in the stats registers already), we just reuse the
902	* same mbuf, which is still dma-mapped, by resetting
903	* the rx descriptor.
904	*/
905	ffec_setup_rxdesc(sc, sc->rx_idx,
906	sc->rxdesc_ring[sc->rx_idx].buf_paddr);
907	} else {
908	/*
909	* Normal case: a good frame all in one buffer.
910	*/
911	ffec_rxfinish_onebuf(sc, len);
912	}
913	sc->rx_idx = next_rxidx(sc, sc->rx_idx);
914	}
915
916	if (produced_empty_buffer) {
917	bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_PREWRITE);
918	WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR);
919	bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_POSTWRITE);
920	}
921	}
922
923	static void
924	ffec_get_hwaddr(struct ffec_softc sc, uint8_t hwaddr)
925	{
926	uint32_t palr, paur, rnd;
927
928	/*
929	* Try to recover a MAC address from the running hardware. If there's
930	* something non-zero there, assume the bootloader did the right thing
931	* and just use it.
932	*
933	* Otherwise, set the address to a convenient locally assigned address,
934	* 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally
935	* assigned bit set, and the broadcast/multicast bit clear.
936	*/
937	palr = RD4(sc, FEC_PALR_REG);
938	paur = RD4(sc, FEC_PAUR_REG) & FEC_PAUR_PADDR2_MASK;
939	if ((palr \| paur) != 0) {
940	hwaddr[0] = palr >> 24;
941	hwaddr[1] = palr >> 16;
942	hwaddr[2] = palr >> 8;
943	hwaddr[3] = palr >> 0;
944	hwaddr[4] = paur >> 24;
945	hwaddr[5] = paur >> 16;
946	} else {
947	rnd = arc4random() & 0x00ffffff;
948	hwaddr[0] = 'b';
949	hwaddr[1] = 's';
950	hwaddr[2] = 'd';
951	hwaddr[3] = rnd >> 16;
952	hwaddr[4] = rnd >> 8;
953	hwaddr[5] = rnd >> 0;
954	}
955
956	if (bootverbose) {
957	device_printf(sc->dev,
958	"MAC address %02x:%02x:%02x:%02x:%02x:%02x:\n",
959	hwaddr[0], hwaddr[1], hwaddr[2],
960	hwaddr[3], hwaddr[4], hwaddr[5]);
961	}
962	}
963
964	static void
965	ffec_setup_rxfilter(struct ffec_softc *sc)
966	{
967	struct ifnet *ifp;
968	struct ifmultiaddr *ifma;
969	uint8_t *eaddr;
970	uint32_t crc;
971	uint64_t ghash, ihash;
972
973	FFEC_ASSERT_LOCKED(sc);
974
975	ifp = sc->ifp;
976
977	/*
978	* Set the multicast (group) filter hash.
979	*/
980	if ((ifp->if_flags & IFF_ALLMULTI))
981	ghash = 0xffffffffffffffffLLU;
982	else {
983	ghash = 0;
984	if_maddr_rlock(ifp);
985	TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) {
986	if (ifma->ifma_addr->sa_family != AF_LINK)
987	continue;
988	/* 6 bits from MSB in LE CRC32 are used for hash. */
989	crc = ether_crc32_le(LLADDR((struct sockaddr_dl *)
990	ifma->ifma_addr), ETHER_ADDR_LEN);
991	ghash \|= 1LLU << (((uint8_t *)&crc)[3] >> 2);
992	}
993	if_maddr_runlock(ifp);
994	}
995	WR4(sc, FEC_GAUR_REG, (uint32_t)(ghash >> 32));
996	WR4(sc, FEC_GALR_REG, (uint32_t)ghash);
997
998	/*
999	* Set the individual address filter hash.
1000	*
1001	* XXX Is 0 the right value when promiscuous is off? This hw feature
1002	* seems to support the concept of MAC address aliases, does such a
1003	* thing even exist?
1004	*/
1005	if ((ifp->if_flags & IFF_PROMISC))
1006	ihash = 0xffffffffffffffffLLU;
1007	else {
1008	ihash = 0;
1009	}
1010	WR4(sc, FEC_IAUR_REG, (uint32_t)(ihash >> 32));
1011	WR4(sc, FEC_IALR_REG, (uint32_t)ihash);
1012
1013	/*
1014	* Set the primary address.
1015	*/
1016	eaddr = IF_LLADDR(ifp);
1017	WR4(sc, FEC_PALR_REG, (eaddr[0] << 24) \| (eaddr[1] << 16) \|
1018	(eaddr[2] << 8) \| eaddr[3]);
1019	WR4(sc, FEC_PAUR_REG, (eaddr[4] << 24) \| (eaddr[5] << 16));
1020	}
1021
1022	static void
1023	ffec_stop_locked(struct ffec_softc *sc)
1024	{
1025	struct ifnet *ifp;
1026	struct ffec_hwdesc *desc;
1027	struct ffec_bufmap *bmap;
1028	int idx;
1029
1030	FFEC_ASSERT_LOCKED(sc);
1031
1032	ifp = sc->ifp;
1033	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING \| IFF_DRV_OACTIVE);
1034	sc->tx_watchdog_count = 0;
1035	sc->stats_harvest_count = 0;
1036
1037	/*
1038	* Stop the hardware, mask all interrupts, and clear all current
1039	* interrupt status bits.
1040	*/
1041	WR4(sc, FEC_ECR_REG, RD4(sc, FEC_ECR_REG) & ~FEC_ECR_ETHEREN);
1042	WR4(sc, FEC_IEM_REG, 0x00000000);
1043	WR4(sc, FEC_IER_REG, 0xffffffff);
1044
1045	/*
1046	* Stop the media-check callout. Do not use callout_drain() because
1047	* we're holding a mutex the callout acquires, and if it's currently
1048	* waiting to acquire it, we'd deadlock. If it is waiting now, the
1049	* ffec_tick() routine will return without doing anything when it sees
1050	* that IFF_DRV_RUNNING is not set, so avoiding callout_drain() is safe.
1051	*/
1052	callout_stop(&sc->ffec_callout);
1053
1054	/*
1055	* Discard all untransmitted buffers. Each buffer is simply freed;
1056	* it's as if the bits were transmitted and then lost on the wire.
1057	*
1058	* XXX Is this right? Or should we use IFQ_DRV_PREPEND() to put them
1059	* back on the queue for when we get restarted later?
1060	*/
1061	idx = sc->tx_idx_tail;
1062	while (idx != sc->tx_idx_head) {
1063	desc = &sc->txdesc_ring[idx];
1064	bmap = &sc->txbuf_map[idx];
1065	if (desc->buf_paddr != 0) {
1066	bus_dmamap_unload(sc->txbuf_tag, bmap->map);
1067	m_freem(bmap->mbuf);
1068	bmap->mbuf = NULL;
1069	ffec_setup_txdesc(sc, idx, 0, 0);
1070	}
1071	idx = next_txidx(sc, idx);
1072	}
1073
1074	/*
1075	* Discard all unprocessed receive buffers. This amounts to just
1076	* pretending that nothing ever got received into them. We reuse the
1077	* mbuf already mapped for each desc, simply turning the EMPTY flags
1078	* back on so they'll get reused when we start up again.
1079	*/
1080	for (idx = 0; idx < RX_DESC_COUNT; ++idx) {
1081	desc = &sc->rxdesc_ring[idx];
1082	ffec_setup_rxdesc(sc, idx, desc->buf_paddr);
1083	}
1084	}
1085
1086	static void
1087	ffec_init_locked(struct ffec_softc *sc)
1088	{
1089	struct ifnet *ifp = sc->ifp;
1090	uint32_t maxbuf, maxfl, regval;
1091
1092	FFEC_ASSERT_LOCKED(sc);
1093
1094	/*
1095	* The hardware has a limit of 0x7ff as the max frame length (see
1096	* comments for MRBR below), and we use mbuf clusters as receive
1097	* buffers, and we currently are designed to receive an entire frame
1098	* into a single buffer.
1099	*
1100	* We start with a MCLBYTES-sized cluster, but we have to offset into
1101	* the buffer by ETHER_ALIGN to make room for post-receive re-alignment,
1102	* and then that value has to be rounded up to the hardware's DMA
1103	* alignment requirements, so all in all our buffer is that much smaller
1104	* than MCLBYTES.
1105	*
1106	* The resulting value is used as the frame truncation length and the
1107	* max buffer receive buffer size for now. It'll become more complex
1108	* when we support jumbo frames and receiving fragments of them into
1109	* separate buffers.
1110	*/
1111	maxbuf = MCLBYTES - roundup(ETHER_ALIGN, sc->rxbuf_align);
1112	maxfl = min(maxbuf, 0x7ff);
1113
1114	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1115	return;
1116
1117	/* Mask all interrupts and clear all current interrupt status bits. */
1118	WR4(sc, FEC_IEM_REG, 0x00000000);
1119	WR4(sc, FEC_IER_REG, 0xffffffff);
1120
1121	/*
1122	* Go set up palr/puar, galr/gaur, ialr/iaur.
1123	*/
1124	ffec_setup_rxfilter(sc);
1125
1126	/*
1127	* TFWR - Transmit FIFO watermark register.
1128	*
1129	* Set the transmit fifo watermark register to "store and forward" mode
1130	* and also set a threshold of 128 bytes in the fifo before transmission
1131	* of a frame begins (to avoid dma underruns). Recent FEC hardware
1132	* supports STRFWD and when that bit is set, the watermark level in the
1133	* low bits is ignored. Older hardware doesn't have STRFWD, but writing
1134	* to that bit is innocuous, and the TWFR bits get used instead.
1135	*/
1136	WR4(sc, FEC_TFWR_REG, FEC_TFWR_STRFWD \| FEC_TFWR_TWFR_128BYTE);
1137
1138	/* RCR - Receive control register.
1139	*
1140	* Set max frame length + clean out anything left from u-boot.
1141	*/
1142	WR4(sc, FEC_RCR_REG, (maxfl << FEC_RCR_MAX_FL_SHIFT));
1143
1144	/*
1145	* TCR - Transmit control register.
1146	*
1147	* Clean out anything left from u-boot. Any necessary values are set in
1148	* ffec_miibus_statchg() based on the media type.
1149	*/
1150	WR4(sc, FEC_TCR_REG, 0);
1151
1152	/*
1153	* OPD - Opcode/pause duration.
1154	*
1155	* XXX These magic numbers come from u-boot.
1156	*/
1157	WR4(sc, FEC_OPD_REG, 0x00010020);
1158
1159	/*
1160	* FRSR - Fifo receive start register.
1161	*
1162	* This register does not exist on imx6, it is present on earlier
1163	* hardware. The u-boot code sets this to a non-default value that's 32
1164	* bytes larger than the default, with no clue as to why. The default
1165	* value should work fine, so there's no code to init it here.
1166	*/
1167
1168	/*
1169	* MRBR - Max RX buffer size.
1170	*
1171	* Note: For hardware prior to imx6 this value cannot exceed 0x07ff,
1172	* but the datasheet says no such thing for imx6. On the imx6, setting
1173	* this to 2K without setting EN1588 resulted in a crazy runaway
1174	* receive loop in the hardware, where every rx descriptor in the ring
1175	* had its EMPTY flag cleared, no completion or error flags set, and a
1176	* length of zero. I think maybe you can only exceed it when EN1588 is
1177	* set, like maybe that's what enables jumbo frames, because in general
1178	* the EN1588 flag seems to be the "enable new stuff" vs. "be legacy-
1179	* compatible" flag.
1180	*/
1181	WR4(sc, FEC_MRBR_REG, maxfl << FEC_MRBR_R_BUF_SIZE_SHIFT);
1182
1183	/*
1184	* FTRL - Frame truncation length.
1185	*
1186	* Must be greater than or equal to the value set in FEC_RCR_MAXFL.
1187	*/
1188	WR4(sc, FEC_FTRL_REG, maxfl);
1189
1190	/*
1191	* RDSR / TDSR descriptor ring pointers.
1192	*
1193	* When we turn on ECR_ETHEREN at the end, the hardware zeroes its
1194	* internal current descriptor index values for both rings, so we zero
1195	* our index values as well.
1196	*/
1197	sc->rx_idx = 0;
1198	sc->tx_idx_head = sc->tx_idx_tail = 0;
1199	sc->txcount = 0;
1200	WR4(sc, FEC_RDSR_REG, sc->rxdesc_ring_paddr);
1201	WR4(sc, FEC_TDSR_REG, sc->txdesc_ring_paddr);
1202
1203	/*
1204	* EIM - interrupt mask register.
1205	*
1206	* We always enable the same set of interrupts while running; unlike
1207	* some drivers there's no need to change the mask on the fly depending
1208	* on what operations are in progress.
1209	*/
1210	WR4(sc, FEC_IEM_REG, FEC_IER_TXF \| FEC_IER_RXF \| FEC_IER_EBERR);
1211
1212	/*
1213	* MIBC - MIB control (hardware stats).
1214	*/
1215	regval = RD4(sc, FEC_MIBC_REG);
1216	WR4(sc, FEC_MIBC_REG, regval \| FEC_MIBC_DIS);
1217	ffec_clear_stats(sc);
1218	WR4(sc, FEC_MIBC_REG, regval & ~FEC_MIBC_DIS);
1219
1220	/*
1221	* ECR - Ethernet control register.
1222	*
1223	* This must happen after all the other config registers are set. If
1224	* we're running on little-endian hardware, also set the flag for byte-
1225	* swapping descriptor ring entries. This flag doesn't exist on older
1226	* hardware, but it can be safely set -- the bit position it occupies
1227	* was unused.
1228	*/
1229	regval = RD4(sc, FEC_ECR_REG);
1230	#if _BYTE_ORDER == _LITTLE_ENDIAN
1231	regval \|= FEC_ECR_DBSWP;
1232	#endif
1233	regval \|= FEC_ECR_ETHEREN;
1234	WR4(sc, FEC_ECR_REG, regval);
1235
1236	ifp->if_drv_flags \|= IFF_DRV_RUNNING;
1237
1238	/*
1239	* Call mii_mediachg() which will call back into ffec_miibus_statchg() to
1240	* set up the remaining config registers based on the current media.
1241	*/
1242	mii_mediachg(sc->mii_softc);
1243	callout_reset(&sc->ffec_callout, hz, ffec_tick, sc);
1244
1245	/*
1246	* Tell the hardware that receive buffers are available. They were made
1247	* available in ffec_attach() or ffec_stop().
1248	*/
1249	WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR);
1250	}
1251
1252	static void
1253	ffec_init(void *if_softc)
1254	{
1255	struct ffec_softc *sc = if_softc;
1256
1257	FFEC_LOCK(sc);
1258	ffec_init_locked(sc);
1259	FFEC_UNLOCK(sc);
1260	}
1261
1262	static void
1263	ffec_intr(void *arg)
1264	{
1265	struct ffec_softc *sc;
1266	uint32_t ier;
1267
1268	sc = arg;
1269
1270	FFEC_LOCK(sc);
1271
1272	ier = RD4(sc, FEC_IER_REG);
1273
1274	if (ier & FEC_IER_TXF) {
1275	WR4(sc, FEC_IER_REG, FEC_IER_TXF);
1276	ffec_txfinish_locked(sc);
1277	}
1278
1279	if (ier & FEC_IER_RXF) {
1280	WR4(sc, FEC_IER_REG, FEC_IER_RXF);
1281	ffec_rxfinish_locked(sc);
1282	}
1283
1284	/*
1285	* We actually don't care about most errors, because the hardware copes
1286	* with them just fine, discarding the incoming bad frame, or forcing a
1287	* bad CRC onto an outgoing bad frame, and counting the errors in the
1288	* stats registers. The one that really matters is EBERR (DMA bus
1289	* error) because the hardware automatically clears ECR[ETHEREN] and we
1290	* have to restart it here. It should never happen.
1291	*/
1292	if (ier & FEC_IER_EBERR) {
1293	WR4(sc, FEC_IER_REG, FEC_IER_EBERR);
1294	device_printf(sc->dev,
1295	"Ethernet DMA error, restarting controller.\n");
1296	ffec_stop_locked(sc);
1297	ffec_init_locked(sc);
1298	}
1299
1300	FFEC_UNLOCK(sc);
1301
1302	}
1303
1304	static int
1305	ffec_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1306	{
1307	struct ffec_softc *sc;
1308	struct mii_data *mii;
1309	struct ifreq *ifr;
1310	int mask, error;
1311
1312	sc = ifp->if_softc;
1313	ifr = (struct ifreq *)data;
1314
1315	error = 0;
1316	switch (cmd) {
1317	case SIOCSIFFLAGS:
1318	FFEC_LOCK(sc);
1319	if (ifp->if_flags & IFF_UP) {
1320	if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1321	if ((ifp->if_flags ^ sc->if_flags) &
1322	(IFF_PROMISC \| IFF_ALLMULTI))
1323	ffec_setup_rxfilter(sc);
1324	} else {
1325	if (!sc->is_detaching)
1326	ffec_init_locked(sc);
1327	}
1328	} else {
1329	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1330	ffec_stop_locked(sc);
1331	}
1332	sc->if_flags = ifp->if_flags;
1333	FFEC_UNLOCK(sc);
1334	break;
1335
1336	case SIOCADDMULTI:
1337	case SIOCDELMULTI:
1338	if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1339	FFEC_LOCK(sc);
1340	ffec_setup_rxfilter(sc);
1341	FFEC_UNLOCK(sc);
1342	}
1343	break;
1344
1345	case SIOCSIFMEDIA:
1346	case SIOCGIFMEDIA:
1347	mii = sc->mii_softc;
1348	error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1349	break;
1350
1351	case SIOCSIFCAP:
1352	mask = ifp->if_capenable ^ ifr->ifr_reqcap;
1353	if (mask & IFCAP_VLAN_MTU) {
1354	/* No work to do except acknowledge the change took. */
1355	ifp->if_capenable ^= IFCAP_VLAN_MTU;
1356	}
1357	break;
1358
1359	default:
1360	error = ether_ioctl(ifp, cmd, data);
1361	break;
1362	}
1363
1364	return (error);
1365	}
1366
1367	static int
1368	ffec_detach(device_t dev)
1369	{
1370	struct ffec_softc *sc;
1371	bus_dmamap_t map;
1372	int idx, irq;
1373
1374	/*
1375	* NB: This function can be called internally to unwind a failure to
1376	* attach. Make sure a resource got allocated/created before destroying.
1377	*/
1378
1379	sc = device_get_softc(dev);
1380
1381	if (sc->is_attached) {
1382	FFEC_LOCK(sc);
1383	sc->is_detaching = true;
1384	ffec_stop_locked(sc);
1385	FFEC_UNLOCK(sc);
1386	callout_drain(&sc->ffec_callout);
1387	ether_ifdetach(sc->ifp);
1388	}
1389
1390	/* XXX no miibus detach? */
1391
1392	/* Clean up RX DMA resources and free mbufs. */
1393	for (idx = 0; idx < RX_DESC_COUNT; ++idx) {
1394	if ((map = sc->rxbuf_map[idx].map) != NULL) {
1395	bus_dmamap_unload(sc->rxbuf_tag, map);
1396	bus_dmamap_destroy(sc->rxbuf_tag, map);
1397	m_freem(sc->rxbuf_map[idx].mbuf);
1398	}
1399	}
1400	if (sc->rxbuf_tag != NULL)
1401	bus_dma_tag_destroy(sc->rxbuf_tag);
1402	if (sc->rxdesc_map != NULL) {
1403	bus_dmamap_unload(sc->rxdesc_tag, sc->rxdesc_map);
1404	bus_dmamap_destroy(sc->rxdesc_tag, sc->rxdesc_map);
1405	}
1406	if (sc->rxdesc_tag != NULL)
1407	bus_dma_tag_destroy(sc->rxdesc_tag);
1408
1409	/* Clean up TX DMA resources. */
1410	for (idx = 0; idx < TX_DESC_COUNT; ++idx) {
1411	if ((map = sc->txbuf_map[idx].map) != NULL) {
1412	/* TX maps are already unloaded. */
1413	bus_dmamap_destroy(sc->txbuf_tag, map);
1414	}
1415	}
1416	if (sc->txbuf_tag != NULL)
1417	bus_dma_tag_destroy(sc->txbuf_tag);
1418	if (sc->txdesc_map != NULL) {
1419	bus_dmamap_unload(sc->txdesc_tag, sc->txdesc_map);
1420	bus_dmamap_destroy(sc->txdesc_tag, sc->txdesc_map);
1421	}
1422	if (sc->txdesc_tag != NULL)
1423	bus_dma_tag_destroy(sc->txdesc_tag);
1424
1425	/* Release bus resources. */
1426	for (irq = 0; irq < sc->irq_count; ++irq) {
1427	if (sc->intr_cookie[irq])
1428	bus_teardown_intr(dev, sc->irq_res[irq],
1429	sc->intr_cookie[irq]);
1430
1431	if (sc->irq_res[irq] != NULL)
1432	bus_release_resource(dev, SYS_RES_IRQ, 0,
1433	sc->irq_res[irq]);
1434	}
1435
1436	if (sc->mem_res != NULL)
1437	bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
1438
1439	FFEC_LOCK_DESTROY(sc);
1440	return (0);
1441	}
1442
1443	static int
1444	ffec_attach(device_t dev)
1445	{
1446	struct ffec_softc *sc;
1447	struct ifnet *ifp = NULL;
1448	struct mbuf *m;
1449	phandle_t ofw_node;
1450	int error, rid, irq;
1451	uint8_t eaddr[ETHER_ADDR_LEN];
1452	char phy_conn_name[32];
1453	uint32_t idx, mscr;
1454
1455	sc = device_get_softc(dev);
1456	sc->dev = dev;
1457
1458	FFEC_LOCK_INIT(sc);
1459
1460	/*
1461	* There are differences in the implementation and features of the FEC
1462	* hardware on different SoCs, so figure out what type we are.
1463	*/
1464	sc->fectype = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
1465
1466	if (sc->fectype & FECFLAG_AVB) {
1467	sc->rxbuf_align = 64;
1468	sc->txbuf_align = 1;
1469	} else {
1470	sc->rxbuf_align = 16;
1471	sc->txbuf_align = 16;
1472	}
1473
1474	/*
1475	* We have to be told what kind of electrical connection exists between
1476	* the MAC and PHY or we can't operate correctly.
1477	*/
1478	if ((ofw_node = ofw_bus_get_node(dev)) == -1) {
1479	device_printf(dev, "Impossible: Can't find ofw bus node\n");
1480	error = ENXIO;
1481	goto out;
1482	}
1483	if (OF_searchprop(ofw_node, "phy-mode",
1484	phy_conn_name, sizeof(phy_conn_name)) != -1) {
1485	if (strcasecmp(phy_conn_name, "mii") == 0)
1486	sc->phy_conn_type = PHY_CONN_MII;
1487	else if (strcasecmp(phy_conn_name, "rmii") == 0)
1488	sc->phy_conn_type = PHY_CONN_RMII;
1489	#ifndef __rtems__
1490	else if (strcasecmp(phy_conn_name, "rgmii") == 0)
1491	#else /* __rtems__ */
1492	else if (strncasecmp(phy_conn_name, "rgmii", 5) == 0)
1493	#endif /* __rtems__ */
1494	sc->phy_conn_type = PHY_CONN_RGMII;
1495	}
1496	if (sc->phy_conn_type == PHY_CONN_UNKNOWN) {
1497	device_printf(sc->dev, "No valid 'phy-mode' "
1498	"property found in FDT data for device.\n");
1499	#ifndef __rtems__
1500	error = ENOATTR;
1501	#else /* __rtems__ */
1502	error = ENXIO;
1503	#endif /* __rtems__ */
1504	goto out;
1505	}
1506
1507	callout_init_mtx(&sc->ffec_callout, &sc->mtx, 0);
1508
1509	/* Allocate bus resources for accessing the hardware. */
1510	rid = 0;
1511	sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1512	RF_ACTIVE);
1513	if (sc->mem_res == NULL) {
1514	device_printf(dev, "could not allocate memory resources.\n");
1515	error = ENOMEM;
1516	goto out;
1517	}
1518	for (irq = 0; irq < MAX_IRQ_COUNT; ++irq) {
1519	rid = irq;
1520	sc->irq_res[irq] = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1521	&rid, RF_ACTIVE);
1522	if (sc->irq_res[irq] == NULL)
1523	break;
1524	}
1525	sc->irq_count = irq;
1526	if (irq == 0) {
1527	device_printf(dev, "could not allocate interrupt resources.\n");
1528	error = ENOMEM;
1529	goto out;
1530	}
1531
1532	/*
1533	* Set up TX descriptor ring, descriptors, and dma maps.
1534	*/
1535	error = bus_dma_tag_create(
1536	bus_get_dma_tag(dev), /* Parent tag. */
1537	FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */
1538	BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1539	BUS_SPACE_MAXADDR, /* highaddr */
1540	NULL, NULL, /* filter, filterarg */
1541	TX_DESC_SIZE, 1, /* maxsize, nsegments */
1542	TX_DESC_SIZE, /* maxsegsize */
1543	0, /* flags */
1544	NULL, NULL, /* lockfunc, lockarg */
1545	&sc->txdesc_tag);
1546	if (error != 0) {
1547	device_printf(sc->dev,
1548	"could not create TX ring DMA tag.\n");
1549	goto out;
1550	}
1551
1552	error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring,
1553	BUS_DMA_COHERENT \| BUS_DMA_WAITOK \| BUS_DMA_ZERO, &sc->txdesc_map);
1554	if (error != 0) {
1555	device_printf(sc->dev,
1556	"could not allocate TX descriptor ring.\n");
1557	goto out;
1558	}
1559
1560	error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, sc->txdesc_ring,
1561	TX_DESC_SIZE, ffec_get1paddr, &sc->txdesc_ring_paddr, 0);
1562	if (error != 0) {
1563	device_printf(sc->dev,
1564	"could not load TX descriptor ring map.\n");
1565	goto out;
1566	}
1567
1568	error = bus_dma_tag_create(
1569	bus_get_dma_tag(dev), /* Parent tag. */
1570	sc->txbuf_align, 0, /* alignment, boundary */
1571	BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1572	BUS_SPACE_MAXADDR, /* highaddr */
1573	NULL, NULL, /* filter, filterarg */
1574	MCLBYTES, 1, /* maxsize, nsegments */
1575	MCLBYTES, /* maxsegsize */
1576	0, /* flags */
1577	NULL, NULL, /* lockfunc, lockarg */
1578	&sc->txbuf_tag);
1579	if (error != 0) {
1580	device_printf(sc->dev,
1581	"could not create TX ring DMA tag.\n");
1582	goto out;
1583	}
1584
1585	for (idx = 0; idx < TX_DESC_COUNT; ++idx) {
1586	error = bus_dmamap_create(sc->txbuf_tag, 0,
1587	&sc->txbuf_map[idx].map);
1588	if (error != 0) {
1589	device_printf(sc->dev,
1590	"could not create TX buffer DMA map.\n");
1591	goto out;
1592	}
1593	ffec_setup_txdesc(sc, idx, 0, 0);
1594	}
1595
1596	/*
1597	* Set up RX descriptor ring, descriptors, dma maps, and mbufs.
1598	*/
1599	error = bus_dma_tag_create(
1600	bus_get_dma_tag(dev), /* Parent tag. */
1601	FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */
1602	BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1603	BUS_SPACE_MAXADDR, /* highaddr */
1604	NULL, NULL, /* filter, filterarg */
1605	RX_DESC_SIZE, 1, /* maxsize, nsegments */
1606	RX_DESC_SIZE, /* maxsegsize */
1607	0, /* flags */
1608	NULL, NULL, /* lockfunc, lockarg */
1609	&sc->rxdesc_tag);
1610	if (error != 0) {
1611	device_printf(sc->dev,
1612	"could not create RX ring DMA tag.\n");
1613	goto out;
1614	}
1615
1616	error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring,
1617	BUS_DMA_COHERENT \| BUS_DMA_WAITOK \| BUS_DMA_ZERO, &sc->rxdesc_map);
1618	if (error != 0) {
1619	device_printf(sc->dev,
1620	"could not allocate RX descriptor ring.\n");
1621	goto out;
1622	}
1623
1624	error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, sc->rxdesc_ring,
1625	RX_DESC_SIZE, ffec_get1paddr, &sc->rxdesc_ring_paddr, 0);
1626	if (error != 0) {
1627	device_printf(sc->dev,
1628	"could not load RX descriptor ring map.\n");
1629	goto out;
1630	}
1631
1632	error = bus_dma_tag_create(
1633	bus_get_dma_tag(dev), /* Parent tag. */
1634	1, 0, /* alignment, boundary */
1635	BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1636	BUS_SPACE_MAXADDR, /* highaddr */
1637	NULL, NULL, /* filter, filterarg */
1638	MCLBYTES, 1, /* maxsize, nsegments */
1639	MCLBYTES, /* maxsegsize */
1640	0, /* flags */
1641	NULL, NULL, /* lockfunc, lockarg */
1642	&sc->rxbuf_tag);
1643	if (error != 0) {
1644	device_printf(sc->dev,
1645	"could not create RX buf DMA tag.\n");
1646	goto out;
1647	}
1648
1649	for (idx = 0; idx < RX_DESC_COUNT; ++idx) {
1650	error = bus_dmamap_create(sc->rxbuf_tag, 0,
1651	&sc->rxbuf_map[idx].map);
1652	if (error != 0) {
1653	device_printf(sc->dev,
1654	"could not create RX buffer DMA map.\n");
1655	goto out;
1656	}
1657	if ((m = ffec_alloc_mbufcl(sc)) == NULL) {
1658	device_printf(dev, "Could not alloc mbuf\n");
1659	error = ENOMEM;
1660	goto out;
1661	}
1662	if ((error = ffec_setup_rxbuf(sc, idx, m)) != 0) {
1663	device_printf(sc->dev,
1664	"could not create new RX buffer.\n");
1665	goto out;
1666	}
1667	}
1668
1669	/* Try to get the MAC address from the hardware before resetting it. */
1670	ffec_get_hwaddr(sc, eaddr);
1671
1672	/* Reset the hardware. Disables all interrupts. */
1673	if (sc->fectype & FECFLAG_AVB)
1674	/*
1675	* Avoid AXI bus issues due to a MAC reset, see Linux for more
1676	* details.
1677	*/
1678	WR4(sc, FEC_ECR_REG, 0);
1679	else
1680	WR4(sc, FEC_ECR_REG, FEC_ECR_RESET);
1681
1682	/* Setup interrupt handler. */
1683	for (irq = 0; irq < sc->irq_count; ++irq) {
1684	error = bus_setup_intr(dev, sc->irq_res[irq],
1685	INTR_TYPE_NET \| INTR_MPSAFE, NULL, ffec_intr, sc,
1686	&sc->intr_cookie[irq]);
1687	if (error != 0) {
1688	device_printf(dev,
1689	"could not setup interrupt handler.\n");
1690	goto out;
1691	}
1692	}
1693
1694	/*
1695	* Set up the PHY control register.
1696	*
1697	* Speed formula for ENET is md_clock = mac_clock / ((N + 1) * 2).
1698	* Speed formula for FEC is md_clock = mac_clock / (N * 2)
1699	*
1700	* XXX - Revisit this...
1701	*
1702	* For a Wandboard imx6 (ENET) I was originally using 4, but the uboot
1703	* code uses 10. Both values seem to work, but I suspect many modern
1704	* PHY parts can do mdio at speeds far above the standard 2.5 MHz.
1705	*
1706	* Different imx manuals use confusingly different terminology (things
1707	* like "system clock" and "internal module clock") with examples that
1708	* use frequencies that have nothing to do with ethernet, giving the
1709	* vague impression that maybe the clock in question is the periphclock
1710	* or something. In fact, on an imx53 development board (FEC),
1711	* measuring the mdio clock at the pin on the PHY and playing with
1712	* various divisors showed that the root speed was 66 MHz (clk_ipg_root
1713	* aka periphclock) and 13 was the right divisor.
1714	*
1715	* All in all, it seems likely that 13 is a safe divisor for now,
1716	* because if we really do need to base it on the peripheral clock
1717	* speed, then we need a platform-independant get-clock-freq API.
1718	*/
1719	mscr = 13 << FEC_MSCR_MII_SPEED_SHIFT;
1720	if (OF_hasprop(ofw_node, "phy-disable-preamble")) {
1721	mscr \|= FEC_MSCR_DIS_PRE;
1722	if (bootverbose)
1723	device_printf(dev, "PHY preamble disabled\n");
1724	}
1725	WR4(sc, FEC_MSCR_REG, mscr);
1726
1727	/* Set up the ethernet interface. */
1728	sc->ifp = ifp = if_alloc(IFT_ETHER);
1729
1730	ifp->if_softc = sc;
1731	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1732	ifp->if_flags = IFF_BROADCAST \| IFF_SIMPLEX \| IFF_MULTICAST;
1733	ifp->if_capabilities = IFCAP_VLAN_MTU;
1734	ifp->if_capenable = ifp->if_capabilities;
1735	ifp->if_start = ffec_txstart;
1736	ifp->if_ioctl = ffec_ioctl;
1737	ifp->if_init = ffec_init;
1738	IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1);
1739	ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1;
1740	IFQ_SET_READY(&ifp->if_snd);
1741	ifp->if_hdrlen = sizeof(struct ether_vlan_header);
1742
1743	#if 0 /* XXX The hardware keeps stats we could use for these. */
1744	ifp->if_linkmib = &sc->mibdata;
1745	ifp->if_linkmiblen = sizeof(sc->mibdata);
1746	#endif
1747
1748	/* Set up the miigasket hardware (if any). */
1749	ffec_miigasket_setup(sc);
1750
1751	/* Attach the mii driver. */
1752	error = mii_attach(dev, &sc->miibus, ifp, ffec_media_change,
1753	ffec_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY,
1754	(sc->fectype & FECTYPE_MVF) ? MIIF_FORCEANEG : 0);
1755	if (error != 0) {
1756	device_printf(dev, "PHY attach failed\n");
1757	goto out;
1758	}
1759	sc->mii_softc = device_get_softc(sc->miibus);
1760
1761	/* All ready to run, attach the ethernet interface. */
1762	ether_ifattach(ifp, eaddr);
1763	sc->is_attached = true;
1764
1765	error = 0;
1766	out:
1767
1768	if (error != 0)
1769	ffec_detach(dev);
1770
1771	return (error);
1772	}
1773
1774	static int
1775	ffec_probe(device_t dev)
1776	{
1777	uintptr_t fectype;
1778
1779	if (!ofw_bus_status_okay(dev))
1780	return (ENXIO);
1781
1782	fectype = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
1783	if (fectype == FECTYPE_NONE)
1784	return (ENXIO);
1785
1786	device_set_desc(dev, (fectype & FECFLAG_GBE) ?
1787	"Freescale Gigabit Ethernet Controller" :
1788	"Freescale Fast Ethernet Controller");
1789
1790	return (BUS_PROBE_DEFAULT);
1791	}
1792
1793
1794	static device_method_t ffec_methods[] = {
1795	/* Device interface. */
1796	DEVMETHOD(device_probe, ffec_probe),
1797	DEVMETHOD(device_attach, ffec_attach),
1798	DEVMETHOD(device_detach, ffec_detach),
1799
1800	/*
1801	DEVMETHOD(device_shutdown, ffec_shutdown),
1802	DEVMETHOD(device_suspend, ffec_suspend),
1803	DEVMETHOD(device_resume, ffec_resume),
1804	*/
1805
1806	/* MII interface. */
1807	DEVMETHOD(miibus_readreg, ffec_miibus_readreg),
1808	DEVMETHOD(miibus_writereg, ffec_miibus_writereg),
1809	DEVMETHOD(miibus_statchg, ffec_miibus_statchg),
1810
1811	DEVMETHOD_END
1812	};
1813
1814	static driver_t ffec_driver = {
1815	"ffec",
1816	ffec_methods,
1817	sizeof(struct ffec_softc)
1818	};
1819
1820	static devclass_t ffec_devclass;
1821
1822	DRIVER_MODULE(ffec, simplebus, ffec_driver, ffec_devclass, 0, 0);
1823	DRIVER_MODULE(miibus, ffec, miibus_driver, miibus_devclass, 0, 0);
1824
1825	MODULE_DEPEND(ffec, ether, 1, 1, 1);
1826	MODULE_DEPEND(ffec, miibus, 1, 1, 1);

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