1 | #include <machine/rtems-bsd-kernel-space.h> |
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2 | |
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3 | /*- |
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4 | * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> |
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5 | * Copyright (C) 2007-2008 Semihalf, Rafal Jaworowski |
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6 | * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski |
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7 | * All rights reserved. |
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8 | * |
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9 | * Redistribution and use in source and binary forms, with or without |
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10 | * modification, are permitted provided that the following conditions |
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11 | * are met: |
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12 | * 1. Redistributions of source code must retain the above copyright |
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13 | * notice, this list of conditions and the following disclaimer. |
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14 | * 2. Redistributions in binary form must reproduce the above copyright |
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15 | * notice, this list of conditions and the following disclaimer in the |
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16 | * documentation and/or other materials provided with the distribution. |
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17 | * |
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18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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19 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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22 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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23 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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24 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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25 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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26 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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27 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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28 | * SUCH DAMAGE. |
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29 | * |
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30 | */ |
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31 | |
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32 | #include <sys/cdefs.h> |
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33 | __FBSDID("$FreeBSD$"); |
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34 | |
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35 | /* |
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36 | * Driver for Freescale Fast Ethernet Controller, found on imx-series SoCs among |
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37 | * others. Also works for the ENET Gigibit controller found on imx6 and imx28, |
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38 | * but the driver doesn't currently use any of the ENET advanced features other |
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39 | * than enabling gigabit. |
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40 | * |
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41 | * The interface name 'fec' is already taken by netgraph's Fast Etherchannel |
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42 | * (netgraph/ng_fec.c), so we use 'ffec'. |
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43 | * |
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44 | * Requires an FDT entry with at least these properties: |
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45 | * fec: ethernet@02188000 { |
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46 | * compatible = "fsl,imxNN-fec"; |
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47 | * reg = <0x02188000 0x4000>; |
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48 | * interrupts = <150 151>; |
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49 | * phy-mode = "rgmii"; |
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50 | * phy-disable-preamble; // optional |
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51 | * }; |
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52 | * The second interrupt number is for IEEE-1588, and is not currently used; it |
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53 | * need not be present. phy-mode must be one of: "mii", "rmii", "rgmii". |
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54 | * There is also an optional property, phy-disable-preamble, which if present |
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55 | * will disable the preamble bits, cutting the size of each mdio transaction |
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56 | * (and thus the busy-wait time) in half. |
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57 | */ |
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58 | |
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59 | #include <sys/param.h> |
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60 | #include <sys/systm.h> |
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61 | #include <sys/bus.h> |
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62 | #include <sys/endian.h> |
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63 | #include <sys/kernel.h> |
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64 | #include <sys/lock.h> |
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65 | #include <sys/malloc.h> |
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66 | #include <sys/mbuf.h> |
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67 | #include <sys/module.h> |
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68 | #include <sys/mutex.h> |
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69 | #include <sys/rman.h> |
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70 | #include <sys/socket.h> |
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71 | #include <sys/sockio.h> |
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72 | #include <sys/sysctl.h> |
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73 | |
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74 | #include <machine/bus.h> |
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75 | |
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76 | #include <net/bpf.h> |
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77 | #include <net/if.h> |
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78 | #include <net/ethernet.h> |
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79 | #include <net/if_dl.h> |
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80 | #include <net/if_media.h> |
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81 | #include <net/if_types.h> |
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82 | #include <net/if_var.h> |
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83 | #include <net/if_vlan_var.h> |
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84 | #include <netinet/in.h> |
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85 | #include <netinet/ip.h> |
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86 | |
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87 | #include <dev/ffec/if_ffecreg.h> |
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88 | #include <dev/ofw/ofw_bus.h> |
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89 | #include <dev/ofw/ofw_bus_subr.h> |
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90 | #include <dev/mii/mii.h> |
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91 | #include <dev/mii/miivar.h> |
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92 | #include <rtems/bsd/local/miibus_if.h> |
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93 | |
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94 | /* |
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95 | * There are small differences in the hardware on various SoCs. Not every SoC |
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96 | * we support has its own FECTYPE; most work as GENERIC and only the ones that |
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97 | * need different handling get their own entry. In addition to the types in |
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98 | * this list, there are some flags below that can be ORed into the upper bits. |
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99 | */ |
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100 | enum { |
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101 | FECTYPE_NONE, |
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102 | FECTYPE_GENERIC, |
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103 | FECTYPE_IMX53, |
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104 | FECTYPE_IMX6, |
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105 | FECTYPE_MVF, |
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106 | }; |
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107 | |
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108 | /* |
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109 | * Flags that describe general differences between the FEC hardware in various |
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110 | * SoCs. These are ORed into the FECTYPE enum values. |
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111 | */ |
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112 | #define FECTYPE_MASK 0x0000ffff |
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113 | #define FECFLAG_GBE (1 << 16) |
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114 | #define FECFLAG_AVB (1 << 17) |
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115 | #define FECFLAG_RACC (1 << 18) |
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116 | |
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117 | /* |
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118 | * Table of supported FDT compat strings and their associated FECTYPE values. |
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119 | */ |
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120 | static struct ofw_compat_data compat_data[] = { |
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121 | {"fsl,imx51-fec", FECTYPE_GENERIC}, |
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122 | {"fsl,imx53-fec", FECTYPE_IMX53}, |
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123 | {"fsl,imx6q-fec", FECTYPE_IMX6 | FECFLAG_GBE | FECFLAG_RACC}, |
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124 | {"fsl,mvf600-fec", FECTYPE_MVF | FECFLAG_RACC}, |
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125 | {"fsl,mvf-fec", FECTYPE_MVF}, |
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126 | {"fsl,imx7d-fec", FECTYPE_IMX6 | FECFLAG_GBE | FECFLAG_AVB | |
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127 | FECFLAG_RACC}, |
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128 | {NULL, FECTYPE_NONE}, |
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129 | }; |
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130 | |
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131 | /* |
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132 | * Driver data and defines. The descriptor counts must be a power of two. |
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133 | */ |
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134 | #define RX_DESC_COUNT 512 |
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135 | #define RX_DESC_SIZE (sizeof(struct ffec_hwdesc) * RX_DESC_COUNT) |
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136 | #define TX_DESC_COUNT 512 |
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137 | #define TX_DESC_SIZE (sizeof(struct ffec_hwdesc) * TX_DESC_COUNT) |
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138 | #define TX_MAX_DMA_SEGS 8 |
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139 | |
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140 | #define WATCHDOG_TIMEOUT_SECS 5 |
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141 | #define STATS_HARVEST_INTERVAL 3 |
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142 | |
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143 | #define MAX_IRQ_COUNT 3 |
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144 | |
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145 | /* Interrupt Coalescing types */ |
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146 | #define FEC_IC_RX 0 |
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147 | #define FEC_IC_TX 1 |
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148 | |
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149 | struct ffec_bufmap { |
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150 | struct mbuf *mbuf; |
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151 | bus_dmamap_t map; |
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152 | }; |
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153 | |
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154 | enum { |
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155 | PHY_CONN_UNKNOWN, |
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156 | PHY_CONN_MII, |
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157 | PHY_CONN_RMII, |
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158 | PHY_CONN_RGMII |
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159 | }; |
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160 | |
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161 | struct ffec_softc { |
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162 | device_t dev; |
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163 | device_t miibus; |
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164 | struct mii_data * mii_softc; |
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165 | struct ifnet *ifp; |
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166 | int if_flags; |
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167 | struct mtx mtx; |
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168 | struct resource *irq_res[MAX_IRQ_COUNT]; |
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169 | int irq_count; |
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170 | struct resource *mem_res; |
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171 | void * intr_cookie[MAX_IRQ_COUNT]; |
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172 | struct callout ffec_callout; |
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173 | uint8_t phy_conn_type; |
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174 | uintptr_t fectype; |
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175 | boolean_t link_is_up; |
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176 | boolean_t is_attached; |
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177 | boolean_t is_detaching; |
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178 | int tx_watchdog_count; |
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179 | int stats_harvest_count; |
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180 | int rxbuf_align; |
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181 | int txbuf_align; |
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182 | |
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183 | bus_dma_tag_t rxdesc_tag; |
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184 | bus_dmamap_t rxdesc_map; |
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185 | struct ffec_hwdesc *rxdesc_ring; |
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186 | bus_addr_t rxdesc_ring_paddr; |
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187 | bus_dma_tag_t rxbuf_tag; |
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188 | struct ffec_bufmap rxbuf_map[RX_DESC_COUNT]; |
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189 | uint32_t rx_idx; |
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190 | |
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191 | bus_dma_tag_t txdesc_tag; |
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192 | bus_dmamap_t txdesc_map; |
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193 | struct ffec_hwdesc *txdesc_ring; |
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194 | bus_addr_t txdesc_ring_paddr; |
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195 | bus_dma_tag_t txbuf_tag; |
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196 | struct ffec_bufmap txbuf_map[TX_DESC_COUNT]; |
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197 | uint32_t tx_idx_head; |
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198 | uint32_t tx_idx_tail; |
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199 | |
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200 | /* interrupt coalescing */ |
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201 | int rx_ic_time; /* RW, valid values 0..65535 */ |
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202 | int rx_ic_count; /* RW, valid values 0..255 */ |
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203 | int tx_ic_time; |
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204 | int tx_ic_count; |
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205 | }; |
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206 | |
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207 | #define FFEC_LOCK(sc) mtx_lock(&(sc)->mtx) |
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208 | #define FFEC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) |
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209 | #define FFEC_LOCK_INIT(sc) mtx_init(&(sc)->mtx, \ |
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210 | device_get_nameunit((sc)->dev), MTX_NETWORK_LOCK, MTX_DEF) |
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211 | #define FFEC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx); |
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212 | #define FFEC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED); |
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213 | #define FFEC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED); |
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214 | |
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215 | static void ffec_init_locked(struct ffec_softc *sc); |
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216 | static void ffec_stop_locked(struct ffec_softc *sc); |
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217 | static void ffec_encap(struct ifnet *ifp, struct ffec_softc *sc, |
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218 | struct mbuf *m0, int *start_tx); |
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219 | static void ffec_txstart_locked(struct ffec_softc *sc); |
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220 | static void ffec_txfinish_locked(struct ffec_softc *sc); |
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221 | static void ffec_add_sysctls(struct ffec_softc *sc); |
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222 | static int ffec_sysctl_ic_time(SYSCTL_HANDLER_ARGS); |
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223 | static int ffec_sysctl_ic_count(SYSCTL_HANDLER_ARGS); |
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224 | static void ffec_set_ic(struct ffec_softc *sc, bus_size_t off, int count, |
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225 | int time); |
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226 | static void ffec_set_rxic(struct ffec_softc *sc); |
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227 | static void ffec_set_txic(struct ffec_softc *sc); |
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228 | |
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229 | static inline uint16_t |
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230 | RD2(struct ffec_softc *sc, bus_size_t off) |
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231 | { |
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232 | |
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233 | return (bus_read_2(sc->mem_res, off)); |
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234 | } |
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235 | |
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236 | static inline void |
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237 | WR2(struct ffec_softc *sc, bus_size_t off, uint16_t val) |
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238 | { |
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239 | |
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240 | bus_write_2(sc->mem_res, off, val); |
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241 | } |
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242 | |
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243 | static inline uint32_t |
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244 | RD4(struct ffec_softc *sc, bus_size_t off) |
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245 | { |
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246 | |
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247 | return (bus_read_4(sc->mem_res, off)); |
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248 | } |
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249 | |
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250 | static inline void |
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251 | WR4(struct ffec_softc *sc, bus_size_t off, uint32_t val) |
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252 | { |
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253 | |
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254 | bus_write_4(sc->mem_res, off, val); |
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255 | } |
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256 | |
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257 | static inline uint32_t |
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258 | next_rxidx(uint32_t curidx) |
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259 | { |
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260 | |
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261 | return ((curidx + 1) & (RX_DESC_COUNT - 1)); |
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262 | } |
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263 | |
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264 | static inline uint32_t |
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265 | next_txidx(uint32_t curidx) |
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266 | { |
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267 | |
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268 | return ((curidx + 1) & (TX_DESC_COUNT - 1)); |
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269 | } |
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270 | |
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271 | static inline uint32_t |
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272 | prev_txidx(uint32_t curidx) |
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273 | { |
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274 | |
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275 | return ((curidx - 1) & (TX_DESC_COUNT - 1)); |
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276 | } |
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277 | |
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278 | static inline uint32_t |
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279 | inc_txidx(uint32_t curidx, uint32_t inc) |
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280 | { |
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281 | |
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282 | return ((curidx + inc) & (TX_DESC_COUNT - 1)); |
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283 | } |
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284 | |
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285 | static inline uint32_t |
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286 | free_txdesc(struct ffec_softc *sc) |
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287 | { |
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288 | |
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289 | return (((sc)->tx_idx_tail - (sc)->tx_idx_head - 1) & |
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290 | (TX_DESC_COUNT - 1)); |
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291 | } |
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292 | |
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293 | static void |
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294 | ffec_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) |
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295 | { |
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296 | |
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297 | if (error != 0) |
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298 | return; |
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299 | *(bus_addr_t *)arg = segs[0].ds_addr; |
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300 | } |
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301 | |
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302 | static void |
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303 | ffec_miigasket_setup(struct ffec_softc *sc) |
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304 | { |
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305 | uint32_t ifmode; |
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306 | |
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307 | /* |
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308 | * We only need the gasket for MII and RMII connections on certain SoCs. |
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309 | */ |
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310 | |
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311 | switch (sc->fectype & FECTYPE_MASK) |
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312 | { |
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313 | case FECTYPE_IMX53: |
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314 | break; |
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315 | default: |
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316 | return; |
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317 | } |
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318 | |
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319 | switch (sc->phy_conn_type) |
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320 | { |
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321 | case PHY_CONN_MII: |
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322 | ifmode = 0; |
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323 | break; |
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324 | case PHY_CONN_RMII: |
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325 | ifmode = FEC_MIIGSK_CFGR_IF_MODE_RMII; |
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326 | break; |
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327 | default: |
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328 | return; |
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329 | } |
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330 | |
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331 | /* |
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332 | * Disable the gasket, configure for either MII or RMII, then enable. |
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333 | */ |
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334 | |
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335 | WR2(sc, FEC_MIIGSK_ENR, 0); |
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336 | while (RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY) |
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337 | continue; |
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338 | |
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339 | WR2(sc, FEC_MIIGSK_CFGR, ifmode); |
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340 | |
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341 | WR2(sc, FEC_MIIGSK_ENR, FEC_MIIGSK_ENR_EN); |
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342 | while (!(RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY)) |
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343 | continue; |
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344 | } |
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345 | |
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346 | static boolean_t |
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347 | ffec_miibus_iowait(struct ffec_softc *sc) |
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348 | { |
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349 | uint32_t timeout; |
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350 | |
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351 | for (timeout = 10000; timeout != 0; --timeout) |
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352 | if (RD4(sc, FEC_IER_REG) & FEC_IER_MII) |
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353 | return (true); |
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354 | |
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355 | return (false); |
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356 | } |
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357 | |
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358 | static int |
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359 | ffec_miibus_readreg(device_t dev, int phy, int reg) |
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360 | { |
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361 | struct ffec_softc *sc; |
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362 | int val; |
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363 | |
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364 | sc = device_get_softc(dev); |
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365 | |
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366 | WR4(sc, FEC_IER_REG, FEC_IER_MII); |
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367 | |
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368 | WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_READ | |
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369 | FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE | |
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370 | ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) | |
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371 | ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK)); |
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372 | |
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373 | if (!ffec_miibus_iowait(sc)) { |
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374 | device_printf(dev, "timeout waiting for mii read\n"); |
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375 | return (-1); /* All-ones is a symptom of bad mdio. */ |
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376 | } |
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377 | |
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378 | val = RD4(sc, FEC_MMFR_REG) & FEC_MMFR_DATA_MASK; |
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379 | |
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380 | return (val); |
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381 | } |
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382 | |
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383 | static int |
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384 | ffec_miibus_writereg(device_t dev, int phy, int reg, int val) |
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385 | { |
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386 | struct ffec_softc *sc; |
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387 | |
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388 | sc = device_get_softc(dev); |
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389 | |
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390 | WR4(sc, FEC_IER_REG, FEC_IER_MII); |
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391 | |
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392 | WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_WRITE | |
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393 | FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE | |
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394 | ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) | |
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395 | ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK) | |
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396 | (val & FEC_MMFR_DATA_MASK)); |
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397 | |
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398 | if (!ffec_miibus_iowait(sc)) { |
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399 | device_printf(dev, "timeout waiting for mii write\n"); |
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400 | return (-1); |
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401 | } |
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402 | |
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403 | return (0); |
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404 | } |
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405 | |
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406 | static void |
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407 | ffec_miibus_statchg(device_t dev) |
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408 | { |
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409 | struct ffec_softc *sc; |
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410 | struct mii_data *mii; |
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411 | uint32_t ecr, rcr, tcr; |
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412 | |
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413 | /* |
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414 | * Called by the MII bus driver when the PHY establishes link to set the |
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415 | * MAC interface registers. |
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416 | */ |
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417 | |
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418 | sc = device_get_softc(dev); |
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419 | |
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420 | FFEC_ASSERT_LOCKED(sc); |
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421 | |
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422 | mii = sc->mii_softc; |
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423 | |
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424 | if (mii->mii_media_status & IFM_ACTIVE) |
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425 | sc->link_is_up = true; |
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426 | else |
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427 | sc->link_is_up = false; |
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428 | |
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429 | ecr = RD4(sc, FEC_ECR_REG) & ~FEC_ECR_SPEED; |
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430 | rcr = RD4(sc, FEC_RCR_REG) & ~(FEC_RCR_RMII_10T | FEC_RCR_RMII_MODE | |
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431 | FEC_RCR_RGMII_EN | FEC_RCR_DRT | FEC_RCR_FCE); |
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432 | tcr = RD4(sc, FEC_TCR_REG) & ~FEC_TCR_FDEN; |
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433 | |
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434 | rcr |= FEC_RCR_MII_MODE; /* Must always be on even for R[G]MII. */ |
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435 | switch (sc->phy_conn_type) { |
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436 | case PHY_CONN_MII: |
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437 | break; |
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438 | case PHY_CONN_RMII: |
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439 | rcr |= FEC_RCR_RMII_MODE; |
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440 | break; |
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441 | case PHY_CONN_RGMII: |
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442 | rcr |= FEC_RCR_RGMII_EN; |
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443 | break; |
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444 | } |
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445 | |
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446 | switch (IFM_SUBTYPE(mii->mii_media_active)) { |
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447 | case IFM_1000_T: |
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448 | case IFM_1000_SX: |
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449 | ecr |= FEC_ECR_SPEED; |
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450 | break; |
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451 | case IFM_100_TX: |
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452 | /* Not-FEC_ECR_SPEED + not-FEC_RCR_RMII_10T means 100TX */ |
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453 | break; |
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454 | case IFM_10_T: |
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455 | rcr |= FEC_RCR_RMII_10T; |
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456 | break; |
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457 | case IFM_NONE: |
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458 | sc->link_is_up = false; |
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459 | return; |
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460 | default: |
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461 | sc->link_is_up = false; |
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462 | device_printf(dev, "Unsupported media %u\n", |
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463 | IFM_SUBTYPE(mii->mii_media_active)); |
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464 | return; |
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465 | } |
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466 | |
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467 | if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) |
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468 | tcr |= FEC_TCR_FDEN; |
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469 | else |
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470 | rcr |= FEC_RCR_DRT; |
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471 | |
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472 | if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLOW) != 0) |
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473 | rcr |= FEC_RCR_FCE; |
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474 | |
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475 | WR4(sc, FEC_RCR_REG, rcr); |
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476 | WR4(sc, FEC_TCR_REG, tcr); |
---|
477 | WR4(sc, FEC_ECR_REG, ecr); |
---|
478 | } |
---|
479 | |
---|
480 | static void |
---|
481 | ffec_media_status(struct ifnet * ifp, struct ifmediareq *ifmr) |
---|
482 | { |
---|
483 | struct ffec_softc *sc; |
---|
484 | struct mii_data *mii; |
---|
485 | |
---|
486 | |
---|
487 | sc = ifp->if_softc; |
---|
488 | mii = sc->mii_softc; |
---|
489 | FFEC_LOCK(sc); |
---|
490 | mii_pollstat(mii); |
---|
491 | ifmr->ifm_active = mii->mii_media_active; |
---|
492 | ifmr->ifm_status = mii->mii_media_status; |
---|
493 | FFEC_UNLOCK(sc); |
---|
494 | } |
---|
495 | |
---|
496 | static int |
---|
497 | ffec_media_change_locked(struct ffec_softc *sc) |
---|
498 | { |
---|
499 | |
---|
500 | return (mii_mediachg(sc->mii_softc)); |
---|
501 | } |
---|
502 | |
---|
503 | static int |
---|
504 | ffec_media_change(struct ifnet * ifp) |
---|
505 | { |
---|
506 | struct ffec_softc *sc; |
---|
507 | int error; |
---|
508 | |
---|
509 | sc = ifp->if_softc; |
---|
510 | |
---|
511 | FFEC_LOCK(sc); |
---|
512 | error = ffec_media_change_locked(sc); |
---|
513 | FFEC_UNLOCK(sc); |
---|
514 | return (error); |
---|
515 | } |
---|
516 | |
---|
517 | static void ffec_clear_stats(struct ffec_softc *sc) |
---|
518 | { |
---|
519 | |
---|
520 | WR4(sc, FEC_RMON_R_PACKETS, 0); |
---|
521 | WR4(sc, FEC_RMON_R_MC_PKT, 0); |
---|
522 | WR4(sc, FEC_RMON_R_CRC_ALIGN, 0); |
---|
523 | WR4(sc, FEC_RMON_R_UNDERSIZE, 0); |
---|
524 | WR4(sc, FEC_RMON_R_OVERSIZE, 0); |
---|
525 | WR4(sc, FEC_RMON_R_FRAG, 0); |
---|
526 | WR4(sc, FEC_RMON_R_JAB, 0); |
---|
527 | WR4(sc, FEC_RMON_T_PACKETS, 0); |
---|
528 | WR4(sc, FEC_RMON_T_MC_PKT, 0); |
---|
529 | WR4(sc, FEC_RMON_T_CRC_ALIGN, 0); |
---|
530 | WR4(sc, FEC_RMON_T_UNDERSIZE, 0); |
---|
531 | WR4(sc, FEC_RMON_T_OVERSIZE , 0); |
---|
532 | WR4(sc, FEC_RMON_T_FRAG, 0); |
---|
533 | WR4(sc, FEC_RMON_T_JAB, 0); |
---|
534 | WR4(sc, FEC_RMON_T_COL, 0); |
---|
535 | } |
---|
536 | |
---|
537 | static void |
---|
538 | ffec_harvest_stats(struct ffec_softc *sc) |
---|
539 | { |
---|
540 | struct ifnet *ifp; |
---|
541 | |
---|
542 | /* We don't need to harvest too often. */ |
---|
543 | if (++sc->stats_harvest_count < STATS_HARVEST_INTERVAL) |
---|
544 | return; |
---|
545 | |
---|
546 | /* |
---|
547 | * Try to avoid harvesting unless the IDLE flag is on, but if it has |
---|
548 | * been too long just go ahead and do it anyway, the worst that'll |
---|
549 | * happen is we'll lose a packet count or two as we clear at the end. |
---|
550 | */ |
---|
551 | if (sc->stats_harvest_count < (2 * STATS_HARVEST_INTERVAL) && |
---|
552 | ((RD4(sc, FEC_MIBC_REG) & FEC_MIBC_IDLE) == 0)) |
---|
553 | return; |
---|
554 | |
---|
555 | sc->stats_harvest_count = 0; |
---|
556 | ifp = sc->ifp; |
---|
557 | |
---|
558 | if_inc_counter(ifp, IFCOUNTER_IPACKETS, RD4(sc, FEC_RMON_R_PACKETS)); |
---|
559 | if_inc_counter(ifp, IFCOUNTER_IMCASTS, RD4(sc, FEC_RMON_R_MC_PKT)); |
---|
560 | if_inc_counter(ifp, IFCOUNTER_IERRORS, |
---|
561 | RD4(sc, FEC_RMON_R_CRC_ALIGN) + RD4(sc, FEC_RMON_R_UNDERSIZE) + |
---|
562 | RD4(sc, FEC_RMON_R_OVERSIZE) + RD4(sc, FEC_RMON_R_FRAG) + |
---|
563 | RD4(sc, FEC_RMON_R_JAB)); |
---|
564 | |
---|
565 | if_inc_counter(ifp, IFCOUNTER_OPACKETS, RD4(sc, FEC_RMON_T_PACKETS)); |
---|
566 | if_inc_counter(ifp, IFCOUNTER_OMCASTS, RD4(sc, FEC_RMON_T_MC_PKT)); |
---|
567 | if_inc_counter(ifp, IFCOUNTER_OERRORS, |
---|
568 | RD4(sc, FEC_RMON_T_CRC_ALIGN) + RD4(sc, FEC_RMON_T_UNDERSIZE) + |
---|
569 | RD4(sc, FEC_RMON_T_OVERSIZE) + RD4(sc, FEC_RMON_T_FRAG) + |
---|
570 | RD4(sc, FEC_RMON_T_JAB)); |
---|
571 | |
---|
572 | if_inc_counter(ifp, IFCOUNTER_COLLISIONS, RD4(sc, FEC_RMON_T_COL)); |
---|
573 | |
---|
574 | ffec_clear_stats(sc); |
---|
575 | } |
---|
576 | |
---|
577 | static void |
---|
578 | ffec_tick(void *arg) |
---|
579 | { |
---|
580 | struct ffec_softc *sc; |
---|
581 | struct ifnet *ifp; |
---|
582 | int link_was_up; |
---|
583 | |
---|
584 | sc = arg; |
---|
585 | |
---|
586 | FFEC_ASSERT_LOCKED(sc); |
---|
587 | |
---|
588 | ifp = sc->ifp; |
---|
589 | |
---|
590 | if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) |
---|
591 | return; |
---|
592 | |
---|
593 | /* |
---|
594 | * Typical tx watchdog. If this fires it indicates that we enqueued |
---|
595 | * packets for output and never got a txdone interrupt for them. Maybe |
---|
596 | * it's a missed interrupt somehow, just pretend we got one. |
---|
597 | */ |
---|
598 | if (sc->tx_watchdog_count > 0) { |
---|
599 | if (--sc->tx_watchdog_count == 0) { |
---|
600 | ffec_txfinish_locked(sc); |
---|
601 | } |
---|
602 | } |
---|
603 | |
---|
604 | /* Gather stats from hardware counters. */ |
---|
605 | ffec_harvest_stats(sc); |
---|
606 | |
---|
607 | /* Check the media status. */ |
---|
608 | link_was_up = sc->link_is_up; |
---|
609 | mii_tick(sc->mii_softc); |
---|
610 | if (sc->link_is_up && !link_was_up) |
---|
611 | ffec_txstart_locked(sc); |
---|
612 | |
---|
613 | /* Schedule another check one second from now. */ |
---|
614 | callout_reset(&sc->ffec_callout, hz, ffec_tick, sc); |
---|
615 | } |
---|
616 | |
---|
617 | static void |
---|
618 | ffec_encap(struct ifnet *ifp, struct ffec_softc *sc, struct mbuf *m0, |
---|
619 | int *start_tx) |
---|
620 | { |
---|
621 | bus_dma_segment_t segs[TX_MAX_DMA_SEGS]; |
---|
622 | int error, i, nsegs; |
---|
623 | struct ffec_bufmap *bmap; |
---|
624 | uint32_t tx_idx; |
---|
625 | int csum_flags; |
---|
626 | uint32_t flags; |
---|
627 | uint32_t flags2; |
---|
628 | |
---|
629 | FFEC_ASSERT_LOCKED(sc); |
---|
630 | |
---|
631 | tx_idx = sc->tx_idx_head; |
---|
632 | bmap = &sc->txbuf_map[tx_idx]; |
---|
633 | |
---|
634 | /* Create mapping in DMA memory */ |
---|
635 | error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, bmap->map, m0, |
---|
636 | segs, &nsegs, BUS_DMA_NOWAIT); |
---|
637 | if (error == EFBIG) { |
---|
638 | /* Too many segments! Defrag and try again. */ |
---|
639 | struct mbuf *m = m_defrag(m0, M_NOWAIT); |
---|
640 | |
---|
641 | if (m == NULL) { |
---|
642 | m_freem(m0); |
---|
643 | return; |
---|
644 | } |
---|
645 | m0 = m; |
---|
646 | error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, |
---|
647 | bmap->map, m0, segs, &nsegs, BUS_DMA_NOWAIT); |
---|
648 | } |
---|
649 | if (error != 0) { |
---|
650 | /* Give up. */ |
---|
651 | m_freem(m0); |
---|
652 | return; |
---|
653 | } |
---|
654 | |
---|
655 | #ifndef __rtems__ |
---|
656 | bus_dmamap_sync(sc->txbuf_tag, bmap->map, BUS_DMASYNC_PREWRITE); |
---|
657 | #endif /* __rtems__ */ |
---|
658 | bmap->mbuf = m0; |
---|
659 | |
---|
660 | flags2 = FEC_TXDESC_INT; |
---|
661 | csum_flags = m0->m_pkthdr.csum_flags; |
---|
662 | |
---|
663 | if ((csum_flags & CSUM_IP) != 0) { |
---|
664 | struct mbuf *n; |
---|
665 | int off; |
---|
666 | int off2; |
---|
667 | struct ip *ip; |
---|
668 | |
---|
669 | flags2 |= FEC_TXDESC_IINS; |
---|
670 | n = m_getptr(m0, sizeof(struct ether_header), &off); |
---|
671 | ip = (struct ip *)mtodo(n, off); |
---|
672 | ip->ip_sum = 0; |
---|
673 | |
---|
674 | off2 = m0->m_pkthdr.csum_data; |
---|
675 | if ((csum_flags & (CSUM_TCP | CSUM_UDP)) != 0 && off2 != 0) { |
---|
676 | flags2 |= FEC_TXDESC_PINS; |
---|
677 | *(uint16_t *)((caddr_t)(ip + 1) + off2) = 0; |
---|
678 | } |
---|
679 | } |
---|
680 | |
---|
681 | /* |
---|
682 | * Fill in the TX descriptors back to front so that READY bit in first |
---|
683 | * descriptor is set last. |
---|
684 | */ |
---|
685 | tx_idx = inc_txidx(tx_idx, (uint32_t)nsegs); |
---|
686 | sc->tx_idx_head = tx_idx; |
---|
687 | flags = FEC_TXDESC_L | FEC_TXDESC_READY | FEC_TXDESC_TC; |
---|
688 | for (i = nsegs - 1; i >= 0; i--) { |
---|
689 | struct ffec_hwdesc *tx_desc; |
---|
690 | |
---|
691 | tx_idx = prev_txidx(tx_idx);; |
---|
692 | tx_desc = &sc->txdesc_ring[tx_idx]; |
---|
693 | tx_desc->buf_paddr = segs[i].ds_addr; |
---|
694 | tx_desc->flags2 = flags2; |
---|
695 | #ifdef __rtems__ |
---|
696 | rtems_cache_flush_multiple_data_lines((void *)segs[i].ds_addr, |
---|
697 | segs[i].ds_len); |
---|
698 | #endif /* __rtems__ */ |
---|
699 | |
---|
700 | if (i == 0) { |
---|
701 | wmb(); |
---|
702 | } |
---|
703 | |
---|
704 | tx_desc->flags_len = (tx_idx == (TX_DESC_COUNT - 1) ? |
---|
705 | FEC_TXDESC_WRAP : 0) | flags | segs[i].ds_len; |
---|
706 | |
---|
707 | flags &= ~FEC_TXDESC_L; |
---|
708 | } |
---|
709 | |
---|
710 | BPF_MTAP(ifp, m0); |
---|
711 | *start_tx = 1; |
---|
712 | } |
---|
713 | |
---|
714 | static void |
---|
715 | ffec_txstart_locked(struct ffec_softc *sc) |
---|
716 | { |
---|
717 | struct ifnet *ifp; |
---|
718 | struct mbuf *m0; |
---|
719 | int start_tx; |
---|
720 | |
---|
721 | FFEC_ASSERT_LOCKED(sc); |
---|
722 | |
---|
723 | ifp = sc->ifp; |
---|
724 | start_tx = 0; |
---|
725 | |
---|
726 | if (!sc->link_is_up) |
---|
727 | return; |
---|
728 | |
---|
729 | for (;;) { |
---|
730 | if (free_txdesc(sc) < TX_MAX_DMA_SEGS) { |
---|
731 | /* No free descriptors */ |
---|
732 | ifp->if_drv_flags |= IFF_DRV_OACTIVE; |
---|
733 | break; |
---|
734 | } |
---|
735 | |
---|
736 | /* Get packet from the queue */ |
---|
737 | IFQ_DRV_DEQUEUE(&ifp->if_snd, m0); |
---|
738 | if (m0 == NULL) |
---|
739 | break; |
---|
740 | |
---|
741 | ffec_encap(ifp, sc, m0, &start_tx); |
---|
742 | } |
---|
743 | |
---|
744 | if (start_tx ) { |
---|
745 | bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREWRITE); |
---|
746 | WR4(sc, FEC_TDAR_REG, FEC_TDAR_TDAR); |
---|
747 | bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTWRITE); |
---|
748 | sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS; |
---|
749 | } |
---|
750 | } |
---|
751 | |
---|
752 | static void |
---|
753 | ffec_txstart(struct ifnet *ifp) |
---|
754 | { |
---|
755 | struct ffec_softc *sc = ifp->if_softc; |
---|
756 | |
---|
757 | FFEC_LOCK(sc); |
---|
758 | ffec_txstart_locked(sc); |
---|
759 | FFEC_UNLOCK(sc); |
---|
760 | } |
---|
761 | |
---|
762 | static void |
---|
763 | ffec_txfinish_locked(struct ffec_softc *sc) |
---|
764 | { |
---|
765 | struct ifnet *ifp; |
---|
766 | uint32_t tx_idx; |
---|
767 | |
---|
768 | FFEC_ASSERT_LOCKED(sc); |
---|
769 | |
---|
770 | ifp = sc->ifp; |
---|
771 | |
---|
772 | /* XXX Can't set PRE|POST right now, but we need both. */ |
---|
773 | bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREREAD); |
---|
774 | bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTREAD); |
---|
775 | |
---|
776 | tx_idx = sc->tx_idx_tail; |
---|
777 | while (tx_idx != sc->tx_idx_head) { |
---|
778 | struct ffec_hwdesc *desc; |
---|
779 | struct ffec_bufmap *bmap; |
---|
780 | |
---|
781 | desc = &sc->txdesc_ring[tx_idx]; |
---|
782 | if (desc->flags_len & FEC_TXDESC_READY) |
---|
783 | break; |
---|
784 | |
---|
785 | bmap = &sc->txbuf_map[tx_idx]; |
---|
786 | tx_idx = next_txidx(tx_idx); |
---|
787 | if (bmap->mbuf == NULL) |
---|
788 | continue; |
---|
789 | |
---|
790 | /* |
---|
791 | * This is the last buf in this packet, so unmap and free it. |
---|
792 | */ |
---|
793 | bus_dmamap_sync(sc->txbuf_tag, bmap->map, |
---|
794 | BUS_DMASYNC_POSTWRITE); |
---|
795 | bus_dmamap_unload(sc->txbuf_tag, bmap->map); |
---|
796 | m_freem(bmap->mbuf); |
---|
797 | bmap->mbuf = NULL; |
---|
798 | } |
---|
799 | sc->tx_idx_tail = tx_idx; |
---|
800 | |
---|
801 | ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; |
---|
802 | ffec_txstart_locked(sc); |
---|
803 | |
---|
804 | /* If there are no buffers outstanding, muzzle the watchdog. */ |
---|
805 | if (sc->tx_idx_tail == sc->tx_idx_head) { |
---|
806 | sc->tx_watchdog_count = 0; |
---|
807 | } |
---|
808 | } |
---|
809 | |
---|
810 | inline static uint32_t |
---|
811 | ffec_setup_rxdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr) |
---|
812 | { |
---|
813 | uint32_t nidx; |
---|
814 | |
---|
815 | /* |
---|
816 | * The hardware requires 32-bit physical addresses. We set up the dma |
---|
817 | * tag to indicate that, so the cast to uint32_t should never lose |
---|
818 | * significant bits. |
---|
819 | */ |
---|
820 | nidx = next_rxidx(idx); |
---|
821 | sc->rxdesc_ring[idx].buf_paddr = (uint32_t)paddr; |
---|
822 | sc->rxdesc_ring[idx].flags2 = FEC_RXDESC_INT; |
---|
823 | wmb(); |
---|
824 | sc->rxdesc_ring[idx].flags_len = FEC_RXDESC_EMPTY | |
---|
825 | ((nidx == 0) ? FEC_RXDESC_WRAP : 0); |
---|
826 | |
---|
827 | return (nidx); |
---|
828 | } |
---|
829 | |
---|
830 | static int |
---|
831 | ffec_setup_rxbuf(struct ffec_softc *sc, int idx, struct mbuf * m) |
---|
832 | { |
---|
833 | int error, nsegs; |
---|
834 | struct bus_dma_segment seg; |
---|
835 | |
---|
836 | if ((sc->fectype & FECFLAG_RACC) == 0) { |
---|
837 | /* |
---|
838 | * The RACC[SHIFT16] feature is not used. So, we need to leave |
---|
839 | * at least ETHER_ALIGN bytes free at the beginning of the |
---|
840 | * buffer to allow the data to be re-aligned after receiving it |
---|
841 | * (by copying it backwards ETHER_ALIGN bytes in the same |
---|
842 | * buffer). We also have to ensure that the beginning of the |
---|
843 | * buffer is aligned to the hardware's requirements. |
---|
844 | */ |
---|
845 | m_adj(m, roundup(ETHER_ALIGN, sc->rxbuf_align)); |
---|
846 | } |
---|
847 | |
---|
848 | error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map, |
---|
849 | m, &seg, &nsegs, 0); |
---|
850 | if (error != 0) { |
---|
851 | return (error); |
---|
852 | } |
---|
853 | |
---|
854 | bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, |
---|
855 | BUS_DMASYNC_PREREAD); |
---|
856 | |
---|
857 | sc->rxbuf_map[idx].mbuf = m; |
---|
858 | ffec_setup_rxdesc(sc, idx, seg.ds_addr); |
---|
859 | |
---|
860 | return (0); |
---|
861 | } |
---|
862 | |
---|
863 | static struct mbuf * |
---|
864 | ffec_alloc_mbufcl(struct ffec_softc *sc) |
---|
865 | { |
---|
866 | struct mbuf *m; |
---|
867 | |
---|
868 | m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); |
---|
869 | if (m == NULL) |
---|
870 | return (m); |
---|
871 | |
---|
872 | m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; |
---|
873 | #ifdef __rtems__ |
---|
874 | rtems_cache_invalidate_multiple_data_lines(m->m_data, m->m_len); |
---|
875 | #endif /* __rtems__ */ |
---|
876 | |
---|
877 | return (m); |
---|
878 | } |
---|
879 | |
---|
880 | static void |
---|
881 | ffec_rxfinish_onebuf(struct ffec_softc *sc, int len, uint32_t flags2) |
---|
882 | { |
---|
883 | struct mbuf *m, *newmbuf; |
---|
884 | struct ffec_bufmap *bmap; |
---|
885 | int error; |
---|
886 | |
---|
887 | /* |
---|
888 | * First try to get a new mbuf to plug into this slot in the rx ring. |
---|
889 | * If that fails, drop the current packet and recycle the current |
---|
890 | * mbuf, which is still mapped and loaded. |
---|
891 | */ |
---|
892 | if ((newmbuf = ffec_alloc_mbufcl(sc)) == NULL) { |
---|
893 | if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1); |
---|
894 | ffec_setup_rxdesc(sc, sc->rx_idx, |
---|
895 | sc->rxdesc_ring[sc->rx_idx].buf_paddr); |
---|
896 | return; |
---|
897 | } |
---|
898 | |
---|
899 | /* |
---|
900 | * Unfortunately, the protocol headers need to be aligned on a 32-bit |
---|
901 | * boundary for the upper layers. The hardware requires receive |
---|
902 | * buffers to be 16-byte aligned. The ethernet header is 14 bytes, |
---|
903 | * leaving the protocol header unaligned. We used m_adj() after |
---|
904 | * allocating the buffer to leave empty space at the start of the |
---|
905 | * buffer, now we'll use the alignment agnostic bcopy() routine to |
---|
906 | * shuffle all the data backwards 2 bytes and adjust m_data. |
---|
907 | * |
---|
908 | * XXX imx6 hardware is able to do this 2-byte alignment by setting the |
---|
909 | * SHIFT16 bit in the RACC register. Older hardware doesn't have that |
---|
910 | * feature, but for them could we speed this up by copying just the |
---|
911 | * protocol headers into their own small mbuf then chaining the cluster |
---|
912 | * to it? That way we'd only need to copy like 64 bytes or whatever |
---|
913 | * the biggest header is, instead of the whole 1530ish-byte frame. |
---|
914 | */ |
---|
915 | |
---|
916 | FFEC_UNLOCK(sc); |
---|
917 | |
---|
918 | bmap = &sc->rxbuf_map[sc->rx_idx]; |
---|
919 | len -= ETHER_CRC_LEN; |
---|
920 | bus_dmamap_sync(sc->rxbuf_tag, bmap->map, BUS_DMASYNC_POSTREAD); |
---|
921 | bus_dmamap_unload(sc->rxbuf_tag, bmap->map); |
---|
922 | m = bmap->mbuf; |
---|
923 | bmap->mbuf = NULL; |
---|
924 | m->m_len = len; |
---|
925 | m->m_pkthdr.len = len; |
---|
926 | m->m_pkthdr.rcvif = sc->ifp; |
---|
927 | |
---|
928 | if ((flags2 & (FEC_RXDESC_ICE | FEC_RXDESC_PCR)) == 0) { |
---|
929 | m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID | |
---|
930 | CSUM_DATA_VALID | CSUM_PSEUDO_HDR; |
---|
931 | m->m_pkthdr.csum_data = 0xffff; |
---|
932 | } |
---|
933 | |
---|
934 | if (sc->fectype & FECFLAG_RACC) { |
---|
935 | /* We use the RACC[SHIFT16] feature */ |
---|
936 | m->m_data = mtod(m, uint8_t *) + 2; |
---|
937 | } else { |
---|
938 | uint8_t *dst, *src; |
---|
939 | |
---|
940 | src = mtod(m, uint8_t*); |
---|
941 | dst = src - ETHER_ALIGN; |
---|
942 | bcopy(src, dst, len); |
---|
943 | m->m_data = dst; |
---|
944 | } |
---|
945 | sc->ifp->if_input(sc->ifp, m); |
---|
946 | |
---|
947 | FFEC_LOCK(sc); |
---|
948 | |
---|
949 | if ((error = ffec_setup_rxbuf(sc, sc->rx_idx, newmbuf)) != 0) { |
---|
950 | device_printf(sc->dev, "ffec_setup_rxbuf error %d\n", error); |
---|
951 | /* XXX Now what? We've got a hole in the rx ring. */ |
---|
952 | } |
---|
953 | |
---|
954 | } |
---|
955 | |
---|
956 | static void |
---|
957 | ffec_rxfinish_locked(struct ffec_softc *sc) |
---|
958 | { |
---|
959 | struct ffec_hwdesc *desc; |
---|
960 | int len; |
---|
961 | boolean_t produced_empty_buffer; |
---|
962 | |
---|
963 | FFEC_ASSERT_LOCKED(sc); |
---|
964 | |
---|
965 | /* XXX Can't set PRE|POST right now, but we need both. */ |
---|
966 | bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_PREREAD); |
---|
967 | bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_POSTREAD); |
---|
968 | produced_empty_buffer = false; |
---|
969 | for (;;) { |
---|
970 | desc = &sc->rxdesc_ring[sc->rx_idx]; |
---|
971 | if (desc->flags_len & FEC_RXDESC_EMPTY) |
---|
972 | break; |
---|
973 | produced_empty_buffer = true; |
---|
974 | len = (desc->flags_len & FEC_RXDESC_LEN_MASK); |
---|
975 | if (len < 64) { |
---|
976 | /* |
---|
977 | * Just recycle the descriptor and continue. . |
---|
978 | */ |
---|
979 | ffec_setup_rxdesc(sc, sc->rx_idx, |
---|
980 | sc->rxdesc_ring[sc->rx_idx].buf_paddr); |
---|
981 | } else if ((desc->flags_len & FEC_RXDESC_L) == 0) { |
---|
982 | /* |
---|
983 | * The entire frame is not in this buffer. Impossible. |
---|
984 | * Recycle the descriptor and continue. |
---|
985 | * |
---|
986 | * XXX what's the right way to handle this? Probably we |
---|
987 | * should stop/init the hardware because this should |
---|
988 | * just really never happen when we have buffers bigger |
---|
989 | * than the maximum frame size. |
---|
990 | */ |
---|
991 | device_printf(sc->dev, |
---|
992 | "fec_rxfinish: received frame without LAST bit set"); |
---|
993 | ffec_setup_rxdesc(sc, sc->rx_idx, |
---|
994 | sc->rxdesc_ring[sc->rx_idx].buf_paddr); |
---|
995 | } else if (desc->flags_len & FEC_RXDESC_ERROR_BITS) { |
---|
996 | /* |
---|
997 | * Something went wrong with receiving the frame, we |
---|
998 | * don't care what (the hardware has counted the error |
---|
999 | * in the stats registers already), we just reuse the |
---|
1000 | * same mbuf, which is still dma-mapped, by resetting |
---|
1001 | * the rx descriptor. |
---|
1002 | */ |
---|
1003 | ffec_setup_rxdesc(sc, sc->rx_idx, |
---|
1004 | sc->rxdesc_ring[sc->rx_idx].buf_paddr); |
---|
1005 | } else { |
---|
1006 | /* |
---|
1007 | * Normal case: a good frame all in one buffer. |
---|
1008 | */ |
---|
1009 | ffec_rxfinish_onebuf(sc, len, desc->flags2); |
---|
1010 | } |
---|
1011 | sc->rx_idx = next_rxidx(sc->rx_idx); |
---|
1012 | } |
---|
1013 | |
---|
1014 | if (produced_empty_buffer) { |
---|
1015 | bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_PREWRITE); |
---|
1016 | WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR); |
---|
1017 | bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_POSTWRITE); |
---|
1018 | } |
---|
1019 | } |
---|
1020 | |
---|
1021 | static void |
---|
1022 | ffec_get_hwaddr(struct ffec_softc *sc, uint8_t *hwaddr) |
---|
1023 | { |
---|
1024 | uint32_t palr, paur, rnd; |
---|
1025 | |
---|
1026 | /* |
---|
1027 | * Try to recover a MAC address from the running hardware. If there's |
---|
1028 | * something non-zero there, assume the bootloader did the right thing |
---|
1029 | * and just use it. |
---|
1030 | * |
---|
1031 | * Otherwise, set the address to a convenient locally assigned address, |
---|
1032 | * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally |
---|
1033 | * assigned bit set, and the broadcast/multicast bit clear. |
---|
1034 | */ |
---|
1035 | palr = RD4(sc, FEC_PALR_REG); |
---|
1036 | paur = RD4(sc, FEC_PAUR_REG) & FEC_PAUR_PADDR2_MASK; |
---|
1037 | if ((palr | paur) != 0) { |
---|
1038 | hwaddr[0] = palr >> 24; |
---|
1039 | hwaddr[1] = palr >> 16; |
---|
1040 | hwaddr[2] = palr >> 8; |
---|
1041 | hwaddr[3] = palr >> 0; |
---|
1042 | hwaddr[4] = paur >> 24; |
---|
1043 | hwaddr[5] = paur >> 16; |
---|
1044 | } else { |
---|
1045 | rnd = arc4random() & 0x00ffffff; |
---|
1046 | hwaddr[0] = 'b'; |
---|
1047 | hwaddr[1] = 's'; |
---|
1048 | hwaddr[2] = 'd'; |
---|
1049 | hwaddr[3] = rnd >> 16; |
---|
1050 | hwaddr[4] = rnd >> 8; |
---|
1051 | hwaddr[5] = rnd >> 0; |
---|
1052 | } |
---|
1053 | |
---|
1054 | if (bootverbose) { |
---|
1055 | device_printf(sc->dev, |
---|
1056 | "MAC address %02x:%02x:%02x:%02x:%02x:%02x:\n", |
---|
1057 | hwaddr[0], hwaddr[1], hwaddr[2], |
---|
1058 | hwaddr[3], hwaddr[4], hwaddr[5]); |
---|
1059 | } |
---|
1060 | } |
---|
1061 | |
---|
1062 | static void |
---|
1063 | ffec_setup_rxfilter(struct ffec_softc *sc) |
---|
1064 | { |
---|
1065 | struct ifnet *ifp; |
---|
1066 | struct ifmultiaddr *ifma; |
---|
1067 | uint8_t *eaddr; |
---|
1068 | uint32_t crc; |
---|
1069 | uint64_t ghash, ihash; |
---|
1070 | |
---|
1071 | FFEC_ASSERT_LOCKED(sc); |
---|
1072 | |
---|
1073 | ifp = sc->ifp; |
---|
1074 | |
---|
1075 | /* |
---|
1076 | * Set the multicast (group) filter hash. |
---|
1077 | */ |
---|
1078 | if ((ifp->if_flags & IFF_ALLMULTI)) |
---|
1079 | ghash = 0xffffffffffffffffLLU; |
---|
1080 | else { |
---|
1081 | ghash = 0; |
---|
1082 | if_maddr_rlock(ifp); |
---|
1083 | TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { |
---|
1084 | if (ifma->ifma_addr->sa_family != AF_LINK) |
---|
1085 | continue; |
---|
1086 | /* 6 bits from MSB in LE CRC32 are used for hash. */ |
---|
1087 | crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) |
---|
1088 | ifma->ifma_addr), ETHER_ADDR_LEN); |
---|
1089 | ghash |= 1LLU << (((uint8_t *)&crc)[3] >> 2); |
---|
1090 | } |
---|
1091 | if_maddr_runlock(ifp); |
---|
1092 | } |
---|
1093 | WR4(sc, FEC_GAUR_REG, (uint32_t)(ghash >> 32)); |
---|
1094 | WR4(sc, FEC_GALR_REG, (uint32_t)ghash); |
---|
1095 | |
---|
1096 | /* |
---|
1097 | * Set the individual address filter hash. |
---|
1098 | * |
---|
1099 | * XXX Is 0 the right value when promiscuous is off? This hw feature |
---|
1100 | * seems to support the concept of MAC address aliases, does such a |
---|
1101 | * thing even exist? |
---|
1102 | */ |
---|
1103 | if ((ifp->if_flags & IFF_PROMISC)) |
---|
1104 | ihash = 0xffffffffffffffffLLU; |
---|
1105 | else { |
---|
1106 | ihash = 0; |
---|
1107 | } |
---|
1108 | WR4(sc, FEC_IAUR_REG, (uint32_t)(ihash >> 32)); |
---|
1109 | WR4(sc, FEC_IALR_REG, (uint32_t)ihash); |
---|
1110 | |
---|
1111 | /* |
---|
1112 | * Set the primary address. |
---|
1113 | */ |
---|
1114 | eaddr = IF_LLADDR(ifp); |
---|
1115 | WR4(sc, FEC_PALR_REG, (eaddr[0] << 24) | (eaddr[1] << 16) | |
---|
1116 | (eaddr[2] << 8) | eaddr[3]); |
---|
1117 | WR4(sc, FEC_PAUR_REG, (eaddr[4] << 24) | (eaddr[5] << 16)); |
---|
1118 | } |
---|
1119 | |
---|
1120 | static void |
---|
1121 | ffec_stop_locked(struct ffec_softc *sc) |
---|
1122 | { |
---|
1123 | struct ifnet *ifp; |
---|
1124 | struct ffec_hwdesc *desc; |
---|
1125 | struct ffec_bufmap *bmap; |
---|
1126 | int idx; |
---|
1127 | |
---|
1128 | FFEC_ASSERT_LOCKED(sc); |
---|
1129 | |
---|
1130 | ifp = sc->ifp; |
---|
1131 | ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); |
---|
1132 | sc->tx_watchdog_count = 0; |
---|
1133 | sc->stats_harvest_count = 0; |
---|
1134 | |
---|
1135 | /* |
---|
1136 | * Stop the hardware, mask all interrupts, and clear all current |
---|
1137 | * interrupt status bits. |
---|
1138 | */ |
---|
1139 | WR4(sc, FEC_ECR_REG, RD4(sc, FEC_ECR_REG) & ~FEC_ECR_ETHEREN); |
---|
1140 | WR4(sc, FEC_IEM_REG, 0x00000000); |
---|
1141 | WR4(sc, FEC_IER_REG, 0xffffffff); |
---|
1142 | |
---|
1143 | /* |
---|
1144 | * Stop the media-check callout. Do not use callout_drain() because |
---|
1145 | * we're holding a mutex the callout acquires, and if it's currently |
---|
1146 | * waiting to acquire it, we'd deadlock. If it is waiting now, the |
---|
1147 | * ffec_tick() routine will return without doing anything when it sees |
---|
1148 | * that IFF_DRV_RUNNING is not set, so avoiding callout_drain() is safe. |
---|
1149 | */ |
---|
1150 | callout_stop(&sc->ffec_callout); |
---|
1151 | |
---|
1152 | /* |
---|
1153 | * Discard all untransmitted buffers. Each buffer is simply freed; |
---|
1154 | * it's as if the bits were transmitted and then lost on the wire. |
---|
1155 | * |
---|
1156 | * XXX Is this right? Or should we use IFQ_DRV_PREPEND() to put them |
---|
1157 | * back on the queue for when we get restarted later? |
---|
1158 | */ |
---|
1159 | idx = sc->tx_idx_tail; |
---|
1160 | while (idx != sc->tx_idx_head) { |
---|
1161 | desc = &sc->txdesc_ring[idx]; |
---|
1162 | bmap = &sc->txbuf_map[idx]; |
---|
1163 | idx = next_txidx(idx); |
---|
1164 | if (bmap->mbuf == NULL) |
---|
1165 | continue; |
---|
1166 | |
---|
1167 | bus_dmamap_sync(sc->txbuf_tag, bmap->map, |
---|
1168 | BUS_DMASYNC_POSTWRITE); |
---|
1169 | bus_dmamap_unload(sc->txbuf_tag, bmap->map); |
---|
1170 | m_freem(bmap->mbuf); |
---|
1171 | bmap->mbuf = NULL; |
---|
1172 | } |
---|
1173 | |
---|
1174 | /* |
---|
1175 | * Discard all unprocessed receive buffers. This amounts to just |
---|
1176 | * pretending that nothing ever got received into them. We reuse the |
---|
1177 | * mbuf already mapped for each desc, simply turning the EMPTY flags |
---|
1178 | * back on so they'll get reused when we start up again. |
---|
1179 | */ |
---|
1180 | for (idx = 0; idx < RX_DESC_COUNT; ++idx) { |
---|
1181 | desc = &sc->rxdesc_ring[idx]; |
---|
1182 | ffec_setup_rxdesc(sc, idx, desc->buf_paddr); |
---|
1183 | } |
---|
1184 | } |
---|
1185 | |
---|
1186 | static void |
---|
1187 | ffec_init_locked(struct ffec_softc *sc) |
---|
1188 | { |
---|
1189 | struct ifnet *ifp = sc->ifp; |
---|
1190 | uint32_t maxbuf, maxfl, regval; |
---|
1191 | |
---|
1192 | FFEC_ASSERT_LOCKED(sc); |
---|
1193 | |
---|
1194 | /* |
---|
1195 | * The hardware has a limit of 0x7ff as the max frame length (see |
---|
1196 | * comments for MRBR below), and we use mbuf clusters as receive |
---|
1197 | * buffers, and we currently are designed to receive an entire frame |
---|
1198 | * into a single buffer. |
---|
1199 | * |
---|
1200 | * We start with a MCLBYTES-sized cluster, but we have to offset into |
---|
1201 | * the buffer by ETHER_ALIGN to make room for post-receive re-alignment, |
---|
1202 | * and then that value has to be rounded up to the hardware's DMA |
---|
1203 | * alignment requirements, so all in all our buffer is that much smaller |
---|
1204 | * than MCLBYTES. |
---|
1205 | * |
---|
1206 | * The resulting value is used as the frame truncation length and the |
---|
1207 | * max buffer receive buffer size for now. It'll become more complex |
---|
1208 | * when we support jumbo frames and receiving fragments of them into |
---|
1209 | * separate buffers. |
---|
1210 | */ |
---|
1211 | maxbuf = MCLBYTES - roundup(ETHER_ALIGN, sc->rxbuf_align); |
---|
1212 | maxfl = min(maxbuf, 0x7ff); |
---|
1213 | |
---|
1214 | if (ifp->if_drv_flags & IFF_DRV_RUNNING) |
---|
1215 | return; |
---|
1216 | |
---|
1217 | /* Mask all interrupts and clear all current interrupt status bits. */ |
---|
1218 | WR4(sc, FEC_IEM_REG, 0x00000000); |
---|
1219 | WR4(sc, FEC_IER_REG, 0xffffffff); |
---|
1220 | |
---|
1221 | /* |
---|
1222 | * Go set up palr/puar, galr/gaur, ialr/iaur. |
---|
1223 | */ |
---|
1224 | ffec_setup_rxfilter(sc); |
---|
1225 | |
---|
1226 | /* |
---|
1227 | * TFWR - Transmit FIFO watermark register. |
---|
1228 | * |
---|
1229 | * Set the transmit fifo watermark register to "store and forward" mode |
---|
1230 | * and also set a threshold of 128 bytes in the fifo before transmission |
---|
1231 | * of a frame begins (to avoid dma underruns). Recent FEC hardware |
---|
1232 | * supports STRFWD and when that bit is set, the watermark level in the |
---|
1233 | * low bits is ignored. Older hardware doesn't have STRFWD, but writing |
---|
1234 | * to that bit is innocuous, and the TWFR bits get used instead. |
---|
1235 | */ |
---|
1236 | WR4(sc, FEC_TFWR_REG, FEC_TFWR_STRFWD | FEC_TFWR_TWFR_128BYTE); |
---|
1237 | |
---|
1238 | /* RCR - Receive control register. |
---|
1239 | * |
---|
1240 | * Set max frame length + clean out anything left from u-boot. |
---|
1241 | */ |
---|
1242 | WR4(sc, FEC_RCR_REG, (maxfl << FEC_RCR_MAX_FL_SHIFT)); |
---|
1243 | |
---|
1244 | /* |
---|
1245 | * TCR - Transmit control register. |
---|
1246 | * |
---|
1247 | * Clean out anything left from u-boot. Any necessary values are set in |
---|
1248 | * ffec_miibus_statchg() based on the media type. |
---|
1249 | */ |
---|
1250 | WR4(sc, FEC_TCR_REG, 0); |
---|
1251 | |
---|
1252 | /* |
---|
1253 | * OPD - Opcode/pause duration. |
---|
1254 | * |
---|
1255 | * XXX These magic numbers come from u-boot. |
---|
1256 | */ |
---|
1257 | WR4(sc, FEC_OPD_REG, 0x00010020); |
---|
1258 | |
---|
1259 | /* |
---|
1260 | * FRSR - Fifo receive start register. |
---|
1261 | * |
---|
1262 | * This register does not exist on imx6, it is present on earlier |
---|
1263 | * hardware. The u-boot code sets this to a non-default value that's 32 |
---|
1264 | * bytes larger than the default, with no clue as to why. The default |
---|
1265 | * value should work fine, so there's no code to init it here. |
---|
1266 | */ |
---|
1267 | |
---|
1268 | /* |
---|
1269 | * MRBR - Max RX buffer size. |
---|
1270 | * |
---|
1271 | * Note: For hardware prior to imx6 this value cannot exceed 0x07ff, |
---|
1272 | * but the datasheet says no such thing for imx6. On the imx6, setting |
---|
1273 | * this to 2K without setting EN1588 resulted in a crazy runaway |
---|
1274 | * receive loop in the hardware, where every rx descriptor in the ring |
---|
1275 | * had its EMPTY flag cleared, no completion or error flags set, and a |
---|
1276 | * length of zero. I think maybe you can only exceed it when EN1588 is |
---|
1277 | * set, like maybe that's what enables jumbo frames, because in general |
---|
1278 | * the EN1588 flag seems to be the "enable new stuff" vs. "be legacy- |
---|
1279 | * compatible" flag. |
---|
1280 | */ |
---|
1281 | WR4(sc, FEC_MRBR_REG, maxfl << FEC_MRBR_R_BUF_SIZE_SHIFT); |
---|
1282 | |
---|
1283 | /* |
---|
1284 | * FTRL - Frame truncation length. |
---|
1285 | * |
---|
1286 | * Must be greater than or equal to the value set in FEC_RCR_MAXFL. |
---|
1287 | */ |
---|
1288 | WR4(sc, FEC_FTRL_REG, maxfl); |
---|
1289 | |
---|
1290 | /* |
---|
1291 | * RDSR / TDSR descriptor ring pointers. |
---|
1292 | * |
---|
1293 | * When we turn on ECR_ETHEREN at the end, the hardware zeroes its |
---|
1294 | * internal current descriptor index values for both rings, so we zero |
---|
1295 | * our index values as well. |
---|
1296 | */ |
---|
1297 | sc->rx_idx = 0; |
---|
1298 | sc->tx_idx_head = sc->tx_idx_tail = 0; |
---|
1299 | WR4(sc, FEC_RDSR_REG, sc->rxdesc_ring_paddr); |
---|
1300 | WR4(sc, FEC_TDSR_REG, sc->txdesc_ring_paddr); |
---|
1301 | |
---|
1302 | /* |
---|
1303 | * EIM - interrupt mask register. |
---|
1304 | * |
---|
1305 | * We always enable the same set of interrupts while running; unlike |
---|
1306 | * some drivers there's no need to change the mask on the fly depending |
---|
1307 | * on what operations are in progress. |
---|
1308 | */ |
---|
1309 | WR4(sc, FEC_IEM_REG, FEC_IER_TXF | FEC_IER_RXF | FEC_IER_EBERR); |
---|
1310 | |
---|
1311 | /* |
---|
1312 | * MIBC - MIB control (hardware stats). |
---|
1313 | */ |
---|
1314 | regval = RD4(sc, FEC_MIBC_REG); |
---|
1315 | WR4(sc, FEC_MIBC_REG, regval | FEC_MIBC_DIS); |
---|
1316 | ffec_clear_stats(sc); |
---|
1317 | WR4(sc, FEC_MIBC_REG, regval & ~FEC_MIBC_DIS); |
---|
1318 | |
---|
1319 | if (sc->fectype & FECFLAG_RACC) { |
---|
1320 | /* |
---|
1321 | * RACC - Receive Accelerator Function Configuration. |
---|
1322 | */ |
---|
1323 | regval = RD4(sc, FEC_RACC_REG); |
---|
1324 | WR4(sc, FEC_RACC_REG, regval | FEC_RACC_SHIFT16); |
---|
1325 | } |
---|
1326 | |
---|
1327 | /* |
---|
1328 | * ECR - Ethernet control register. |
---|
1329 | * |
---|
1330 | * This must happen after all the other config registers are set. If |
---|
1331 | * we're running on little-endian hardware, also set the flag for byte- |
---|
1332 | * swapping descriptor ring entries. This flag doesn't exist on older |
---|
1333 | * hardware, but it can be safely set -- the bit position it occupies |
---|
1334 | * was unused. |
---|
1335 | */ |
---|
1336 | regval = RD4(sc, FEC_ECR_REG); |
---|
1337 | #if _BYTE_ORDER == _LITTLE_ENDIAN |
---|
1338 | regval |= FEC_ECR_DBSWP; |
---|
1339 | #endif |
---|
1340 | regval |= FEC_ECR_ETHEREN; |
---|
1341 | regval |= FEC_ECR_EN1588; |
---|
1342 | WR4(sc, FEC_ECR_REG, regval); |
---|
1343 | |
---|
1344 | ifp->if_drv_flags |= IFF_DRV_RUNNING; |
---|
1345 | |
---|
1346 | /* |
---|
1347 | * Call mii_mediachg() which will call back into ffec_miibus_statchg() to |
---|
1348 | * set up the remaining config registers based on the current media. |
---|
1349 | */ |
---|
1350 | mii_mediachg(sc->mii_softc); |
---|
1351 | callout_reset(&sc->ffec_callout, hz, ffec_tick, sc); |
---|
1352 | |
---|
1353 | /* |
---|
1354 | * Tell the hardware that receive buffers are available. They were made |
---|
1355 | * available in ffec_attach() or ffec_stop(). |
---|
1356 | */ |
---|
1357 | WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR); |
---|
1358 | |
---|
1359 | ffec_set_rxic(sc); |
---|
1360 | ffec_set_txic(sc); |
---|
1361 | } |
---|
1362 | |
---|
1363 | static void |
---|
1364 | ffec_init(void *if_softc) |
---|
1365 | { |
---|
1366 | struct ffec_softc *sc = if_softc; |
---|
1367 | |
---|
1368 | FFEC_LOCK(sc); |
---|
1369 | ffec_init_locked(sc); |
---|
1370 | FFEC_UNLOCK(sc); |
---|
1371 | } |
---|
1372 | |
---|
1373 | static void |
---|
1374 | ffec_intr(void *arg) |
---|
1375 | { |
---|
1376 | struct ffec_softc *sc; |
---|
1377 | uint32_t ier; |
---|
1378 | |
---|
1379 | sc = arg; |
---|
1380 | |
---|
1381 | FFEC_LOCK(sc); |
---|
1382 | |
---|
1383 | ier = RD4(sc, FEC_IER_REG); |
---|
1384 | |
---|
1385 | if (ier & FEC_IER_TXF) { |
---|
1386 | WR4(sc, FEC_IER_REG, FEC_IER_TXF); |
---|
1387 | ffec_txfinish_locked(sc); |
---|
1388 | } |
---|
1389 | |
---|
1390 | if (ier & FEC_IER_RXF) { |
---|
1391 | WR4(sc, FEC_IER_REG, FEC_IER_RXF); |
---|
1392 | ffec_rxfinish_locked(sc); |
---|
1393 | } |
---|
1394 | |
---|
1395 | /* |
---|
1396 | * We actually don't care about most errors, because the hardware copes |
---|
1397 | * with them just fine, discarding the incoming bad frame, or forcing a |
---|
1398 | * bad CRC onto an outgoing bad frame, and counting the errors in the |
---|
1399 | * stats registers. The one that really matters is EBERR (DMA bus |
---|
1400 | * error) because the hardware automatically clears ECR[ETHEREN] and we |
---|
1401 | * have to restart it here. It should never happen. |
---|
1402 | */ |
---|
1403 | if (ier & FEC_IER_EBERR) { |
---|
1404 | WR4(sc, FEC_IER_REG, FEC_IER_EBERR); |
---|
1405 | device_printf(sc->dev, |
---|
1406 | "Ethernet DMA error, restarting controller.\n"); |
---|
1407 | ffec_stop_locked(sc); |
---|
1408 | ffec_init_locked(sc); |
---|
1409 | } |
---|
1410 | |
---|
1411 | FFEC_UNLOCK(sc); |
---|
1412 | |
---|
1413 | } |
---|
1414 | |
---|
1415 | static int |
---|
1416 | ffec_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) |
---|
1417 | { |
---|
1418 | struct ffec_softc *sc; |
---|
1419 | struct mii_data *mii; |
---|
1420 | struct ifreq *ifr; |
---|
1421 | int mask, error; |
---|
1422 | |
---|
1423 | sc = ifp->if_softc; |
---|
1424 | ifr = (struct ifreq *)data; |
---|
1425 | |
---|
1426 | error = 0; |
---|
1427 | switch (cmd) { |
---|
1428 | case SIOCSIFFLAGS: |
---|
1429 | FFEC_LOCK(sc); |
---|
1430 | if (ifp->if_flags & IFF_UP) { |
---|
1431 | if (ifp->if_drv_flags & IFF_DRV_RUNNING) { |
---|
1432 | if ((ifp->if_flags ^ sc->if_flags) & |
---|
1433 | (IFF_PROMISC | IFF_ALLMULTI)) |
---|
1434 | ffec_setup_rxfilter(sc); |
---|
1435 | } else { |
---|
1436 | if (!sc->is_detaching) |
---|
1437 | ffec_init_locked(sc); |
---|
1438 | } |
---|
1439 | } else { |
---|
1440 | if (ifp->if_drv_flags & IFF_DRV_RUNNING) |
---|
1441 | ffec_stop_locked(sc); |
---|
1442 | } |
---|
1443 | sc->if_flags = ifp->if_flags; |
---|
1444 | FFEC_UNLOCK(sc); |
---|
1445 | break; |
---|
1446 | |
---|
1447 | case SIOCADDMULTI: |
---|
1448 | case SIOCDELMULTI: |
---|
1449 | if (ifp->if_drv_flags & IFF_DRV_RUNNING) { |
---|
1450 | FFEC_LOCK(sc); |
---|
1451 | ffec_setup_rxfilter(sc); |
---|
1452 | FFEC_UNLOCK(sc); |
---|
1453 | } |
---|
1454 | break; |
---|
1455 | |
---|
1456 | case SIOCSIFMEDIA: |
---|
1457 | case SIOCGIFMEDIA: |
---|
1458 | mii = sc->mii_softc; |
---|
1459 | error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); |
---|
1460 | break; |
---|
1461 | |
---|
1462 | case SIOCSIFCAP: |
---|
1463 | mask = ifp->if_capenable ^ ifr->ifr_reqcap; |
---|
1464 | if (mask & IFCAP_VLAN_MTU) { |
---|
1465 | /* No work to do except acknowledge the change took. */ |
---|
1466 | ifp->if_capenable ^= IFCAP_VLAN_MTU; |
---|
1467 | } |
---|
1468 | break; |
---|
1469 | |
---|
1470 | default: |
---|
1471 | error = ether_ioctl(ifp, cmd, data); |
---|
1472 | break; |
---|
1473 | } |
---|
1474 | |
---|
1475 | return (error); |
---|
1476 | } |
---|
1477 | |
---|
1478 | static int |
---|
1479 | ffec_detach(device_t dev) |
---|
1480 | { |
---|
1481 | struct ffec_softc *sc; |
---|
1482 | bus_dmamap_t map; |
---|
1483 | int idx, irq; |
---|
1484 | |
---|
1485 | /* |
---|
1486 | * NB: This function can be called internally to unwind a failure to |
---|
1487 | * attach. Make sure a resource got allocated/created before destroying. |
---|
1488 | */ |
---|
1489 | |
---|
1490 | sc = device_get_softc(dev); |
---|
1491 | |
---|
1492 | if (sc->is_attached) { |
---|
1493 | FFEC_LOCK(sc); |
---|
1494 | sc->is_detaching = true; |
---|
1495 | ffec_stop_locked(sc); |
---|
1496 | FFEC_UNLOCK(sc); |
---|
1497 | callout_drain(&sc->ffec_callout); |
---|
1498 | ether_ifdetach(sc->ifp); |
---|
1499 | } |
---|
1500 | |
---|
1501 | /* XXX no miibus detach? */ |
---|
1502 | |
---|
1503 | /* Clean up RX DMA resources and free mbufs. */ |
---|
1504 | for (idx = 0; idx < RX_DESC_COUNT; ++idx) { |
---|
1505 | if ((map = sc->rxbuf_map[idx].map) != NULL) { |
---|
1506 | bus_dmamap_unload(sc->rxbuf_tag, map); |
---|
1507 | bus_dmamap_destroy(sc->rxbuf_tag, map); |
---|
1508 | m_freem(sc->rxbuf_map[idx].mbuf); |
---|
1509 | } |
---|
1510 | } |
---|
1511 | if (sc->rxbuf_tag != NULL) |
---|
1512 | bus_dma_tag_destroy(sc->rxbuf_tag); |
---|
1513 | if (sc->rxdesc_map != NULL) { |
---|
1514 | bus_dmamap_unload(sc->rxdesc_tag, sc->rxdesc_map); |
---|
1515 | bus_dmamap_destroy(sc->rxdesc_tag, sc->rxdesc_map); |
---|
1516 | } |
---|
1517 | if (sc->rxdesc_tag != NULL) |
---|
1518 | bus_dma_tag_destroy(sc->rxdesc_tag); |
---|
1519 | |
---|
1520 | /* Clean up TX DMA resources. */ |
---|
1521 | for (idx = 0; idx < TX_DESC_COUNT; ++idx) { |
---|
1522 | if ((map = sc->txbuf_map[idx].map) != NULL) { |
---|
1523 | /* TX maps are already unloaded. */ |
---|
1524 | bus_dmamap_destroy(sc->txbuf_tag, map); |
---|
1525 | } |
---|
1526 | } |
---|
1527 | if (sc->txbuf_tag != NULL) |
---|
1528 | bus_dma_tag_destroy(sc->txbuf_tag); |
---|
1529 | if (sc->txdesc_map != NULL) { |
---|
1530 | bus_dmamap_unload(sc->txdesc_tag, sc->txdesc_map); |
---|
1531 | bus_dmamap_destroy(sc->txdesc_tag, sc->txdesc_map); |
---|
1532 | } |
---|
1533 | if (sc->txdesc_tag != NULL) |
---|
1534 | bus_dma_tag_destroy(sc->txdesc_tag); |
---|
1535 | |
---|
1536 | /* Release bus resources. */ |
---|
1537 | for (irq = 0; irq < sc->irq_count; ++irq) { |
---|
1538 | if (sc->intr_cookie[irq]) |
---|
1539 | bus_teardown_intr(dev, sc->irq_res[irq], |
---|
1540 | sc->intr_cookie[irq]); |
---|
1541 | |
---|
1542 | if (sc->irq_res[irq] != NULL) |
---|
1543 | bus_release_resource(dev, SYS_RES_IRQ, 0, |
---|
1544 | sc->irq_res[irq]); |
---|
1545 | } |
---|
1546 | |
---|
1547 | if (sc->mem_res != NULL) |
---|
1548 | bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); |
---|
1549 | |
---|
1550 | FFEC_LOCK_DESTROY(sc); |
---|
1551 | return (0); |
---|
1552 | } |
---|
1553 | |
---|
1554 | static void |
---|
1555 | ffec_add_sysctls(struct ffec_softc *sc) |
---|
1556 | { |
---|
1557 | struct sysctl_ctx_list *ctx; |
---|
1558 | struct sysctl_oid_list *children; |
---|
1559 | struct sysctl_oid *tree; |
---|
1560 | |
---|
1561 | ctx = device_get_sysctl_ctx(sc->dev); |
---|
1562 | children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); |
---|
1563 | tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "int_coal", |
---|
1564 | CTLFLAG_RD, 0, "FEC Interrupts coalescing"); |
---|
1565 | children = SYSCTL_CHILDREN(tree); |
---|
1566 | |
---|
1567 | SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_time", |
---|
1568 | CTLTYPE_UINT | CTLFLAG_RW, sc, FEC_IC_RX, ffec_sysctl_ic_time, |
---|
1569 | "I", "IC RX time threshold (0-65535)"); |
---|
1570 | SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_count", |
---|
1571 | CTLTYPE_UINT | CTLFLAG_RW, sc, FEC_IC_RX, ffec_sysctl_ic_count, |
---|
1572 | "I", "IC RX frame count threshold (0-255)"); |
---|
1573 | |
---|
1574 | SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_time", |
---|
1575 | CTLTYPE_UINT | CTLFLAG_RW, sc, FEC_IC_TX, ffec_sysctl_ic_time, |
---|
1576 | "I", "IC TX time threshold (0-65535)"); |
---|
1577 | SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_count", |
---|
1578 | CTLTYPE_UINT | CTLFLAG_RW, sc, FEC_IC_TX, ffec_sysctl_ic_count, |
---|
1579 | "I", "IC TX frame count threshold (0-255)"); |
---|
1580 | } |
---|
1581 | |
---|
1582 | /* |
---|
1583 | * With Interrupt Coalescing (IC) active, a transmit/receive frame |
---|
1584 | * interrupt is raised either upon: |
---|
1585 | * |
---|
1586 | * - threshold-defined period of time elapsed, or |
---|
1587 | * - threshold-defined number of frames is received/transmitted, |
---|
1588 | * whichever occurs first. |
---|
1589 | * |
---|
1590 | * The following sysctls regulate IC behaviour (for TX/RX separately): |
---|
1591 | * |
---|
1592 | * dev.ffec.<unit>.int_coal.rx_time |
---|
1593 | * dev.ffec.<unit>.int_coal.rx_count |
---|
1594 | * dev.ffec.<unit>.int_coal.tx_time |
---|
1595 | * dev.ffec.<unit>.int_coal.tx_count |
---|
1596 | * |
---|
1597 | * Values: |
---|
1598 | * |
---|
1599 | * - 0 for either time or count disables IC on the given TX/RX path |
---|
1600 | * |
---|
1601 | * - count: 1-255 (expresses frame count number; note that value of 1 is |
---|
1602 | * effectively IC off) |
---|
1603 | * |
---|
1604 | * - time: 1-65535 (value corresponds to a real time period and is |
---|
1605 | * expressed in units equivalent to 64 FEC interface clocks, i.e. one timer |
---|
1606 | * threshold unit is 26.5 us, 2.56 us, or 512 ns, corresponding to 10 Mbps, |
---|
1607 | * 100 Mbps, or 1Gbps, respectively. For detailed discussion consult the |
---|
1608 | * FEC reference manual. |
---|
1609 | */ |
---|
1610 | static int |
---|
1611 | ffec_sysctl_ic_time(SYSCTL_HANDLER_ARGS) |
---|
1612 | { |
---|
1613 | int error; |
---|
1614 | uint32_t time; |
---|
1615 | struct ffec_softc *sc = (struct ffec_softc *)arg1; |
---|
1616 | |
---|
1617 | time = (arg2 == FEC_IC_RX) ? sc->rx_ic_time : sc->tx_ic_time; |
---|
1618 | |
---|
1619 | error = sysctl_handle_int(oidp, &time, 0, req); |
---|
1620 | if (error != 0) |
---|
1621 | return (error); |
---|
1622 | |
---|
1623 | if (time > 65535) |
---|
1624 | return (EINVAL); |
---|
1625 | |
---|
1626 | FFEC_LOCK(sc); |
---|
1627 | if (arg2 == FEC_IC_RX) { |
---|
1628 | sc->rx_ic_time = time; |
---|
1629 | ffec_set_rxic(sc); |
---|
1630 | } else { |
---|
1631 | sc->tx_ic_time = time; |
---|
1632 | ffec_set_txic(sc); |
---|
1633 | } |
---|
1634 | FFEC_UNLOCK(sc); |
---|
1635 | |
---|
1636 | return (0); |
---|
1637 | } |
---|
1638 | |
---|
1639 | static int |
---|
1640 | ffec_sysctl_ic_count(SYSCTL_HANDLER_ARGS) |
---|
1641 | { |
---|
1642 | int error; |
---|
1643 | uint32_t count; |
---|
1644 | struct ffec_softc *sc = (struct ffec_softc *)arg1; |
---|
1645 | |
---|
1646 | count = (arg2 == FEC_IC_RX) ? sc->rx_ic_count : sc->tx_ic_count; |
---|
1647 | |
---|
1648 | error = sysctl_handle_int(oidp, &count, 0, req); |
---|
1649 | if (error != 0) |
---|
1650 | return (error); |
---|
1651 | |
---|
1652 | if (count > 255) |
---|
1653 | return (EINVAL); |
---|
1654 | |
---|
1655 | FFEC_LOCK(sc); |
---|
1656 | if (arg2 == FEC_IC_RX) { |
---|
1657 | sc->rx_ic_count = count; |
---|
1658 | ffec_set_rxic(sc); |
---|
1659 | } else { |
---|
1660 | sc->tx_ic_count = count; |
---|
1661 | ffec_set_txic(sc); |
---|
1662 | } |
---|
1663 | FFEC_UNLOCK(sc); |
---|
1664 | |
---|
1665 | return (0); |
---|
1666 | } |
---|
1667 | |
---|
1668 | static void |
---|
1669 | ffec_set_ic(struct ffec_softc *sc, bus_size_t off, int count, int time) |
---|
1670 | { |
---|
1671 | uint32_t ic; |
---|
1672 | |
---|
1673 | if (count == 0 || time == 0) |
---|
1674 | /* Disable RX IC */ |
---|
1675 | ic = 0; |
---|
1676 | else { |
---|
1677 | ic = FEC_IC_ICEN; |
---|
1678 | ic |= FEC_IC_ICFT(count); |
---|
1679 | ic |= FEC_IC_ICTT(time); |
---|
1680 | } |
---|
1681 | |
---|
1682 | WR4(sc, off, ic); |
---|
1683 | } |
---|
1684 | |
---|
1685 | static void |
---|
1686 | ffec_set_rxic(struct ffec_softc *sc) |
---|
1687 | { |
---|
1688 | |
---|
1689 | ffec_set_ic(sc, FEC_RXIC0_REG, sc->rx_ic_count, sc->rx_ic_time); |
---|
1690 | } |
---|
1691 | |
---|
1692 | static void |
---|
1693 | ffec_set_txic(struct ffec_softc *sc) |
---|
1694 | { |
---|
1695 | |
---|
1696 | ffec_set_ic(sc, FEC_TXIC0_REG, sc->tx_ic_count, sc->tx_ic_time); |
---|
1697 | } |
---|
1698 | |
---|
1699 | static int |
---|
1700 | ffec_attach(device_t dev) |
---|
1701 | { |
---|
1702 | struct ffec_softc *sc; |
---|
1703 | struct ifnet *ifp = NULL; |
---|
1704 | struct mbuf *m; |
---|
1705 | phandle_t ofw_node; |
---|
1706 | int error, rid, irq; |
---|
1707 | uint8_t eaddr[ETHER_ADDR_LEN]; |
---|
1708 | char phy_conn_name[32]; |
---|
1709 | uint32_t idx, mscr; |
---|
1710 | |
---|
1711 | sc = device_get_softc(dev); |
---|
1712 | sc->dev = dev; |
---|
1713 | |
---|
1714 | FFEC_LOCK_INIT(sc); |
---|
1715 | |
---|
1716 | /* |
---|
1717 | * There are differences in the implementation and features of the FEC |
---|
1718 | * hardware on different SoCs, so figure out what type we are. |
---|
1719 | */ |
---|
1720 | sc->fectype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; |
---|
1721 | |
---|
1722 | if (sc->fectype & FECFLAG_AVB) { |
---|
1723 | sc->rxbuf_align = 64; |
---|
1724 | sc->txbuf_align = 1; |
---|
1725 | } else { |
---|
1726 | sc->rxbuf_align = 16; |
---|
1727 | sc->txbuf_align = 16; |
---|
1728 | } |
---|
1729 | |
---|
1730 | /* |
---|
1731 | * We have to be told what kind of electrical connection exists between |
---|
1732 | * the MAC and PHY or we can't operate correctly. |
---|
1733 | */ |
---|
1734 | if ((ofw_node = ofw_bus_get_node(dev)) == -1) { |
---|
1735 | device_printf(dev, "Impossible: Can't find ofw bus node\n"); |
---|
1736 | error = ENXIO; |
---|
1737 | goto out; |
---|
1738 | } |
---|
1739 | if (OF_searchprop(ofw_node, "phy-mode", |
---|
1740 | phy_conn_name, sizeof(phy_conn_name)) != -1) { |
---|
1741 | if (strcasecmp(phy_conn_name, "mii") == 0) |
---|
1742 | sc->phy_conn_type = PHY_CONN_MII; |
---|
1743 | else if (strcasecmp(phy_conn_name, "rmii") == 0) |
---|
1744 | sc->phy_conn_type = PHY_CONN_RMII; |
---|
1745 | #ifndef __rtems__ |
---|
1746 | else if (strcasecmp(phy_conn_name, "rgmii") == 0) |
---|
1747 | #else /* __rtems__ */ |
---|
1748 | else if (strncasecmp(phy_conn_name, "rgmii", 5) == 0) |
---|
1749 | #endif /* __rtems__ */ |
---|
1750 | sc->phy_conn_type = PHY_CONN_RGMII; |
---|
1751 | } |
---|
1752 | if (sc->phy_conn_type == PHY_CONN_UNKNOWN) { |
---|
1753 | device_printf(sc->dev, "No valid 'phy-mode' " |
---|
1754 | "property found in FDT data for device.\n"); |
---|
1755 | #ifndef __rtems__ |
---|
1756 | error = ENOATTR; |
---|
1757 | #else /* __rtems__ */ |
---|
1758 | error = ENXIO; |
---|
1759 | #endif /* __rtems__ */ |
---|
1760 | goto out; |
---|
1761 | } |
---|
1762 | |
---|
1763 | callout_init_mtx(&sc->ffec_callout, &sc->mtx, 0); |
---|
1764 | |
---|
1765 | /* Allocate bus resources for accessing the hardware. */ |
---|
1766 | rid = 0; |
---|
1767 | sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, |
---|
1768 | RF_ACTIVE); |
---|
1769 | if (sc->mem_res == NULL) { |
---|
1770 | device_printf(dev, "could not allocate memory resources.\n"); |
---|
1771 | error = ENOMEM; |
---|
1772 | goto out; |
---|
1773 | } |
---|
1774 | for (irq = 0; irq < MAX_IRQ_COUNT; ++irq) { |
---|
1775 | rid = irq; |
---|
1776 | sc->irq_res[irq] = bus_alloc_resource_any(dev, SYS_RES_IRQ, |
---|
1777 | &rid, RF_ACTIVE); |
---|
1778 | if (sc->irq_res[irq] == NULL) |
---|
1779 | break; |
---|
1780 | } |
---|
1781 | sc->irq_count = irq; |
---|
1782 | if (irq == 0) { |
---|
1783 | device_printf(dev, "could not allocate interrupt resources.\n"); |
---|
1784 | error = ENOMEM; |
---|
1785 | goto out; |
---|
1786 | } |
---|
1787 | |
---|
1788 | /* |
---|
1789 | * Set up TX descriptor ring, descriptors, and dma maps. |
---|
1790 | */ |
---|
1791 | error = bus_dma_tag_create( |
---|
1792 | bus_get_dma_tag(dev), /* Parent tag. */ |
---|
1793 | FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */ |
---|
1794 | BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ |
---|
1795 | BUS_SPACE_MAXADDR, /* highaddr */ |
---|
1796 | NULL, NULL, /* filter, filterarg */ |
---|
1797 | TX_DESC_SIZE, 1, /* maxsize, nsegments */ |
---|
1798 | TX_DESC_SIZE, /* maxsegsize */ |
---|
1799 | 0, /* flags */ |
---|
1800 | NULL, NULL, /* lockfunc, lockarg */ |
---|
1801 | &sc->txdesc_tag); |
---|
1802 | if (error != 0) { |
---|
1803 | device_printf(sc->dev, |
---|
1804 | "could not create TX ring DMA tag.\n"); |
---|
1805 | goto out; |
---|
1806 | } |
---|
1807 | |
---|
1808 | error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring, |
---|
1809 | BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->txdesc_map); |
---|
1810 | if (error != 0) { |
---|
1811 | device_printf(sc->dev, |
---|
1812 | "could not allocate TX descriptor ring.\n"); |
---|
1813 | goto out; |
---|
1814 | } |
---|
1815 | |
---|
1816 | error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, sc->txdesc_ring, |
---|
1817 | TX_DESC_SIZE, ffec_get1paddr, &sc->txdesc_ring_paddr, 0); |
---|
1818 | if (error != 0) { |
---|
1819 | device_printf(sc->dev, |
---|
1820 | "could not load TX descriptor ring map.\n"); |
---|
1821 | goto out; |
---|
1822 | } |
---|
1823 | |
---|
1824 | error = bus_dma_tag_create( |
---|
1825 | bus_get_dma_tag(dev), /* Parent tag. */ |
---|
1826 | sc->txbuf_align, 0, /* alignment, boundary */ |
---|
1827 | BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ |
---|
1828 | BUS_SPACE_MAXADDR, /* highaddr */ |
---|
1829 | NULL, NULL, /* filter, filterarg */ |
---|
1830 | MCLBYTES, TX_MAX_DMA_SEGS, /* maxsize, nsegments */ |
---|
1831 | MCLBYTES, /* maxsegsize */ |
---|
1832 | 0, /* flags */ |
---|
1833 | NULL, NULL, /* lockfunc, lockarg */ |
---|
1834 | &sc->txbuf_tag); |
---|
1835 | if (error != 0) { |
---|
1836 | device_printf(sc->dev, |
---|
1837 | "could not create TX ring DMA tag.\n"); |
---|
1838 | goto out; |
---|
1839 | } |
---|
1840 | |
---|
1841 | for (idx = 0; idx < TX_DESC_COUNT; ++idx) { |
---|
1842 | error = bus_dmamap_create(sc->txbuf_tag, 0, |
---|
1843 | &sc->txbuf_map[idx].map); |
---|
1844 | if (error != 0) { |
---|
1845 | device_printf(sc->dev, |
---|
1846 | "could not create TX buffer DMA map.\n"); |
---|
1847 | goto out; |
---|
1848 | } |
---|
1849 | sc->txdesc_ring[idx].buf_paddr = 0; |
---|
1850 | sc->txdesc_ring[idx].flags_len = |
---|
1851 | ((idx == TX_DESC_COUNT - 1) ? FEC_TXDESC_WRAP : 0); |
---|
1852 | } |
---|
1853 | |
---|
1854 | /* |
---|
1855 | * Set up RX descriptor ring, descriptors, dma maps, and mbufs. |
---|
1856 | */ |
---|
1857 | error = bus_dma_tag_create( |
---|
1858 | bus_get_dma_tag(dev), /* Parent tag. */ |
---|
1859 | FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */ |
---|
1860 | BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ |
---|
1861 | BUS_SPACE_MAXADDR, /* highaddr */ |
---|
1862 | NULL, NULL, /* filter, filterarg */ |
---|
1863 | RX_DESC_SIZE, 1, /* maxsize, nsegments */ |
---|
1864 | RX_DESC_SIZE, /* maxsegsize */ |
---|
1865 | 0, /* flags */ |
---|
1866 | NULL, NULL, /* lockfunc, lockarg */ |
---|
1867 | &sc->rxdesc_tag); |
---|
1868 | if (error != 0) { |
---|
1869 | device_printf(sc->dev, |
---|
1870 | "could not create RX ring DMA tag.\n"); |
---|
1871 | goto out; |
---|
1872 | } |
---|
1873 | |
---|
1874 | error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring, |
---|
1875 | BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rxdesc_map); |
---|
1876 | if (error != 0) { |
---|
1877 | device_printf(sc->dev, |
---|
1878 | "could not allocate RX descriptor ring.\n"); |
---|
1879 | goto out; |
---|
1880 | } |
---|
1881 | |
---|
1882 | error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, sc->rxdesc_ring, |
---|
1883 | RX_DESC_SIZE, ffec_get1paddr, &sc->rxdesc_ring_paddr, 0); |
---|
1884 | if (error != 0) { |
---|
1885 | device_printf(sc->dev, |
---|
1886 | "could not load RX descriptor ring map.\n"); |
---|
1887 | goto out; |
---|
1888 | } |
---|
1889 | |
---|
1890 | error = bus_dma_tag_create( |
---|
1891 | bus_get_dma_tag(dev), /* Parent tag. */ |
---|
1892 | 1, 0, /* alignment, boundary */ |
---|
1893 | BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ |
---|
1894 | BUS_SPACE_MAXADDR, /* highaddr */ |
---|
1895 | NULL, NULL, /* filter, filterarg */ |
---|
1896 | MCLBYTES, 1, /* maxsize, nsegments */ |
---|
1897 | MCLBYTES, /* maxsegsize */ |
---|
1898 | 0, /* flags */ |
---|
1899 | NULL, NULL, /* lockfunc, lockarg */ |
---|
1900 | &sc->rxbuf_tag); |
---|
1901 | if (error != 0) { |
---|
1902 | device_printf(sc->dev, |
---|
1903 | "could not create RX buf DMA tag.\n"); |
---|
1904 | goto out; |
---|
1905 | } |
---|
1906 | |
---|
1907 | for (idx = 0; idx < RX_DESC_COUNT; ++idx) { |
---|
1908 | error = bus_dmamap_create(sc->rxbuf_tag, 0, |
---|
1909 | &sc->rxbuf_map[idx].map); |
---|
1910 | if (error != 0) { |
---|
1911 | device_printf(sc->dev, |
---|
1912 | "could not create RX buffer DMA map.\n"); |
---|
1913 | goto out; |
---|
1914 | } |
---|
1915 | if ((m = ffec_alloc_mbufcl(sc)) == NULL) { |
---|
1916 | device_printf(dev, "Could not alloc mbuf\n"); |
---|
1917 | error = ENOMEM; |
---|
1918 | goto out; |
---|
1919 | } |
---|
1920 | if ((error = ffec_setup_rxbuf(sc, idx, m)) != 0) { |
---|
1921 | device_printf(sc->dev, |
---|
1922 | "could not create new RX buffer.\n"); |
---|
1923 | goto out; |
---|
1924 | } |
---|
1925 | } |
---|
1926 | |
---|
1927 | /* Try to get the MAC address from the hardware before resetting it. */ |
---|
1928 | ffec_get_hwaddr(sc, eaddr); |
---|
1929 | |
---|
1930 | /* Reset the hardware. Disables all interrupts. */ |
---|
1931 | if (sc->fectype & FECFLAG_AVB) |
---|
1932 | /* |
---|
1933 | * Avoid AXI bus issues due to a MAC reset, see Linux for more |
---|
1934 | * details. |
---|
1935 | */ |
---|
1936 | WR4(sc, FEC_ECR_REG, 0); |
---|
1937 | else |
---|
1938 | WR4(sc, FEC_ECR_REG, FEC_ECR_RESET); |
---|
1939 | |
---|
1940 | /* Setup interrupt handler. */ |
---|
1941 | for (irq = 0; irq < sc->irq_count; ++irq) { |
---|
1942 | error = bus_setup_intr(dev, sc->irq_res[irq], |
---|
1943 | INTR_TYPE_NET | INTR_MPSAFE, NULL, ffec_intr, sc, |
---|
1944 | &sc->intr_cookie[irq]); |
---|
1945 | if (error != 0) { |
---|
1946 | device_printf(dev, |
---|
1947 | "could not setup interrupt handler.\n"); |
---|
1948 | goto out; |
---|
1949 | } |
---|
1950 | } |
---|
1951 | |
---|
1952 | /* |
---|
1953 | * Set up the PHY control register. |
---|
1954 | * |
---|
1955 | * Speed formula for ENET is md_clock = mac_clock / ((N + 1) * 2). |
---|
1956 | * Speed formula for FEC is md_clock = mac_clock / (N * 2) |
---|
1957 | * |
---|
1958 | * XXX - Revisit this... |
---|
1959 | * |
---|
1960 | * For a Wandboard imx6 (ENET) I was originally using 4, but the uboot |
---|
1961 | * code uses 10. Both values seem to work, but I suspect many modern |
---|
1962 | * PHY parts can do mdio at speeds far above the standard 2.5 MHz. |
---|
1963 | * |
---|
1964 | * Different imx manuals use confusingly different terminology (things |
---|
1965 | * like "system clock" and "internal module clock") with examples that |
---|
1966 | * use frequencies that have nothing to do with ethernet, giving the |
---|
1967 | * vague impression that maybe the clock in question is the periphclock |
---|
1968 | * or something. In fact, on an imx53 development board (FEC), |
---|
1969 | * measuring the mdio clock at the pin on the PHY and playing with |
---|
1970 | * various divisors showed that the root speed was 66 MHz (clk_ipg_root |
---|
1971 | * aka periphclock) and 13 was the right divisor. |
---|
1972 | * |
---|
1973 | * All in all, it seems likely that 13 is a safe divisor for now, |
---|
1974 | * because if we really do need to base it on the peripheral clock |
---|
1975 | * speed, then we need a platform-independant get-clock-freq API. |
---|
1976 | */ |
---|
1977 | mscr = 13 << FEC_MSCR_MII_SPEED_SHIFT; |
---|
1978 | if (OF_hasprop(ofw_node, "phy-disable-preamble")) { |
---|
1979 | mscr |= FEC_MSCR_DIS_PRE; |
---|
1980 | if (bootverbose) |
---|
1981 | device_printf(dev, "PHY preamble disabled\n"); |
---|
1982 | } |
---|
1983 | WR4(sc, FEC_MSCR_REG, mscr); |
---|
1984 | |
---|
1985 | /* Configure defaults for interrupts coalescing */ |
---|
1986 | sc->rx_ic_time = 768; |
---|
1987 | sc->rx_ic_count = RX_DESC_COUNT / 4; |
---|
1988 | sc->tx_ic_time = 768; |
---|
1989 | sc->tx_ic_count = TX_DESC_COUNT / 4; |
---|
1990 | |
---|
1991 | ffec_add_sysctls(sc); |
---|
1992 | |
---|
1993 | /* Set up the ethernet interface. */ |
---|
1994 | sc->ifp = ifp = if_alloc(IFT_ETHER); |
---|
1995 | |
---|
1996 | ifp->if_softc = sc; |
---|
1997 | if_initname(ifp, device_get_name(dev), device_get_unit(dev)); |
---|
1998 | ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; |
---|
1999 | ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6 | |
---|
2000 | IFCAP_VLAN_MTU; |
---|
2001 | ifp->if_capenable = ifp->if_capabilities; |
---|
2002 | ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP; |
---|
2003 | ifp->if_start = ffec_txstart; |
---|
2004 | ifp->if_ioctl = ffec_ioctl; |
---|
2005 | ifp->if_init = ffec_init; |
---|
2006 | IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1); |
---|
2007 | ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1; |
---|
2008 | IFQ_SET_READY(&ifp->if_snd); |
---|
2009 | ifp->if_hdrlen = sizeof(struct ether_vlan_header); |
---|
2010 | |
---|
2011 | #if 0 /* XXX The hardware keeps stats we could use for these. */ |
---|
2012 | ifp->if_linkmib = &sc->mibdata; |
---|
2013 | ifp->if_linkmiblen = sizeof(sc->mibdata); |
---|
2014 | #endif |
---|
2015 | |
---|
2016 | /* Set up the miigasket hardware (if any). */ |
---|
2017 | ffec_miigasket_setup(sc); |
---|
2018 | |
---|
2019 | /* Attach the mii driver. */ |
---|
2020 | error = mii_attach(dev, &sc->miibus, ifp, ffec_media_change, |
---|
2021 | ffec_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, |
---|
2022 | (sc->fectype & FECTYPE_MVF) ? MIIF_FORCEANEG : 0); |
---|
2023 | if (error != 0) { |
---|
2024 | device_printf(dev, "PHY attach failed\n"); |
---|
2025 | goto out; |
---|
2026 | } |
---|
2027 | sc->mii_softc = device_get_softc(sc->miibus); |
---|
2028 | |
---|
2029 | /* All ready to run, attach the ethernet interface. */ |
---|
2030 | ether_ifattach(ifp, eaddr); |
---|
2031 | sc->is_attached = true; |
---|
2032 | |
---|
2033 | error = 0; |
---|
2034 | out: |
---|
2035 | |
---|
2036 | if (error != 0) |
---|
2037 | ffec_detach(dev); |
---|
2038 | |
---|
2039 | return (error); |
---|
2040 | } |
---|
2041 | |
---|
2042 | static int |
---|
2043 | ffec_probe(device_t dev) |
---|
2044 | { |
---|
2045 | uintptr_t fectype; |
---|
2046 | |
---|
2047 | if (!ofw_bus_status_okay(dev)) |
---|
2048 | return (ENXIO); |
---|
2049 | |
---|
2050 | fectype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; |
---|
2051 | if (fectype == FECTYPE_NONE) |
---|
2052 | return (ENXIO); |
---|
2053 | |
---|
2054 | device_set_desc(dev, (fectype & FECFLAG_GBE) ? |
---|
2055 | "Freescale Gigabit Ethernet Controller" : |
---|
2056 | "Freescale Fast Ethernet Controller"); |
---|
2057 | |
---|
2058 | return (BUS_PROBE_DEFAULT); |
---|
2059 | } |
---|
2060 | |
---|
2061 | |
---|
2062 | static device_method_t ffec_methods[] = { |
---|
2063 | /* Device interface. */ |
---|
2064 | DEVMETHOD(device_probe, ffec_probe), |
---|
2065 | DEVMETHOD(device_attach, ffec_attach), |
---|
2066 | DEVMETHOD(device_detach, ffec_detach), |
---|
2067 | |
---|
2068 | /* |
---|
2069 | DEVMETHOD(device_shutdown, ffec_shutdown), |
---|
2070 | DEVMETHOD(device_suspend, ffec_suspend), |
---|
2071 | DEVMETHOD(device_resume, ffec_resume), |
---|
2072 | */ |
---|
2073 | |
---|
2074 | /* MII interface. */ |
---|
2075 | DEVMETHOD(miibus_readreg, ffec_miibus_readreg), |
---|
2076 | DEVMETHOD(miibus_writereg, ffec_miibus_writereg), |
---|
2077 | DEVMETHOD(miibus_statchg, ffec_miibus_statchg), |
---|
2078 | |
---|
2079 | DEVMETHOD_END |
---|
2080 | }; |
---|
2081 | |
---|
2082 | static driver_t ffec_driver = { |
---|
2083 | "ffec", |
---|
2084 | ffec_methods, |
---|
2085 | sizeof(struct ffec_softc) |
---|
2086 | }; |
---|
2087 | |
---|
2088 | static devclass_t ffec_devclass; |
---|
2089 | |
---|
2090 | DRIVER_MODULE(ffec, simplebus, ffec_driver, ffec_devclass, 0, 0); |
---|
2091 | DRIVER_MODULE(miibus, ffec, miibus_driver, miibus_devclass, 0, 0); |
---|
2092 | |
---|
2093 | MODULE_DEPEND(ffec, ether, 1, 1, 1); |
---|
2094 | MODULE_DEPEND(ffec, miibus, 1, 1, 1); |
---|