source: rtems-libbsd/freebsd/sys/dev/ffec/if_ffec.c @ e2e4bf4

55-freebsd-126-freebsd-12
Last change on this file since e2e4bf4 was e2e4bf4, checked in by Sebastian Huber <sebastian.huber@…>, on 09/27/17 at 07:42:10

ffec: Avoid AXI bus issues due to a MAC reset

  • Property mode set to 100644
File size: 47.6 KB
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[807b5bb]1#include <machine/rtems-bsd-kernel-space.h>
2
3/*-
4 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 */
29
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD$");
32
33/*
34 * Driver for Freescale Fast Ethernet Controller, found on imx-series SoCs among
35 * others.  Also works for the ENET Gigibit controller found on imx6 and imx28,
36 * but the driver doesn't currently use any of the ENET advanced features other
37 * than enabling gigabit.
38 *
39 * The interface name 'fec' is already taken by netgraph's Fast Etherchannel
40 * (netgraph/ng_fec.c), so we use 'ffec'.
41 *
42 * Requires an FDT entry with at least these properties:
43 *   fec: ethernet@02188000 {
44 *      compatible = "fsl,imxNN-fec";
45 *      reg = <0x02188000 0x4000>;
46 *      interrupts = <150 151>;
47 *      phy-mode = "rgmii";
48 *      phy-disable-preamble; // optional
49 *   };
50 * The second interrupt number is for IEEE-1588, and is not currently used; it
51 * need not be present.  phy-mode must be one of: "mii", "rmii", "rgmii".
52 * There is also an optional property, phy-disable-preamble, which if present
53 * will disable the preamble bits, cutting the size of each mdio transaction
54 * (and thus the busy-wait time) in half.
55 */
56
57#include <sys/param.h>
58#include <sys/systm.h>
59#include <sys/bus.h>
60#include <sys/endian.h>
61#include <sys/kernel.h>
62#include <sys/lock.h>
63#include <sys/malloc.h>
64#include <sys/mbuf.h>
65#include <sys/module.h>
66#include <sys/mutex.h>
67#include <sys/rman.h>
68#include <sys/socket.h>
69#include <sys/sockio.h>
70#include <sys/sysctl.h>
71
72#include <machine/bus.h>
73
74#include <net/bpf.h>
75#include <net/if.h>
76#include <net/ethernet.h>
77#include <net/if_dl.h>
78#include <net/if_media.h>
79#include <net/if_types.h>
80#include <net/if_var.h>
81#include <net/if_vlan_var.h>
82
83#include <dev/ffec/if_ffecreg.h>
84#include <dev/ofw/ofw_bus.h>
85#include <dev/ofw/ofw_bus_subr.h>
86#include <dev/mii/mii.h>
87#include <dev/mii/miivar.h>
88#include <rtems/bsd/local/miibus_if.h>
89
90/*
91 * There are small differences in the hardware on various SoCs.  Not every SoC
92 * we support has its own FECTYPE; most work as GENERIC and only the ones that
93 * need different handling get their own entry.  In addition to the types in
94 * this list, there are some flags below that can be ORed into the upper bits.
95 */
96enum {
97        FECTYPE_NONE,
98        FECTYPE_GENERIC,
99        FECTYPE_IMX53,
100        FECTYPE_IMX6,
101        FECTYPE_MVF,
102};
103
104/*
105 * Flags that describe general differences between the FEC hardware in various
106 * SoCs.  These are ORed into the FECTYPE enum values.
107 */
108#define FECTYPE_MASK            0x0000ffff
[ba0b059]109#define FECFLAG_GBE             (1 << 16)
110#define FECFLAG_AVB             (1 << 17)
[807b5bb]111
112/*
113 * Table of supported FDT compat strings and their associated FECTYPE values.
114 */
115static struct ofw_compat_data compat_data[] = {
116        {"fsl,imx51-fec",       FECTYPE_GENERIC},
117        {"fsl,imx53-fec",       FECTYPE_IMX53},
118        {"fsl,imx6q-fec",       FECTYPE_IMX6 | FECFLAG_GBE},
119        {"fsl,mvf600-fec",      FECTYPE_MVF},
120        {"fsl,mvf-fec",         FECTYPE_MVF},
[ba0b059]121        {"fsl,imx7d-fec",       FECTYPE_IMX6 | FECFLAG_GBE | FECFLAG_AVB},
[807b5bb]122        {NULL,                  FECTYPE_NONE},
123};
124
125/*
126 * Driver data and defines.
127 */
128#define RX_DESC_COUNT   64
129#define RX_DESC_SIZE    (sizeof(struct ffec_hwdesc) * RX_DESC_COUNT)
130#define TX_DESC_COUNT   64
131#define TX_DESC_SIZE    (sizeof(struct ffec_hwdesc) * TX_DESC_COUNT)
132
133#define WATCHDOG_TIMEOUT_SECS   5
134#define STATS_HARVEST_INTERVAL  3
135
136struct ffec_bufmap {
137        struct mbuf     *mbuf;
138        bus_dmamap_t    map;
139};
140
141enum {
142        PHY_CONN_UNKNOWN,
143        PHY_CONN_MII,
144        PHY_CONN_RMII,
145        PHY_CONN_RGMII
146};
147
148struct ffec_softc {
149        device_t                dev;
150        device_t                miibus;
151        struct mii_data *       mii_softc;
152        struct ifnet            *ifp;
153        int                     if_flags;
154        struct mtx              mtx;
155        struct resource         *irq_res;
156        struct resource         *mem_res;
157        void *                  intr_cookie;
158        struct callout          ffec_callout;
159        uint8_t                 phy_conn_type;
[ba0b059]160        uintptr_t               fectype;
[807b5bb]161        boolean_t               link_is_up;
162        boolean_t               is_attached;
163        boolean_t               is_detaching;
164        int                     tx_watchdog_count;
165        int                     stats_harvest_count;
[ba0b059]166        int                     rxbuf_align;
167        int                     txbuf_align;
[807b5bb]168
169        bus_dma_tag_t           rxdesc_tag;
170        bus_dmamap_t            rxdesc_map;
171        struct ffec_hwdesc      *rxdesc_ring;
172        bus_addr_t              rxdesc_ring_paddr;
173        bus_dma_tag_t           rxbuf_tag;
174        struct ffec_bufmap      rxbuf_map[RX_DESC_COUNT];
175        uint32_t                rx_idx;
176
177        bus_dma_tag_t           txdesc_tag;
178        bus_dmamap_t            txdesc_map;
179        struct ffec_hwdesc      *txdesc_ring;
180        bus_addr_t              txdesc_ring_paddr;
181        bus_dma_tag_t           txbuf_tag;
182        struct ffec_bufmap      txbuf_map[TX_DESC_COUNT];
183        uint32_t                tx_idx_head;
184        uint32_t                tx_idx_tail;
185        int                     txcount;
186};
187
188#define FFEC_LOCK(sc)                   mtx_lock(&(sc)->mtx)
189#define FFEC_UNLOCK(sc)                 mtx_unlock(&(sc)->mtx)
190#define FFEC_LOCK_INIT(sc)              mtx_init(&(sc)->mtx, \
191            device_get_nameunit((sc)->dev), MTX_NETWORK_LOCK, MTX_DEF)
192#define FFEC_LOCK_DESTROY(sc)           mtx_destroy(&(sc)->mtx);
193#define FFEC_ASSERT_LOCKED(sc)          mtx_assert(&(sc)->mtx, MA_OWNED);
194#define FFEC_ASSERT_UNLOCKED(sc)        mtx_assert(&(sc)->mtx, MA_NOTOWNED);
195
196static void ffec_init_locked(struct ffec_softc *sc);
197static void ffec_stop_locked(struct ffec_softc *sc);
198static void ffec_txstart_locked(struct ffec_softc *sc);
199static void ffec_txfinish_locked(struct ffec_softc *sc);
200
201static inline uint16_t
202RD2(struct ffec_softc *sc, bus_size_t off)
203{
204
205        return (bus_read_2(sc->mem_res, off));
206}
207
208static inline void
209WR2(struct ffec_softc *sc, bus_size_t off, uint16_t val)
210{
211
212        bus_write_2(sc->mem_res, off, val);
213}
214
215static inline uint32_t
216RD4(struct ffec_softc *sc, bus_size_t off)
217{
218
219        return (bus_read_4(sc->mem_res, off));
220}
221
222static inline void
223WR4(struct ffec_softc *sc, bus_size_t off, uint32_t val)
224{
225
226        bus_write_4(sc->mem_res, off, val);
227}
228
229static inline uint32_t
230next_rxidx(struct ffec_softc *sc, uint32_t curidx)
231{
232
233        return ((curidx == RX_DESC_COUNT - 1) ? 0 : curidx + 1);
234}
235
236static inline uint32_t
237next_txidx(struct ffec_softc *sc, uint32_t curidx)
238{
239
240        return ((curidx == TX_DESC_COUNT - 1) ? 0 : curidx + 1);
241}
242
243static void
244ffec_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
245{
246
247        if (error != 0)
248                return;
249        *(bus_addr_t *)arg = segs[0].ds_addr;
250}
251
252static void
253ffec_miigasket_setup(struct ffec_softc *sc)
254{
255        uint32_t ifmode;
256
257        /*
258         * We only need the gasket for MII and RMII connections on certain SoCs.
259         */
260
261        switch (sc->fectype & FECTYPE_MASK)
262        {
263        case FECTYPE_IMX53:
264                break;
265        default:
266                return;
267        }
268
269        switch (sc->phy_conn_type)
270        {
271        case PHY_CONN_MII:
272                ifmode = 0;
273                break;
274        case PHY_CONN_RMII:
275                ifmode = FEC_MIIGSK_CFGR_IF_MODE_RMII;
276                break;
277        default:
278                return;
279        }
280
281        /*
282         * Disable the gasket, configure for either MII or RMII, then enable.
283         */
284
285        WR2(sc, FEC_MIIGSK_ENR, 0);
286        while (RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY)
287                continue;
288
289        WR2(sc, FEC_MIIGSK_CFGR, ifmode);
290
291        WR2(sc, FEC_MIIGSK_ENR, FEC_MIIGSK_ENR_EN);
292        while (!(RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY))
293                continue;
294}
295
296static boolean_t
297ffec_miibus_iowait(struct ffec_softc *sc)
298{
299        uint32_t timeout;
300
301        for (timeout = 10000; timeout != 0; --timeout)
302                if (RD4(sc, FEC_IER_REG) & FEC_IER_MII)
303                        return (true);
304
305        return (false);
306}
307
308static int
309ffec_miibus_readreg(device_t dev, int phy, int reg)
310{
311        struct ffec_softc *sc;
312        int val;
313
314        sc = device_get_softc(dev);
315
316        WR4(sc, FEC_IER_REG, FEC_IER_MII);
317
318        WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_READ |
319            FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE |
320            ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) |
321            ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK));
322
323        if (!ffec_miibus_iowait(sc)) {
324                device_printf(dev, "timeout waiting for mii read\n");
325                return (-1); /* All-ones is a symptom of bad mdio. */
326        }
327
328        val = RD4(sc, FEC_MMFR_REG) & FEC_MMFR_DATA_MASK;
329
330        return (val);
331}
332
333static int
334ffec_miibus_writereg(device_t dev, int phy, int reg, int val)
335{
336        struct ffec_softc *sc;
337
338        sc = device_get_softc(dev);
339
340        WR4(sc, FEC_IER_REG, FEC_IER_MII);
341
342        WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_WRITE |
343            FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE |
344            ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) |
345            ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK) |
346            (val & FEC_MMFR_DATA_MASK));
347
348        if (!ffec_miibus_iowait(sc)) {
349                device_printf(dev, "timeout waiting for mii write\n");
350                return (-1);
351        }
352
353        return (0);
354}
355
356static void
357ffec_miibus_statchg(device_t dev)
358{
359        struct ffec_softc *sc;
360        struct mii_data *mii;
361        uint32_t ecr, rcr, tcr;
362
363        /*
364         * Called by the MII bus driver when the PHY establishes link to set the
365         * MAC interface registers.
366         */
367
368        sc = device_get_softc(dev);
369
370        FFEC_ASSERT_LOCKED(sc);
371
372        mii = sc->mii_softc;
373
374        if (mii->mii_media_status & IFM_ACTIVE)
375                sc->link_is_up = true;
376        else
377                sc->link_is_up = false;
378
379        ecr = RD4(sc, FEC_ECR_REG) & ~FEC_ECR_SPEED;
380        rcr = RD4(sc, FEC_RCR_REG) & ~(FEC_RCR_RMII_10T | FEC_RCR_RMII_MODE |
381            FEC_RCR_RGMII_EN | FEC_RCR_DRT | FEC_RCR_FCE);
382        tcr = RD4(sc, FEC_TCR_REG) & ~FEC_TCR_FDEN;
383
384        rcr |= FEC_RCR_MII_MODE; /* Must always be on even for R[G]MII. */
385        switch (sc->phy_conn_type) {
386        case PHY_CONN_MII:
387                break;
388        case PHY_CONN_RMII:
389                rcr |= FEC_RCR_RMII_MODE;
390                break;
391        case PHY_CONN_RGMII:
392                rcr |= FEC_RCR_RGMII_EN;
393                break;
394        }
395
396        switch (IFM_SUBTYPE(mii->mii_media_active)) {
397        case IFM_1000_T:
398        case IFM_1000_SX:
399                ecr |= FEC_ECR_SPEED;
400                break;
401        case IFM_100_TX:
402                /* Not-FEC_ECR_SPEED + not-FEC_RCR_RMII_10T means 100TX */
403                break;
404        case IFM_10_T:
405                rcr |= FEC_RCR_RMII_10T;
406                break;
407        case IFM_NONE:
408                sc->link_is_up = false;
409                return;
410        default:
411                sc->link_is_up = false;
412                device_printf(dev, "Unsupported media %u\n",
413                    IFM_SUBTYPE(mii->mii_media_active));
414                return;
415        }
416
417        if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
418                tcr |= FEC_TCR_FDEN;
419        else
420                rcr |= FEC_RCR_DRT;
421
422        if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLOW) != 0)
423                rcr |= FEC_RCR_FCE;
424
425        WR4(sc, FEC_RCR_REG, rcr);
426        WR4(sc, FEC_TCR_REG, tcr);
427        WR4(sc, FEC_ECR_REG, ecr);
428}
429
430static void
431ffec_media_status(struct ifnet * ifp, struct ifmediareq *ifmr)
432{
433        struct ffec_softc *sc;
434        struct mii_data *mii;
435
436
437        sc = ifp->if_softc;
438        mii = sc->mii_softc;
439        FFEC_LOCK(sc);
440        mii_pollstat(mii);
441        ifmr->ifm_active = mii->mii_media_active;
442        ifmr->ifm_status = mii->mii_media_status;
443        FFEC_UNLOCK(sc);
444}
445
446static int
447ffec_media_change_locked(struct ffec_softc *sc)
448{
449
450        return (mii_mediachg(sc->mii_softc));
451}
452
453static int
454ffec_media_change(struct ifnet * ifp)
455{
456        struct ffec_softc *sc;
457        int error;
458
459        sc = ifp->if_softc;
460
461        FFEC_LOCK(sc);
462        error = ffec_media_change_locked(sc);
463        FFEC_UNLOCK(sc);
464        return (error);
465}
466
467static void ffec_clear_stats(struct ffec_softc *sc)
468{
469
470        WR4(sc, FEC_RMON_R_PACKETS, 0);
471        WR4(sc, FEC_RMON_R_MC_PKT, 0);
472        WR4(sc, FEC_RMON_R_CRC_ALIGN, 0);
473        WR4(sc, FEC_RMON_R_UNDERSIZE, 0);
474        WR4(sc, FEC_RMON_R_OVERSIZE, 0);
475        WR4(sc, FEC_RMON_R_FRAG, 0);
476        WR4(sc, FEC_RMON_R_JAB, 0);
477        WR4(sc, FEC_RMON_T_PACKETS, 0);
478        WR4(sc, FEC_RMON_T_MC_PKT, 0);
479        WR4(sc, FEC_RMON_T_CRC_ALIGN, 0);
480        WR4(sc, FEC_RMON_T_UNDERSIZE, 0);
481        WR4(sc, FEC_RMON_T_OVERSIZE , 0);
482        WR4(sc, FEC_RMON_T_FRAG, 0);
483        WR4(sc, FEC_RMON_T_JAB, 0);
484        WR4(sc, FEC_RMON_T_COL, 0);
485}
486
487static void
488ffec_harvest_stats(struct ffec_softc *sc)
489{
490        struct ifnet *ifp;
491
492        /* We don't need to harvest too often. */
493        if (++sc->stats_harvest_count < STATS_HARVEST_INTERVAL)
494                return;
495
496        /*
497         * Try to avoid harvesting unless the IDLE flag is on, but if it has
498         * been too long just go ahead and do it anyway, the worst that'll
499         * happen is we'll lose a packet count or two as we clear at the end.
500         */
501        if (sc->stats_harvest_count < (2 * STATS_HARVEST_INTERVAL) &&
502            ((RD4(sc, FEC_MIBC_REG) & FEC_MIBC_IDLE) == 0))
503                return;
504
505        sc->stats_harvest_count = 0;
506        ifp = sc->ifp;
507
508        if_inc_counter(ifp, IFCOUNTER_IPACKETS, RD4(sc, FEC_RMON_R_PACKETS));
509        if_inc_counter(ifp, IFCOUNTER_IMCASTS, RD4(sc, FEC_RMON_R_MC_PKT));
510        if_inc_counter(ifp, IFCOUNTER_IERRORS,
511            RD4(sc, FEC_RMON_R_CRC_ALIGN) + RD4(sc, FEC_RMON_R_UNDERSIZE) +
512            RD4(sc, FEC_RMON_R_OVERSIZE) + RD4(sc, FEC_RMON_R_FRAG) +
513            RD4(sc, FEC_RMON_R_JAB));
514
515        if_inc_counter(ifp, IFCOUNTER_OPACKETS, RD4(sc, FEC_RMON_T_PACKETS));
516        if_inc_counter(ifp, IFCOUNTER_OMCASTS, RD4(sc, FEC_RMON_T_MC_PKT));
517        if_inc_counter(ifp, IFCOUNTER_OERRORS,
518            RD4(sc, FEC_RMON_T_CRC_ALIGN) + RD4(sc, FEC_RMON_T_UNDERSIZE) +
519            RD4(sc, FEC_RMON_T_OVERSIZE) + RD4(sc, FEC_RMON_T_FRAG) +
520            RD4(sc, FEC_RMON_T_JAB));
521
522        if_inc_counter(ifp, IFCOUNTER_COLLISIONS, RD4(sc, FEC_RMON_T_COL));
523
524        ffec_clear_stats(sc);
525}
526
527static void
528ffec_tick(void *arg)
529{
530        struct ffec_softc *sc;
531        struct ifnet *ifp;
532        int link_was_up;
533
534        sc = arg;
535
536        FFEC_ASSERT_LOCKED(sc);
537
538        ifp = sc->ifp;
539
540        if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
541            return;
542
543        /*
544         * Typical tx watchdog.  If this fires it indicates that we enqueued
545         * packets for output and never got a txdone interrupt for them.  Maybe
546         * it's a missed interrupt somehow, just pretend we got one.
547         */
548        if (sc->tx_watchdog_count > 0) {
549                if (--sc->tx_watchdog_count == 0) {
550                        ffec_txfinish_locked(sc);
551                }
552        }
553
554        /* Gather stats from hardware counters. */
555        ffec_harvest_stats(sc);
556
557        /* Check the media status. */
558        link_was_up = sc->link_is_up;
559        mii_tick(sc->mii_softc);
560        if (sc->link_is_up && !link_was_up)
561                ffec_txstart_locked(sc);
562
563        /* Schedule another check one second from now. */
564        callout_reset(&sc->ffec_callout, hz, ffec_tick, sc);
565}
566
567inline static uint32_t
568ffec_setup_txdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr,
569    uint32_t len)
570{
571        uint32_t nidx;
572        uint32_t flags;
573
574        nidx = next_txidx(sc, idx);
575
576        /* Addr/len 0 means we're clearing the descriptor after xmit done. */
577        if (paddr == 0 || len == 0) {
578                flags = 0;
579                --sc->txcount;
580        } else {
581                flags = FEC_TXDESC_READY | FEC_TXDESC_L | FEC_TXDESC_TC;
582                ++sc->txcount;
583        }
584        if (nidx == 0)
585                flags |= FEC_TXDESC_WRAP;
586
587        /*
588         * The hardware requires 32-bit physical addresses.  We set up the dma
589         * tag to indicate that, so the cast to uint32_t should never lose
590         * significant bits.
591         */
592        sc->txdesc_ring[idx].buf_paddr = (uint32_t)paddr;
593        sc->txdesc_ring[idx].flags_len = flags | len; /* Must be set last! */
594
595        return (nidx);
596}
597
598static int
599ffec_setup_txbuf(struct ffec_softc *sc, int idx, struct mbuf **mp)
600{
601        struct mbuf * m;
602        int error, nsegs;
603        struct bus_dma_segment seg;
604
605        if ((m = m_defrag(*mp, M_NOWAIT)) == NULL)
606                return (ENOMEM);
607        *mp = m;
608
609        error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map,
610            m, &seg, &nsegs, 0);
611        if (error != 0) {
612                return (ENOMEM);
613        }
[9c34735]614#ifndef __rtems__
[807b5bb]615        bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map,
616            BUS_DMASYNC_PREWRITE);
[9c34735]617#else /* __rtems__ */
618        rtems_cache_flush_multiple_data_lines((void *)seg.ds_addr, seg.ds_len);
619#endif /* __rtems__ */
[807b5bb]620
621        sc->txbuf_map[idx].mbuf = m;
622        ffec_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len);
623
624        return (0);
625
626}
627
628static void
629ffec_txstart_locked(struct ffec_softc *sc)
630{
631        struct ifnet *ifp;
632        struct mbuf *m;
633        int enqueued;
634
635        FFEC_ASSERT_LOCKED(sc);
636
637        if (!sc->link_is_up)
638                return;
639
640        ifp = sc->ifp;
641
642        if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
643                return;
644
645        enqueued = 0;
646
647        for (;;) {
648                if (sc->txcount == (TX_DESC_COUNT-1)) {
649                        ifp->if_drv_flags |= IFF_DRV_OACTIVE;
650                        break;
651                }
652                IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
653                if (m == NULL)
654                        break;
655                if (ffec_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) {
656                        IFQ_DRV_PREPEND(&ifp->if_snd, m);
657                        break;
658                }
659                BPF_MTAP(ifp, m);
660                sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head);
661                ++enqueued;
662        }
663
664        if (enqueued != 0) {
665                bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREWRITE);
666                WR4(sc, FEC_TDAR_REG, FEC_TDAR_TDAR);
667                bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTWRITE);
668                sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS;
669        }
670}
671
672static void
673ffec_txstart(struct ifnet *ifp)
674{
675        struct ffec_softc *sc = ifp->if_softc;
676
677        FFEC_LOCK(sc);
678        ffec_txstart_locked(sc);
679        FFEC_UNLOCK(sc);
680}
681
682static void
683ffec_txfinish_locked(struct ffec_softc *sc)
684{
685        struct ifnet *ifp;
686        struct ffec_hwdesc *desc;
687        struct ffec_bufmap *bmap;
688        boolean_t retired_buffer;
689
690        FFEC_ASSERT_LOCKED(sc);
691
692        /* XXX Can't set PRE|POST right now, but we need both. */
693        bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREREAD);
694        bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTREAD);
695        ifp = sc->ifp;
696        retired_buffer = false;
697        while (sc->tx_idx_tail != sc->tx_idx_head) {
698                desc = &sc->txdesc_ring[sc->tx_idx_tail];
699                if (desc->flags_len & FEC_TXDESC_READY)
700                        break;
701                retired_buffer = true;
702                bmap = &sc->txbuf_map[sc->tx_idx_tail];
703                bus_dmamap_sync(sc->txbuf_tag, bmap->map,
704                    BUS_DMASYNC_POSTWRITE);
705                bus_dmamap_unload(sc->txbuf_tag, bmap->map);
706                m_freem(bmap->mbuf);
707                bmap->mbuf = NULL;
708                ffec_setup_txdesc(sc, sc->tx_idx_tail, 0, 0);
709                sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail);
710        }
711
712        /*
713         * If we retired any buffers, there will be open tx slots available in
714         * the descriptor ring, go try to start some new output.
715         */
716        if (retired_buffer) {
717                ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
718                ffec_txstart_locked(sc);
719        }
720
721        /* If there are no buffers outstanding, muzzle the watchdog. */
722        if (sc->tx_idx_tail == sc->tx_idx_head) {
723                sc->tx_watchdog_count = 0;
724        }
725}
726
727inline static uint32_t
728ffec_setup_rxdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr)
729{
730        uint32_t nidx;
731
732        /*
733         * The hardware requires 32-bit physical addresses.  We set up the dma
734         * tag to indicate that, so the cast to uint32_t should never lose
735         * significant bits.
736         */
737        nidx = next_rxidx(sc, idx);
738        sc->rxdesc_ring[idx].buf_paddr = (uint32_t)paddr;
739        sc->rxdesc_ring[idx].flags_len = FEC_RXDESC_EMPTY |
740                ((nidx == 0) ? FEC_RXDESC_WRAP : 0);
741
742        return (nidx);
743}
744
745static int
746ffec_setup_rxbuf(struct ffec_softc *sc, int idx, struct mbuf * m)
747{
748        int error, nsegs;
749        struct bus_dma_segment seg;
750
751        /*
752         * We need to leave at least ETHER_ALIGN bytes free at the beginning of
753         * the buffer to allow the data to be re-aligned after receiving it (by
754         * copying it backwards ETHER_ALIGN bytes in the same buffer).  We also
755         * have to ensure that the beginning of the buffer is aligned to the
756         * hardware's requirements.
757         */
[ba0b059]758        m_adj(m, roundup(ETHER_ALIGN, sc->rxbuf_align));
[807b5bb]759
760        error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
761            m, &seg, &nsegs, 0);
762        if (error != 0) {
763                return (error);
764        }
765
766        bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
767            BUS_DMASYNC_PREREAD);
768
769        sc->rxbuf_map[idx].mbuf = m;
770        ffec_setup_rxdesc(sc, idx, seg.ds_addr);
771       
772        return (0);
773}
774
775static struct mbuf *
776ffec_alloc_mbufcl(struct ffec_softc *sc)
777{
778        struct mbuf *m;
779
780        m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
781        m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
[9c34735]782#ifdef __rtems__
783        rtems_cache_invalidate_multiple_data_lines(m->m_data, m->m_len);
784#endif /* __rtems__ */
[807b5bb]785
786        return (m);
787}
788
789static void
790ffec_rxfinish_onebuf(struct ffec_softc *sc, int len)
791{
792        struct mbuf *m, *newmbuf;
793        struct ffec_bufmap *bmap;
794        uint8_t *dst, *src;
795        int error;
796
797        /*
798         *  First try to get a new mbuf to plug into this slot in the rx ring.
799         *  If that fails, drop the current packet and recycle the current
800         *  mbuf, which is still mapped and loaded.
801         */
802        if ((newmbuf = ffec_alloc_mbufcl(sc)) == NULL) {
803                if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1);
804                ffec_setup_rxdesc(sc, sc->rx_idx,
805                    sc->rxdesc_ring[sc->rx_idx].buf_paddr);
806                return;
807        }
808
809        /*
810         *  Unfortunately, the protocol headers need to be aligned on a 32-bit
811         *  boundary for the upper layers.  The hardware requires receive
812         *  buffers to be 16-byte aligned.  The ethernet header is 14 bytes,
813         *  leaving the protocol header unaligned.  We used m_adj() after
814         *  allocating the buffer to leave empty space at the start of the
815         *  buffer, now we'll use the alignment agnostic bcopy() routine to
816         *  shuffle all the data backwards 2 bytes and adjust m_data.
817         *
818         *  XXX imx6 hardware is able to do this 2-byte alignment by setting the
819         *  SHIFT16 bit in the RACC register.  Older hardware doesn't have that
820         *  feature, but for them could we speed this up by copying just the
821         *  protocol headers into their own small mbuf then chaining the cluster
822         *  to it?  That way we'd only need to copy like 64 bytes or whatever
823         *  the biggest header is, instead of the whole 1530ish-byte frame.
824         */
825
826        FFEC_UNLOCK(sc);
827
828        bmap = &sc->rxbuf_map[sc->rx_idx];
829        len -= ETHER_CRC_LEN;
830        bus_dmamap_sync(sc->rxbuf_tag, bmap->map, BUS_DMASYNC_POSTREAD);
831        bus_dmamap_unload(sc->rxbuf_tag, bmap->map);
832        m = bmap->mbuf;
833        bmap->mbuf = NULL;
834        m->m_len = len;
835        m->m_pkthdr.len = len;
836        m->m_pkthdr.rcvif = sc->ifp;
837
838        src = mtod(m, uint8_t*);
839        dst = src - ETHER_ALIGN;
840        bcopy(src, dst, len);
841        m->m_data = dst;
842        sc->ifp->if_input(sc->ifp, m);
843
844        FFEC_LOCK(sc);
845
846        if ((error = ffec_setup_rxbuf(sc, sc->rx_idx, newmbuf)) != 0) {
847                device_printf(sc->dev, "ffec_setup_rxbuf error %d\n", error);
848                /* XXX Now what?  We've got a hole in the rx ring. */
849        }
850
851}
852
853static void
854ffec_rxfinish_locked(struct ffec_softc *sc)
855{
856        struct ffec_hwdesc *desc;
857        int len;
858        boolean_t produced_empty_buffer;
859
860        FFEC_ASSERT_LOCKED(sc);
861
862        /* XXX Can't set PRE|POST right now, but we need both. */
863        bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_PREREAD);
864        bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_POSTREAD);
865        produced_empty_buffer = false;
866        for (;;) {
867                desc = &sc->rxdesc_ring[sc->rx_idx];
868                if (desc->flags_len & FEC_RXDESC_EMPTY)
869                        break;
870                produced_empty_buffer = true;
871                len = (desc->flags_len & FEC_RXDESC_LEN_MASK);
872                if (len < 64) {
873                        /*
874                         * Just recycle the descriptor and continue.           .
875                         */
876                        ffec_setup_rxdesc(sc, sc->rx_idx,
877                            sc->rxdesc_ring[sc->rx_idx].buf_paddr);
878                } else if ((desc->flags_len & FEC_RXDESC_L) == 0) {
879                        /*
880                         * The entire frame is not in this buffer.  Impossible.
881                         * Recycle the descriptor and continue.
882                         *
883                         * XXX what's the right way to handle this? Probably we
884                         * should stop/init the hardware because this should
885                         * just really never happen when we have buffers bigger
886                         * than the maximum frame size.
887                         */
888                        device_printf(sc->dev,
889                            "fec_rxfinish: received frame without LAST bit set");
890                        ffec_setup_rxdesc(sc, sc->rx_idx,
891                            sc->rxdesc_ring[sc->rx_idx].buf_paddr);
892                } else if (desc->flags_len & FEC_RXDESC_ERROR_BITS) {
893                        /*
894                         *  Something went wrong with receiving the frame, we
895                         *  don't care what (the hardware has counted the error
896                         *  in the stats registers already), we just reuse the
897                         *  same mbuf, which is still dma-mapped, by resetting
898                         *  the rx descriptor.
899                         */
900                        ffec_setup_rxdesc(sc, sc->rx_idx,
901                            sc->rxdesc_ring[sc->rx_idx].buf_paddr);
902                } else {
903                        /*
904                         *  Normal case: a good frame all in one buffer.
905                         */
906                        ffec_rxfinish_onebuf(sc, len);
907                }
908                sc->rx_idx = next_rxidx(sc, sc->rx_idx);
909        }
910
911        if (produced_empty_buffer) {
912                bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_PREWRITE);
913                WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR);
914                bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_POSTWRITE);
915        }
916}
917
918static void
919ffec_get_hwaddr(struct ffec_softc *sc, uint8_t *hwaddr)
920{
921        uint32_t palr, paur, rnd;
922
923        /*
924         * Try to recover a MAC address from the running hardware. If there's
925         * something non-zero there, assume the bootloader did the right thing
926         * and just use it.
927         *
928         * Otherwise, set the address to a convenient locally assigned address,
929         * 'bsd' + random 24 low-order bits.  'b' is 0x62, which has the locally
930         * assigned bit set, and the broadcast/multicast bit clear.
931         */
932        palr = RD4(sc, FEC_PALR_REG);
933        paur = RD4(sc, FEC_PAUR_REG) & FEC_PAUR_PADDR2_MASK;
934        if ((palr | paur) != 0) {
935                hwaddr[0] = palr >> 24;
936                hwaddr[1] = palr >> 16;
937                hwaddr[2] = palr >>  8;
938                hwaddr[3] = palr >>  0;
939                hwaddr[4] = paur >> 24;
940                hwaddr[5] = paur >> 16;
941        } else {
942                rnd = arc4random() & 0x00ffffff;
943                hwaddr[0] = 'b';
944                hwaddr[1] = 's';
945                hwaddr[2] = 'd';
946                hwaddr[3] = rnd >> 16;
947                hwaddr[4] = rnd >>  8;
948                hwaddr[5] = rnd >>  0;
949        }
950
951        if (bootverbose) {
952                device_printf(sc->dev,
953                    "MAC address %02x:%02x:%02x:%02x:%02x:%02x:\n",
954                    hwaddr[0], hwaddr[1], hwaddr[2],
955                    hwaddr[3], hwaddr[4], hwaddr[5]);
956        }
957}
958
959static void
960ffec_setup_rxfilter(struct ffec_softc *sc)
961{
962        struct ifnet *ifp;
963        struct ifmultiaddr *ifma;
964        uint8_t *eaddr;
965        uint32_t crc;
966        uint64_t ghash, ihash;
967
968        FFEC_ASSERT_LOCKED(sc);
969
970        ifp = sc->ifp;
971
972        /*
973         * Set the multicast (group) filter hash.
974         */
975        if ((ifp->if_flags & IFF_ALLMULTI))
976                ghash = 0xffffffffffffffffLLU;
977        else {
978                ghash = 0;
979                if_maddr_rlock(ifp);
980                TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) {
981                        if (ifma->ifma_addr->sa_family != AF_LINK)
982                                continue;
983                        /* 6 bits from MSB in LE CRC32 are used for hash. */
984                        crc = ether_crc32_le(LLADDR((struct sockaddr_dl *)
985                            ifma->ifma_addr), ETHER_ADDR_LEN);
986                        ghash |= 1LLU << (((uint8_t *)&crc)[3] >> 2);
987                }
988                if_maddr_runlock(ifp);
989        }
990        WR4(sc, FEC_GAUR_REG, (uint32_t)(ghash >> 32));
991        WR4(sc, FEC_GALR_REG, (uint32_t)ghash);
992
993        /*
994         * Set the individual address filter hash.
995         *
996         * XXX Is 0 the right value when promiscuous is off?  This hw feature
997         * seems to support the concept of MAC address aliases, does such a
998         * thing even exist?
999         */
1000        if ((ifp->if_flags & IFF_PROMISC))
1001                ihash = 0xffffffffffffffffLLU;
1002        else {
1003                ihash = 0;
1004        }
1005        WR4(sc, FEC_IAUR_REG, (uint32_t)(ihash >> 32));
1006        WR4(sc, FEC_IALR_REG, (uint32_t)ihash);
1007
1008        /*
1009         * Set the primary address.
1010         */
1011        eaddr = IF_LLADDR(ifp);
1012        WR4(sc, FEC_PALR_REG, (eaddr[0] << 24) | (eaddr[1] << 16) |
1013            (eaddr[2] <<  8) | eaddr[3]);
1014        WR4(sc, FEC_PAUR_REG, (eaddr[4] << 24) | (eaddr[5] << 16));
1015}
1016
1017static void
1018ffec_stop_locked(struct ffec_softc *sc)
1019{
1020        struct ifnet *ifp;
1021        struct ffec_hwdesc *desc;
1022        struct ffec_bufmap *bmap;
1023        int idx;
1024
1025        FFEC_ASSERT_LOCKED(sc);
1026
1027        ifp = sc->ifp;
1028        ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1029        sc->tx_watchdog_count = 0;
1030        sc->stats_harvest_count = 0;
1031
1032        /*
1033         * Stop the hardware, mask all interrupts, and clear all current
1034         * interrupt status bits.
1035         */
1036        WR4(sc, FEC_ECR_REG, RD4(sc, FEC_ECR_REG) & ~FEC_ECR_ETHEREN);
1037        WR4(sc, FEC_IEM_REG, 0x00000000);
1038        WR4(sc, FEC_IER_REG, 0xffffffff);
1039
1040        /*
1041         * Stop the media-check callout.  Do not use callout_drain() because
1042         * we're holding a mutex the callout acquires, and if it's currently
1043         * waiting to acquire it, we'd deadlock.  If it is waiting now, the
1044         * ffec_tick() routine will return without doing anything when it sees
1045         * that IFF_DRV_RUNNING is not set, so avoiding callout_drain() is safe.
1046         */
1047        callout_stop(&sc->ffec_callout);
1048
1049        /*
1050         * Discard all untransmitted buffers.  Each buffer is simply freed;
1051         * it's as if the bits were transmitted and then lost on the wire.
1052         *
1053         * XXX Is this right?  Or should we use IFQ_DRV_PREPEND() to put them
1054         * back on the queue for when we get restarted later?
1055         */
1056        idx = sc->tx_idx_tail;
1057        while (idx != sc->tx_idx_head) {
1058                desc = &sc->txdesc_ring[idx];
1059                bmap = &sc->txbuf_map[idx];
1060                if (desc->buf_paddr != 0) {
1061                        bus_dmamap_unload(sc->txbuf_tag, bmap->map);
1062                        m_freem(bmap->mbuf);
1063                        bmap->mbuf = NULL;
1064                        ffec_setup_txdesc(sc, idx, 0, 0);
1065                }
1066                idx = next_txidx(sc, idx);
1067        }
1068
1069        /*
1070         * Discard all unprocessed receive buffers.  This amounts to just
1071         * pretending that nothing ever got received into them.  We reuse the
1072         * mbuf already mapped for each desc, simply turning the EMPTY flags
1073         * back on so they'll get reused when we start up again.
1074         */
1075        for (idx = 0; idx < RX_DESC_COUNT; ++idx) {
1076                desc = &sc->rxdesc_ring[idx];
1077                ffec_setup_rxdesc(sc, idx, desc->buf_paddr);
1078        }
1079}
1080
1081static void
1082ffec_init_locked(struct ffec_softc *sc)
1083{
1084        struct ifnet *ifp = sc->ifp;
1085        uint32_t maxbuf, maxfl, regval;
1086
1087        FFEC_ASSERT_LOCKED(sc);
1088
1089        /*
1090         * The hardware has a limit of 0x7ff as the max frame length (see
1091         * comments for MRBR below), and we use mbuf clusters as receive
1092         * buffers, and we currently are designed to receive an entire frame
1093         * into a single buffer.
1094         *
1095         * We start with a MCLBYTES-sized cluster, but we have to offset into
1096         * the buffer by ETHER_ALIGN to make room for post-receive re-alignment,
1097         * and then that value has to be rounded up to the hardware's DMA
1098         * alignment requirements, so all in all our buffer is that much smaller
1099         * than MCLBYTES.
1100         *
1101         * The resulting value is used as the frame truncation length and the
1102         * max buffer receive buffer size for now.  It'll become more complex
1103         * when we support jumbo frames and receiving fragments of them into
1104         * separate buffers.
1105         */
[ba0b059]1106        maxbuf = MCLBYTES - roundup(ETHER_ALIGN, sc->rxbuf_align);
[807b5bb]1107        maxfl = min(maxbuf, 0x7ff);
1108
1109        if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1110                return;
1111
1112        /* Mask all interrupts and clear all current interrupt status bits. */
1113        WR4(sc, FEC_IEM_REG, 0x00000000);
1114        WR4(sc, FEC_IER_REG, 0xffffffff);
1115
1116        /*
1117         * Go set up palr/puar, galr/gaur, ialr/iaur.
1118         */
1119        ffec_setup_rxfilter(sc);
1120
1121        /*
1122         * TFWR - Transmit FIFO watermark register.
1123         *
1124         * Set the transmit fifo watermark register to "store and forward" mode
1125         * and also set a threshold of 128 bytes in the fifo before transmission
1126         * of a frame begins (to avoid dma underruns).  Recent FEC hardware
1127         * supports STRFWD and when that bit is set, the watermark level in the
1128         * low bits is ignored.  Older hardware doesn't have STRFWD, but writing
1129         * to that bit is innocuous, and the TWFR bits get used instead.
1130         */
1131        WR4(sc, FEC_TFWR_REG, FEC_TFWR_STRFWD | FEC_TFWR_TWFR_128BYTE);
1132
1133        /* RCR - Receive control register.
1134         *
1135         * Set max frame length + clean out anything left from u-boot.
1136         */
1137        WR4(sc, FEC_RCR_REG, (maxfl << FEC_RCR_MAX_FL_SHIFT));
1138
1139        /*
1140         * TCR - Transmit control register.
1141         *
1142         * Clean out anything left from u-boot.  Any necessary values are set in
1143         * ffec_miibus_statchg() based on the media type.
1144         */
1145        WR4(sc, FEC_TCR_REG, 0);
1146       
1147        /*
1148         * OPD - Opcode/pause duration.
1149         *
1150         * XXX These magic numbers come from u-boot.
1151         */
1152        WR4(sc, FEC_OPD_REG, 0x00010020);
1153
1154        /*
1155         * FRSR - Fifo receive start register.
1156         *
1157         * This register does not exist on imx6, it is present on earlier
1158         * hardware. The u-boot code sets this to a non-default value that's 32
1159         * bytes larger than the default, with no clue as to why.  The default
1160         * value should work fine, so there's no code to init it here.
1161         */
1162
1163        /*
1164         *  MRBR - Max RX buffer size.
1165         *
1166         *  Note: For hardware prior to imx6 this value cannot exceed 0x07ff,
1167         *  but the datasheet says no such thing for imx6.  On the imx6, setting
1168         *  this to 2K without setting EN1588 resulted in a crazy runaway
1169         *  receive loop in the hardware, where every rx descriptor in the ring
1170         *  had its EMPTY flag cleared, no completion or error flags set, and a
1171         *  length of zero.  I think maybe you can only exceed it when EN1588 is
1172         *  set, like maybe that's what enables jumbo frames, because in general
1173         *  the EN1588 flag seems to be the "enable new stuff" vs. "be legacy-
1174         *  compatible" flag.
1175         */
1176        WR4(sc, FEC_MRBR_REG, maxfl << FEC_MRBR_R_BUF_SIZE_SHIFT);
1177
1178        /*
1179         * FTRL - Frame truncation length.
1180         *
1181         * Must be greater than or equal to the value set in FEC_RCR_MAXFL.
1182         */
1183        WR4(sc, FEC_FTRL_REG, maxfl);
1184
1185        /*
1186         * RDSR / TDSR descriptor ring pointers.
1187         *
1188         * When we turn on ECR_ETHEREN at the end, the hardware zeroes its
1189         * internal current descriptor index values for both rings, so we zero
1190         * our index values as well.
1191         */
1192        sc->rx_idx = 0;
1193        sc->tx_idx_head = sc->tx_idx_tail = 0;
1194        sc->txcount = 0;
1195        WR4(sc, FEC_RDSR_REG, sc->rxdesc_ring_paddr);
1196        WR4(sc, FEC_TDSR_REG, sc->txdesc_ring_paddr);
1197
1198        /*
1199         * EIM - interrupt mask register.
1200         *
1201         * We always enable the same set of interrupts while running; unlike
1202         * some drivers there's no need to change the mask on the fly depending
1203         * on what operations are in progress.
1204         */
1205        WR4(sc, FEC_IEM_REG, FEC_IER_TXF | FEC_IER_RXF | FEC_IER_EBERR);
1206
1207        /*
1208         * MIBC - MIB control (hardware stats).
1209         */
1210        regval = RD4(sc, FEC_MIBC_REG);
1211        WR4(sc, FEC_MIBC_REG, regval | FEC_MIBC_DIS);
1212        ffec_clear_stats(sc);
1213        WR4(sc, FEC_MIBC_REG, regval & ~FEC_MIBC_DIS);
1214
1215        /*
1216         * ECR - Ethernet control register.
1217         *
1218         * This must happen after all the other config registers are set.  If
1219         * we're running on little-endian hardware, also set the flag for byte-
1220         * swapping descriptor ring entries.  This flag doesn't exist on older
1221         * hardware, but it can be safely set -- the bit position it occupies
1222         * was unused.
1223         */
1224        regval = RD4(sc, FEC_ECR_REG);
1225#if _BYTE_ORDER == _LITTLE_ENDIAN
1226        regval |= FEC_ECR_DBSWP;
1227#endif
1228        regval |= FEC_ECR_ETHEREN;
1229        WR4(sc, FEC_ECR_REG, regval);
1230
1231        ifp->if_drv_flags |= IFF_DRV_RUNNING;
1232
1233       /*
1234        * Call mii_mediachg() which will call back into ffec_miibus_statchg() to
1235        * set up the remaining config registers based on the current media.
1236        */
1237        mii_mediachg(sc->mii_softc);
1238        callout_reset(&sc->ffec_callout, hz, ffec_tick, sc);
1239
1240        /*
1241         * Tell the hardware that receive buffers are available.  They were made
1242         * available in ffec_attach() or ffec_stop().
1243         */
1244        WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR);
1245}
1246
1247static void
1248ffec_init(void *if_softc)
1249{
1250        struct ffec_softc *sc = if_softc;
1251
1252        FFEC_LOCK(sc);
1253        ffec_init_locked(sc);
1254        FFEC_UNLOCK(sc);
1255}
1256
1257static void
1258ffec_intr(void *arg)
1259{
1260        struct ffec_softc *sc;
1261        uint32_t ier;
1262
1263        sc = arg;
1264
1265        FFEC_LOCK(sc);
1266
1267        ier = RD4(sc, FEC_IER_REG);
1268
1269        if (ier & FEC_IER_TXF) {
1270                WR4(sc, FEC_IER_REG, FEC_IER_TXF);
1271                ffec_txfinish_locked(sc);
1272        }
1273
1274        if (ier & FEC_IER_RXF) {
1275                WR4(sc, FEC_IER_REG, FEC_IER_RXF);
1276                ffec_rxfinish_locked(sc);
1277        }
1278
1279        /*
1280         * We actually don't care about most errors, because the hardware copes
1281         * with them just fine, discarding the incoming bad frame, or forcing a
1282         * bad CRC onto an outgoing bad frame, and counting the errors in the
1283         * stats registers.  The one that really matters is EBERR (DMA bus
1284         * error) because the hardware automatically clears ECR[ETHEREN] and we
1285         * have to restart it here.  It should never happen.
1286         */
1287        if (ier & FEC_IER_EBERR) {
1288                WR4(sc, FEC_IER_REG, FEC_IER_EBERR);
1289                device_printf(sc->dev,
1290                    "Ethernet DMA error, restarting controller.\n");
1291                ffec_stop_locked(sc);
1292                ffec_init_locked(sc);
1293        }
1294
1295        FFEC_UNLOCK(sc);
1296
1297}
1298
1299static int
1300ffec_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1301{
1302        struct ffec_softc *sc;
1303        struct mii_data *mii;
1304        struct ifreq *ifr;
1305        int mask, error;
1306
1307        sc = ifp->if_softc;
1308        ifr = (struct ifreq *)data;
1309
1310        error = 0;
1311        switch (cmd) {
1312        case SIOCSIFFLAGS:
1313                FFEC_LOCK(sc);
1314                if (ifp->if_flags & IFF_UP) {
1315                        if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1316                                if ((ifp->if_flags ^ sc->if_flags) &
1317                                    (IFF_PROMISC | IFF_ALLMULTI))
1318                                        ffec_setup_rxfilter(sc);
1319                        } else {
1320                                if (!sc->is_detaching)
1321                                        ffec_init_locked(sc);
1322                        }
1323                } else {
1324                        if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1325                                ffec_stop_locked(sc);
1326                }
1327                sc->if_flags = ifp->if_flags;
1328                FFEC_UNLOCK(sc);
1329                break;
1330
1331        case SIOCADDMULTI:
1332        case SIOCDELMULTI:
1333                if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1334                        FFEC_LOCK(sc);
1335                        ffec_setup_rxfilter(sc);
1336                        FFEC_UNLOCK(sc);
1337                }
1338                break;
1339
1340        case SIOCSIFMEDIA:
1341        case SIOCGIFMEDIA:
1342                mii = sc->mii_softc;
1343                error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1344                break;
1345
1346        case SIOCSIFCAP:
1347                mask = ifp->if_capenable ^ ifr->ifr_reqcap;
1348                if (mask & IFCAP_VLAN_MTU) {
1349                        /* No work to do except acknowledge the change took. */
1350                        ifp->if_capenable ^= IFCAP_VLAN_MTU;
1351                }
1352                break;
1353
1354        default:
1355                error = ether_ioctl(ifp, cmd, data);
1356                break;
1357        }       
1358
1359        return (error);
1360}
1361
1362static int
1363ffec_detach(device_t dev)
1364{
1365        struct ffec_softc *sc;
1366        bus_dmamap_t map;
1367        int idx;
1368
1369        /*
1370         * NB: This function can be called internally to unwind a failure to
1371         * attach. Make sure a resource got allocated/created before destroying.
1372         */
1373
1374        sc = device_get_softc(dev);
1375
1376        if (sc->is_attached) {
1377                FFEC_LOCK(sc);
1378                sc->is_detaching = true;
1379                ffec_stop_locked(sc);
1380                FFEC_UNLOCK(sc);
1381                callout_drain(&sc->ffec_callout);
1382                ether_ifdetach(sc->ifp);
1383        }
1384
1385        /* XXX no miibus detach? */
1386
1387        /* Clean up RX DMA resources and free mbufs. */
1388        for (idx = 0; idx < RX_DESC_COUNT; ++idx) {
1389                if ((map = sc->rxbuf_map[idx].map) != NULL) {
1390                        bus_dmamap_unload(sc->rxbuf_tag, map);
1391                        bus_dmamap_destroy(sc->rxbuf_tag, map);
1392                        m_freem(sc->rxbuf_map[idx].mbuf);
1393                }
1394        }
1395        if (sc->rxbuf_tag != NULL)
1396                bus_dma_tag_destroy(sc->rxbuf_tag);
1397        if (sc->rxdesc_map != NULL) {
1398                bus_dmamap_unload(sc->rxdesc_tag, sc->rxdesc_map);
1399                bus_dmamap_destroy(sc->rxdesc_tag, sc->rxdesc_map);
1400        }
1401        if (sc->rxdesc_tag != NULL)
1402        bus_dma_tag_destroy(sc->rxdesc_tag);
1403
1404        /* Clean up TX DMA resources. */
1405        for (idx = 0; idx < TX_DESC_COUNT; ++idx) {
1406                if ((map = sc->txbuf_map[idx].map) != NULL) {
1407                        /* TX maps are already unloaded. */
1408                        bus_dmamap_destroy(sc->txbuf_tag, map);
1409                }
1410        }
1411        if (sc->txbuf_tag != NULL)
1412                bus_dma_tag_destroy(sc->txbuf_tag);
1413        if (sc->txdesc_map != NULL) {
1414                bus_dmamap_unload(sc->txdesc_tag, sc->txdesc_map);
1415                bus_dmamap_destroy(sc->txdesc_tag, sc->txdesc_map);
1416        }
1417        if (sc->txdesc_tag != NULL)
1418        bus_dma_tag_destroy(sc->txdesc_tag);
1419
1420        /* Release bus resources. */
1421        if (sc->intr_cookie)
1422                bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie);
1423
1424        if (sc->irq_res != NULL)
1425                bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
1426
1427        if (sc->mem_res != NULL)
1428                bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
1429
1430        FFEC_LOCK_DESTROY(sc);
1431        return (0);
1432}
1433
1434static int
1435ffec_attach(device_t dev)
1436{
1437        struct ffec_softc *sc;
1438        struct ifnet *ifp = NULL;
1439        struct mbuf *m;
1440        phandle_t ofw_node;
1441        int error, rid;
1442        uint8_t eaddr[ETHER_ADDR_LEN];
1443        char phy_conn_name[32];
1444        uint32_t idx, mscr;
1445
1446        sc = device_get_softc(dev);
1447        sc->dev = dev;
1448
1449        FFEC_LOCK_INIT(sc);
1450
1451        /*
1452         * There are differences in the implementation and features of the FEC
1453         * hardware on different SoCs, so figure out what type we are.
1454         */
1455        sc->fectype = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
1456
[ba0b059]1457        if (sc->fectype & FECFLAG_AVB) {
1458                sc->rxbuf_align = 64;
1459                sc->txbuf_align = 1;
1460        } else {
1461                sc->rxbuf_align = 16;
1462                sc->txbuf_align = 16;
1463        }
1464
[807b5bb]1465        /*
1466         * We have to be told what kind of electrical connection exists between
1467         * the MAC and PHY or we can't operate correctly.
1468         */
1469        if ((ofw_node = ofw_bus_get_node(dev)) == -1) {
1470                device_printf(dev, "Impossible: Can't find ofw bus node\n");
1471                error = ENXIO;
1472                goto out;
1473        }
1474        if (OF_searchprop(ofw_node, "phy-mode",
1475            phy_conn_name, sizeof(phy_conn_name)) != -1) {
1476                if (strcasecmp(phy_conn_name, "mii") == 0)
1477                        sc->phy_conn_type = PHY_CONN_MII;
1478                else if (strcasecmp(phy_conn_name, "rmii") == 0)
1479                        sc->phy_conn_type = PHY_CONN_RMII;
[91a7527]1480#ifndef __rtems__
[807b5bb]1481                else if (strcasecmp(phy_conn_name, "rgmii") == 0)
[91a7527]1482#else /* __rtems__ */
1483                else if (strncasecmp(phy_conn_name, "rgmii", 5) == 0)
1484#endif /* __rtems__ */
[807b5bb]1485                        sc->phy_conn_type = PHY_CONN_RGMII;
1486        }
1487        if (sc->phy_conn_type == PHY_CONN_UNKNOWN) {
1488                device_printf(sc->dev, "No valid 'phy-mode' "
1489                    "property found in FDT data for device.\n");
[95b102f]1490#ifndef __rtems__
[807b5bb]1491                error = ENOATTR;
[95b102f]1492#else /* __rtems__ */
1493                error = ENXIO;
1494#endif /* __rtems__ */
[807b5bb]1495                goto out;
1496        }
1497
1498        callout_init_mtx(&sc->ffec_callout, &sc->mtx, 0);
1499
1500        /* Allocate bus resources for accessing the hardware. */
1501        rid = 0;
1502        sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1503            RF_ACTIVE);
1504        if (sc->mem_res == NULL) {
1505                device_printf(dev, "could not allocate memory resources.\n");
1506                error = ENOMEM;
1507                goto out;
1508        }
1509        rid = 0;
1510        sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1511            RF_ACTIVE);
1512        if (sc->irq_res == NULL) {
1513                device_printf(dev, "could not allocate interrupt resources.\n");
1514                error = ENOMEM;
1515                goto out;
1516        }
1517
1518        /*
1519         * Set up TX descriptor ring, descriptors, and dma maps.
1520         */
1521        error = bus_dma_tag_create(
1522            bus_get_dma_tag(dev),       /* Parent tag. */
1523            FEC_DESC_RING_ALIGN, 0,     /* alignment, boundary */
1524            BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
1525            BUS_SPACE_MAXADDR,          /* highaddr */
1526            NULL, NULL,                 /* filter, filterarg */
1527            TX_DESC_SIZE, 1,            /* maxsize, nsegments */
1528            TX_DESC_SIZE,               /* maxsegsize */
1529            0,                          /* flags */
1530            NULL, NULL,                 /* lockfunc, lockarg */
1531            &sc->txdesc_tag);
1532        if (error != 0) {
1533                device_printf(sc->dev,
1534                    "could not create TX ring DMA tag.\n");
1535                goto out;
1536        }
1537
1538        error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring,
1539            BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->txdesc_map);
1540        if (error != 0) {
1541                device_printf(sc->dev,
1542                    "could not allocate TX descriptor ring.\n");
1543                goto out;
1544        }
1545
1546        error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, sc->txdesc_ring,
1547            TX_DESC_SIZE, ffec_get1paddr, &sc->txdesc_ring_paddr, 0);
1548        if (error != 0) {
1549                device_printf(sc->dev,
1550                    "could not load TX descriptor ring map.\n");
1551                goto out;
1552        }
1553
1554        error = bus_dma_tag_create(
1555            bus_get_dma_tag(dev),       /* Parent tag. */
[ba0b059]1556            sc->txbuf_align, 0,         /* alignment, boundary */
[807b5bb]1557            BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
1558            BUS_SPACE_MAXADDR,          /* highaddr */
1559            NULL, NULL,                 /* filter, filterarg */
1560            MCLBYTES, 1,                /* maxsize, nsegments */
1561            MCLBYTES,                   /* maxsegsize */
1562            0,                          /* flags */
1563            NULL, NULL,                 /* lockfunc, lockarg */
1564            &sc->txbuf_tag);
1565        if (error != 0) {
1566                device_printf(sc->dev,
1567                    "could not create TX ring DMA tag.\n");
1568                goto out;
1569        }
1570
1571        for (idx = 0; idx < TX_DESC_COUNT; ++idx) {
1572                error = bus_dmamap_create(sc->txbuf_tag, 0,
1573                    &sc->txbuf_map[idx].map);
1574                if (error != 0) {
1575                        device_printf(sc->dev,
1576                            "could not create TX buffer DMA map.\n");
1577                        goto out;
1578                }
1579                ffec_setup_txdesc(sc, idx, 0, 0);
1580        }
1581
1582        /*
1583         * Set up RX descriptor ring, descriptors, dma maps, and mbufs.
1584         */
1585        error = bus_dma_tag_create(
1586            bus_get_dma_tag(dev),       /* Parent tag. */
1587            FEC_DESC_RING_ALIGN, 0,     /* alignment, boundary */
1588            BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
1589            BUS_SPACE_MAXADDR,          /* highaddr */
1590            NULL, NULL,                 /* filter, filterarg */
1591            RX_DESC_SIZE, 1,            /* maxsize, nsegments */
1592            RX_DESC_SIZE,               /* maxsegsize */
1593            0,                          /* flags */
1594            NULL, NULL,                 /* lockfunc, lockarg */
1595            &sc->rxdesc_tag);
1596        if (error != 0) {
1597                device_printf(sc->dev,
1598                    "could not create RX ring DMA tag.\n");
1599                goto out;
1600        }
1601
1602        error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring,
1603            BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rxdesc_map);
1604        if (error != 0) {
1605                device_printf(sc->dev,
1606                    "could not allocate RX descriptor ring.\n");
1607                goto out;
1608        }
1609
1610        error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, sc->rxdesc_ring,
1611            RX_DESC_SIZE, ffec_get1paddr, &sc->rxdesc_ring_paddr, 0);
1612        if (error != 0) {
1613                device_printf(sc->dev,
1614                    "could not load RX descriptor ring map.\n");
1615                goto out;
1616        }
1617
1618        error = bus_dma_tag_create(
1619            bus_get_dma_tag(dev),       /* Parent tag. */
1620            1, 0,                       /* alignment, boundary */
1621            BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
1622            BUS_SPACE_MAXADDR,          /* highaddr */
1623            NULL, NULL,                 /* filter, filterarg */
1624            MCLBYTES, 1,                /* maxsize, nsegments */
1625            MCLBYTES,                   /* maxsegsize */
1626            0,                          /* flags */
1627            NULL, NULL,                 /* lockfunc, lockarg */
1628            &sc->rxbuf_tag);
1629        if (error != 0) {
1630                device_printf(sc->dev,
1631                    "could not create RX buf DMA tag.\n");
1632                goto out;
1633        }
1634
1635        for (idx = 0; idx < RX_DESC_COUNT; ++idx) {
1636                error = bus_dmamap_create(sc->rxbuf_tag, 0,
1637                    &sc->rxbuf_map[idx].map);
1638                if (error != 0) {
1639                        device_printf(sc->dev,
1640                            "could not create RX buffer DMA map.\n");
1641                        goto out;
1642                }
1643                if ((m = ffec_alloc_mbufcl(sc)) == NULL) {
1644                        device_printf(dev, "Could not alloc mbuf\n");
1645                        error = ENOMEM;
1646                        goto out;
1647                }
1648                if ((error = ffec_setup_rxbuf(sc, idx, m)) != 0) {
1649                        device_printf(sc->dev,
1650                            "could not create new RX buffer.\n");
1651                        goto out;
1652                }
1653        }
1654
1655        /* Try to get the MAC address from the hardware before resetting it. */
1656        ffec_get_hwaddr(sc, eaddr);
1657
1658        /* Reset the hardware.  Disables all interrupts. */
[e2e4bf4]1659        if (sc->fectype & FECFLAG_AVB)
1660                /*
1661                 * Avoid AXI bus issues due to a MAC reset, see Linux for more
1662                 * details.
1663                 */
1664                WR4(sc, FEC_ECR_REG, 0);
1665        else
1666                WR4(sc, FEC_ECR_REG, FEC_ECR_RESET);
[807b5bb]1667
1668        /* Setup interrupt handler. */
1669        error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE,
1670            NULL, ffec_intr, sc, &sc->intr_cookie);
1671        if (error != 0) {
1672                device_printf(dev, "could not setup interrupt handler.\n");
1673                goto out;
1674        }
1675
1676        /*
1677         * Set up the PHY control register.
1678         *
1679         * Speed formula for ENET is md_clock = mac_clock / ((N + 1) * 2).
1680         * Speed formula for FEC is  md_clock = mac_clock / (N * 2)
1681         *
1682         * XXX - Revisit this...
1683         *
1684         * For a Wandboard imx6 (ENET) I was originally using 4, but the uboot
1685         * code uses 10.  Both values seem to work, but I suspect many modern
1686         * PHY parts can do mdio at speeds far above the standard 2.5 MHz.
1687         *
1688         * Different imx manuals use confusingly different terminology (things
1689         * like "system clock" and "internal module clock") with examples that
1690         * use frequencies that have nothing to do with ethernet, giving the
1691         * vague impression that maybe the clock in question is the periphclock
1692         * or something.  In fact, on an imx53 development board (FEC),
1693         * measuring the mdio clock at the pin on the PHY and playing with
1694         * various divisors showed that the root speed was 66 MHz (clk_ipg_root
1695         * aka periphclock) and 13 was the right divisor.
1696         *
1697         * All in all, it seems likely that 13 is a safe divisor for now,
1698         * because if we really do need to base it on the peripheral clock
1699         * speed, then we need a platform-independant get-clock-freq API.
1700         */
1701        mscr = 13 << FEC_MSCR_MII_SPEED_SHIFT;
1702        if (OF_hasprop(ofw_node, "phy-disable-preamble")) {
1703                mscr |= FEC_MSCR_DIS_PRE;
1704                if (bootverbose)
1705                        device_printf(dev, "PHY preamble disabled\n");
1706        }
1707        WR4(sc, FEC_MSCR_REG, mscr);
1708
1709        /* Set up the ethernet interface. */
1710        sc->ifp = ifp = if_alloc(IFT_ETHER);
1711
1712        ifp->if_softc = sc;
1713        if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1714        ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1715        ifp->if_capabilities = IFCAP_VLAN_MTU;
1716        ifp->if_capenable = ifp->if_capabilities;
1717        ifp->if_start = ffec_txstart;
1718        ifp->if_ioctl = ffec_ioctl;
1719        ifp->if_init = ffec_init;
1720        IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1);
1721        ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1;
1722        IFQ_SET_READY(&ifp->if_snd);
1723        ifp->if_hdrlen = sizeof(struct ether_vlan_header);
1724
1725#if 0 /* XXX The hardware keeps stats we could use for these. */
1726        ifp->if_linkmib = &sc->mibdata;
1727        ifp->if_linkmiblen = sizeof(sc->mibdata);
1728#endif
1729
1730        /* Set up the miigasket hardware (if any). */
1731        ffec_miigasket_setup(sc);
1732
1733        /* Attach the mii driver. */
1734        error = mii_attach(dev, &sc->miibus, ifp, ffec_media_change,
1735            ffec_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY,
1736            (sc->fectype & FECTYPE_MVF) ? MIIF_FORCEANEG : 0);
1737        if (error != 0) {
1738                device_printf(dev, "PHY attach failed\n");
1739                goto out;
1740        }
1741        sc->mii_softc = device_get_softc(sc->miibus);
1742
1743        /* All ready to run, attach the ethernet interface. */
1744        ether_ifattach(ifp, eaddr);
1745        sc->is_attached = true;
1746
1747        error = 0;
1748out:
1749
1750        if (error != 0)
1751                ffec_detach(dev);
1752
1753        return (error);
1754}
1755
1756static int
1757ffec_probe(device_t dev)
1758{
1759        uintptr_t fectype;
1760
1761        if (!ofw_bus_status_okay(dev))
1762                return (ENXIO);
1763
1764        fectype = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
1765        if (fectype == FECTYPE_NONE)
1766                return (ENXIO);
1767
1768        device_set_desc(dev, (fectype & FECFLAG_GBE) ?
1769            "Freescale Gigabit Ethernet Controller" :
1770            "Freescale Fast Ethernet Controller");
1771
1772        return (BUS_PROBE_DEFAULT);
1773}
1774
1775
1776static device_method_t ffec_methods[] = {
1777        /* Device interface. */
1778        DEVMETHOD(device_probe,         ffec_probe),
1779        DEVMETHOD(device_attach,        ffec_attach),
1780        DEVMETHOD(device_detach,        ffec_detach),
1781
1782/*
1783        DEVMETHOD(device_shutdown,      ffec_shutdown),
1784        DEVMETHOD(device_suspend,       ffec_suspend),
1785        DEVMETHOD(device_resume,        ffec_resume),
1786*/
1787
1788        /* MII interface. */
1789        DEVMETHOD(miibus_readreg,       ffec_miibus_readreg),
1790        DEVMETHOD(miibus_writereg,      ffec_miibus_writereg),
1791        DEVMETHOD(miibus_statchg,       ffec_miibus_statchg),
1792
1793        DEVMETHOD_END
1794};
1795
1796static driver_t ffec_driver = {
1797        "ffec",
1798        ffec_methods,
1799        sizeof(struct ffec_softc)
1800};
1801
1802static devclass_t ffec_devclass;
1803
1804DRIVER_MODULE(ffec, simplebus, ffec_driver, ffec_devclass, 0, 0);
1805DRIVER_MODULE(miibus, ffec, miibus_driver, miibus_devclass, 0, 0);
1806
1807MODULE_DEPEND(ffec, ether, 1, 1, 1);
1808MODULE_DEPEND(ffec, miibus, 1, 1, 1);
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