| 1 | /*- |
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| 2 | * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> |
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| 3 | * All rights reserved. |
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| 4 | * |
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| 5 | * This software was developed by SRI International and the University of |
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| 6 | * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) |
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| 7 | * ("CTSRD"), as part of the DARPA CRASH research programme. |
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| 8 | * |
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| 9 | * Redistribution and use in source and binary forms, with or without |
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| 10 | * modification, are permitted provided that the following conditions |
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| 11 | * are met: |
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| 12 | * 1. Redistributions of source code must retain the above copyright |
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| 13 | * notice, this list of conditions and the following disclaimer. |
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| 14 | * 2. Redistributions in binary form must reproduce the above copyright |
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| 15 | * notice, this list of conditions and the following disclaimer in the |
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| 16 | * documentation and/or other materials provided with the distribution. |
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| 17 | * |
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| 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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| 19 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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| 22 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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| 23 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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| 24 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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| 25 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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| 26 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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| 27 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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| 28 | * SUCH DAMAGE. |
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| 29 | * |
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| 30 | * $FreeBSD$ |
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| 31 | */ |
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| 32 | |
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| 33 | /* |
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| 34 | * Register names were taken almost as is from the documentation. |
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| 35 | */ |
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| 36 | |
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| 37 | #ifndef __IF_DWC_H__ |
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| 38 | #define __IF_DWC_H__ |
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| 39 | |
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| 40 | #define MAC_CONFIGURATION 0x0 |
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| 41 | #define CONF_JD (1 << 22) /* jabber timer disable */ |
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| 42 | #define CONF_BE (1 << 21) /* Frame Burst Enable */ |
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| 43 | #define CONF_PS (1 << 15) /* GMII/MII */ |
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| 44 | #define CONF_FES (1 << 14) /* MII speed select */ |
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| 45 | #define CONF_DM (1 << 11) /* Full Duplex Enable */ |
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| 46 | #define CONF_IPC (1 << 10) /* Checksum Enable */ |
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| 47 | #define CONF_ACS (1 << 7) |
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| 48 | #define CONF_TE (1 << 3) |
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| 49 | #define CONF_RE (1 << 2) |
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| 50 | #define MAC_FRAME_FILTER 0x4 |
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| 51 | #define FRAME_FILTER_RA (1U << 31) /* Receive All */ |
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| 52 | #define FRAME_FILTER_HPF (1 << 10) /* Hash or Perfect Filter */ |
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| 53 | #define FRAME_FILTER_PM (1 << 4) /* Pass multicast */ |
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| 54 | #define FRAME_FILTER_HMC (1 << 2) |
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| 55 | #define FRAME_FILTER_HUC (1 << 1) |
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| 56 | #define FRAME_FILTER_PR (1 << 0) /* All Incoming Frames */ |
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| 57 | #define GMAC_MAC_HTHIGH 0x08 |
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| 58 | #define GMAC_MAC_HTLOW 0x0c |
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| 59 | #define GMII_ADDRESS 0x10 |
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| 60 | #define GMII_ADDRESS_PA_MASK 0x1f /* Phy device */ |
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| 61 | #define GMII_ADDRESS_PA_SHIFT 11 |
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| 62 | #define GMII_ADDRESS_GR_MASK 0x1f /* Phy register */ |
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| 63 | #define GMII_ADDRESS_GR_SHIFT 6 |
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| 64 | #define GMII_ADDRESS_CR_MASK 0xf |
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| 65 | #define GMII_ADDRESS_CR_SHIFT 2 /* Clock */ |
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| 66 | #define GMII_ADDRESS_GW (1 << 1) /* Write operation */ |
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| 67 | #define GMII_ADDRESS_GB (1 << 0) /* Busy */ |
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| 68 | #define GMII_DATA 0x14 |
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| 69 | #define FLOW_CONTROL 0x18 |
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| 70 | #define GMAC_VLAN_TAG 0x1C |
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| 71 | #define VERSION 0x20 |
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| 72 | #define DEBUG 0x24 |
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| 73 | #define LPI_CONTROL_STATUS 0x30 |
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| 74 | #define LPI_TIMERS_CONTROL 0x34 |
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| 75 | #define INTERRUPT_STATUS 0x38 |
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| 76 | #define INTERRUPT_MASK 0x3C |
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| 77 | #define MAC_ADDRESS_HIGH(n) ((n > 15 ? 0x800 : 0x40) + 0x8 * n) |
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| 78 | #define MAC_ADDRESS_LOW(n) ((n > 15 ? 0x804 : 0x44) + 0x8 * n) |
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| 79 | |
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| 80 | #define SGMII_RGMII_SMII_CTRL_STATUS 0xD8 |
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| 81 | #define MMC_CONTROL 0x100 |
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| 82 | #define MMC_CONTROL_CNTRST (1 << 0) |
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| 83 | #define MMC_RECEIVE_INTERRUPT 0x104 |
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| 84 | #define MMC_TRANSMIT_INTERRUPT 0x108 |
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| 85 | #define MMC_RECEIVE_INTERRUPT_MASK 0x10C |
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| 86 | #define MMC_TRANSMIT_INTERRUPT_MASK 0x110 |
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| 87 | #define TXOCTETCOUNT_GB 0x114 |
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| 88 | #define TXFRAMECOUNT_GB 0x118 |
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| 89 | #define TXBROADCASTFRAMES_G 0x11C |
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| 90 | #define TXMULTICASTFRAMES_G 0x120 |
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| 91 | #define TX64OCTETS_GB 0x124 |
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| 92 | #define TX65TO127OCTETS_GB 0x128 |
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| 93 | #define TX128TO255OCTETS_GB 0x12C |
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| 94 | #define TX256TO511OCTETS_GB 0x130 |
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| 95 | #define TX512TO1023OCTETS_GB 0x134 |
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| 96 | #define TX1024TOMAXOCTETS_GB 0x138 |
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| 97 | #define TXUNICASTFRAMES_GB 0x13C |
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| 98 | #define TXMULTICASTFRAMES_GB 0x140 |
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| 99 | #define TXBROADCASTFRAMES_GB 0x144 |
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| 100 | #define TXUNDERFLOWERROR 0x148 |
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| 101 | #define TXSINGLECOL_G 0x14C |
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| 102 | #define TXMULTICOL_G 0x150 |
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| 103 | #define TXDEFERRED 0x154 |
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| 104 | #define TXLATECOL 0x158 |
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| 105 | #define TXEXESSCOL 0x15C |
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| 106 | #define TXCARRIERERR 0x160 |
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| 107 | #define TXOCTETCNT 0x164 |
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| 108 | #define TXFRAMECOUNT_G 0x168 |
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| 109 | #define TXEXCESSDEF 0x16C |
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| 110 | #define TXPAUSEFRAMES 0x170 |
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| 111 | #define TXVLANFRAMES_G 0x174 |
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| 112 | #define TXOVERSIZE_G 0x178 |
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| 113 | #define RXFRAMECOUNT_GB 0x180 |
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| 114 | #define RXOCTETCOUNT_GB 0x184 |
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| 115 | #define RXOCTETCOUNT_G 0x188 |
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| 116 | #define RXBROADCASTFRAMES_G 0x18C |
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| 117 | #define RXMULTICASTFRAMES_G 0x190 |
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| 118 | #define RXCRCERROR 0x194 |
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| 119 | #define RXALIGNMENTERROR 0x198 |
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| 120 | #define RXRUNTERROR 0x19C |
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| 121 | #define RXJABBERERROR 0x1A0 |
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| 122 | #define RXUNDERSIZE_G 0x1A4 |
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| 123 | #define RXOVERSIZE_G 0x1A8 |
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| 124 | #define RX64OCTETS_GB 0x1AC |
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| 125 | #define RX65TO127OCTETS_GB 0x1B0 |
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| 126 | #define RX128TO255OCTETS_GB 0x1B4 |
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| 127 | #define RX256TO511OCTETS_GB 0x1B8 |
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| 128 | #define RX512TO1023OCTETS_GB 0x1BC |
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| 129 | #define RX1024TOMAXOCTETS_GB 0x1C0 |
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| 130 | #define RXUNICASTFRAMES_G 0x1C4 |
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| 131 | #define RXLENGTHERROR 0x1C8 |
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| 132 | #define RXOUTOFRANGETYPE 0x1CC |
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| 133 | #define RXPAUSEFRAMES 0x1D0 |
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| 134 | #define RXFIFOOVERFLOW 0x1D4 |
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| 135 | #define RXVLANFRAMES_GB 0x1D8 |
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| 136 | #define RXWATCHDOGERROR 0x1DC |
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| 137 | #define RXRCVERROR 0x1E0 |
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| 138 | #define RXCTRLFRAMES_G 0x1E4 |
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| 139 | #define MMC_IPC_RECEIVE_INT_MASK 0x200 |
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| 140 | #define MMC_IPC_RECEIVE_INT 0x208 |
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| 141 | #define RXIPV4_GD_FRMS 0x210 |
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| 142 | #define RXIPV4_HDRERR_FRMS 0x214 |
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| 143 | #define RXIPV4_NOPAY_FRMS 0x218 |
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| 144 | #define RXIPV4_FRAG_FRMS 0x21C |
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| 145 | #define RXIPV4_UDSBL_FRMS 0x220 |
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| 146 | #define RXIPV6_GD_FRMS 0x224 |
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| 147 | #define RXIPV6_HDRERR_FRMS 0x228 |
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| 148 | #define RXIPV6_NOPAY_FRMS 0x22C |
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| 149 | #define RXUDP_GD_FRMS 0x230 |
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| 150 | #define RXUDP_ERR_FRMS 0x234 |
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| 151 | #define RXTCP_GD_FRMS 0x238 |
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| 152 | #define RXTCP_ERR_FRMS 0x23C |
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| 153 | #define RXICMP_GD_FRMS 0x240 |
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| 154 | #define RXICMP_ERR_FRMS 0x244 |
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| 155 | #define RXIPV4_GD_OCTETS 0x250 |
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| 156 | #define RXIPV4_HDRERR_OCTETS 0x254 |
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| 157 | #define RXIPV4_NOPAY_OCTETS 0x258 |
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| 158 | #define RXIPV4_FRAG_OCTETS 0x25C |
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| 159 | #define RXIPV4_UDSBL_OCTETS 0x260 |
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| 160 | #define RXIPV6_GD_OCTETS 0x264 |
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| 161 | #define RXIPV6_HDRERR_OCTETS 0x268 |
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| 162 | #define RXIPV6_NOPAY_OCTETS 0x26C |
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| 163 | #define RXUDP_GD_OCTETS 0x270 |
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| 164 | #define RXUDP_ERR_OCTETS 0x274 |
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| 165 | #define RXTCP_GD_OCTETS 0x278 |
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| 166 | #define RXTCPERROCTETS 0x27C |
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| 167 | #define RXICMP_GD_OCTETS 0x280 |
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| 168 | #define RXICMP_ERR_OCTETS 0x284 |
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| 169 | #define L3_L4_CONTROL0 0x400 |
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| 170 | #define LAYER4_ADDRESS0 0x404 |
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| 171 | #define LAYER3_ADDR0_REG0 0x410 |
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| 172 | #define LAYER3_ADDR1_REG0 0x414 |
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| 173 | #define LAYER3_ADDR2_REG0 0x418 |
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| 174 | #define LAYER3_ADDR3_REG0 0x41C |
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| 175 | #define L3_L4_CONTROL1 0x430 |
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| 176 | #define LAYER4_ADDRESS1 0x434 |
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| 177 | #define LAYER3_ADDR0_REG1 0x440 |
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| 178 | #define LAYER3_ADDR1_REG1 0x444 |
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| 179 | #define LAYER3_ADDR2_REG1 0x448 |
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| 180 | #define LAYER3_ADDR3_REG1 0x44C |
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| 181 | #define L3_L4_CONTROL2 0x460 |
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| 182 | #define LAYER4_ADDRESS2 0x464 |
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| 183 | #define LAYER3_ADDR0_REG2 0x470 |
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| 184 | #define LAYER3_ADDR1_REG2 0x474 |
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| 185 | #define LAYER3_ADDR2_REG2 0x478 |
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| 186 | #define LAYER3_ADDR3_REG2 0x47C |
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| 187 | #define L3_L4_CONTROL3 0x490 |
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| 188 | #define LAYER4_ADDRESS3 0x494 |
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| 189 | #define LAYER3_ADDR0_REG3 0x4A0 |
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| 190 | #define LAYER3_ADDR1_REG3 0x4A4 |
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| 191 | #define LAYER3_ADDR2_REG3 0x4A8 |
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| 192 | #define LAYER3_ADDR3_REG3 0x4AC |
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| 193 | #define HASH_TABLE_REG(n) 0x500 + (0x4 * n) |
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| 194 | #define VLAN_INCL_REG 0x584 |
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| 195 | #define VLAN_HASH_TABLE_REG 0x588 |
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| 196 | #define TIMESTAMP_CONTROL 0x700 |
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| 197 | #define SUB_SECOND_INCREMENT 0x704 |
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| 198 | #define SYSTEM_TIME_SECONDS 0x708 |
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| 199 | #define SYSTEM_TIME_NANOSECONDS 0x70C |
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| 200 | #define SYSTEM_TIME_SECONDS_UPDATE 0x710 |
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| 201 | #define SYSTEM_TIME_NANOSECONDS_UPDATE 0x714 |
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| 202 | #define TIMESTAMP_ADDEND 0x718 |
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| 203 | #define TARGET_TIME_SECONDS 0x71C |
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| 204 | #define TARGET_TIME_NANOSECONDS 0x720 |
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| 205 | #define SYSTEM_TIME_HIGHER_WORD_SECONDS 0x724 |
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| 206 | #define TIMESTAMP_STATUS 0x728 |
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| 207 | #define PPS_CONTROL 0x72C |
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| 208 | #define AUXILIARY_TIMESTAMP_NANOSECONDS 0x730 |
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| 209 | #define AUXILIARY_TIMESTAMP_SECONDS 0x734 |
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| 210 | #define PPS0_INTERVAL 0x760 |
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| 211 | #define PPS0_WIDTH 0x764 |
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| 212 | |
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| 213 | /* DMA */ |
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| 214 | #define BUS_MODE 0x1000 |
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| 215 | #define BUS_MODE_EIGHTXPBL (1 << 24) /* Multiplies PBL by 8 */ |
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| 216 | #define BUS_MODE_FIXEDBURST (1 << 16) |
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| 217 | #define BUS_MODE_PRIORXTX_SHIFT 14 |
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| 218 | #define BUS_MODE_PRIORXTX_41 3 |
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| 219 | #define BUS_MODE_PRIORXTX_31 2 |
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| 220 | #define BUS_MODE_PRIORXTX_21 1 |
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| 221 | #define BUS_MODE_PRIORXTX_11 0 |
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| 222 | #define BUS_MODE_PBL_SHIFT 8 /* Single block transfer size */ |
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| 223 | #define BUS_MODE_PBL_BEATS_8 8 |
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| 224 | #define BUS_MODE_ATDS (1 << 7) /* Alternate Descriptor Size */ |
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| 225 | #define BUS_MODE_SWR (1 << 0) /* Reset */ |
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| 226 | #define TRANSMIT_POLL_DEMAND 0x1004 |
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| 227 | #define RECEIVE_POLL_DEMAND 0x1008 |
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| 228 | #define RX_DESCR_LIST_ADDR 0x100C |
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| 229 | #define TX_DESCR_LIST_ADDR 0x1010 |
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| 230 | #define DMA_STATUS 0x1014 |
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| 231 | #define DMA_STATUS_NIS (1 << 16) |
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| 232 | #define DMA_STATUS_AIS (1 << 15) |
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| 233 | #define DMA_STATUS_FBI (1 << 13) |
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| 234 | #define DMA_STATUS_RU (1 << 7) |
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| 235 | #define DMA_STATUS_RI (1 << 6) |
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| 236 | #define DMA_STATUS_TI (1 << 0) |
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| 237 | #define DMA_STATUS_INTR_MASK 0x1ffff |
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| 238 | #define OPERATION_MODE 0x1018 |
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| 239 | #define MODE_RSF (1 << 25) /* RX Full Frame */ |
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| 240 | #define MODE_TSF (1 << 21) /* TX Full Frame */ |
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| 241 | #define MODE_FTF (1 << 20) /* Flush TX FIFO */ |
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| 242 | #define MODE_ST (1 << 13) /* Start DMA TX */ |
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| 243 | #define MODE_FUF (1 << 6) /* TX frames < 64bytes */ |
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| 244 | #define MODE_RTC_LEV32 0x1 |
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| 245 | #define MODE_RTC_SHIFT 3 |
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| 246 | #define MODE_OSF (1 << 2) /* Process Second frame */ |
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| 247 | #define MODE_SR (1 << 1) /* Start DMA RX */ |
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| 248 | #define INTERRUPT_ENABLE 0x101C |
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| 249 | #define INT_EN_NIE (1 << 16) /* Normal/Summary */ |
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| 250 | #define INT_EN_AIE (1 << 15) /* Abnormal/Summary */ |
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| 251 | #define INT_EN_ERE (1 << 14) /* Early receive */ |
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| 252 | #define INT_EN_FBE (1 << 13) /* Fatal bus error */ |
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| 253 | #define INT_EN_ETE (1 << 10) /* Early transmit */ |
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| 254 | #define INT_EN_RWE (1 << 9) /* Receive watchdog */ |
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| 255 | #define INT_EN_RSE (1 << 8) /* Receive stopped */ |
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| 256 | #define INT_EN_RUE (1 << 7) /* Recv buf unavailable */ |
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| 257 | #define INT_EN_RIE (1 << 6) /* Receive interrupt */ |
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| 258 | #define INT_EN_UNE (1 << 5) /* Tx underflow */ |
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| 259 | #define INT_EN_OVE (1 << 4) /* Receive overflow */ |
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| 260 | #define INT_EN_TJE (1 << 3) /* Transmit jabber */ |
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| 261 | #define INT_EN_TUE (1 << 2) /* Tx. buf unavailable */ |
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| 262 | #define INT_EN_TSE (1 << 1) /* Transmit stopped */ |
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| 263 | #define INT_EN_TIE (1 << 0) /* Transmit interrupt */ |
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| 264 | #define INT_EN_DEFAULT (INT_EN_TIE|INT_EN_RIE| \ |
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| 265 | INT_EN_NIE|INT_EN_AIE| \ |
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| 266 | INT_EN_FBE|INT_EN_UNE) |
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| 267 | |
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| 268 | #define MISSED_FRAMEBUF_OVERFLOW_CNTR 0x1020 |
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| 269 | #define RECEIVE_INT_WATCHDOG_TMR 0x1024 |
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| 270 | #define AXI_BUS_MODE 0x1028 |
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| 271 | #define AHB_OR_AXI_STATUS 0x102C |
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| 272 | #define CURRENT_HOST_TRANSMIT_DESCR 0x1048 |
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| 273 | #define CURRENT_HOST_RECEIVE_DESCR 0x104C |
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| 274 | #define CURRENT_HOST_TRANSMIT_BUF_ADDR 0x1050 |
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| 275 | #define CURRENT_HOST_RECEIVE_BUF_ADDR 0x1054 |
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| 276 | #define HW_FEATURE 0x1058 |
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| 277 | |
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| 278 | #define DWC_GMAC 0x1 |
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| 279 | #define DWC_GMAC_ALT_DESC 0x2 |
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| 280 | #define GMAC_MII_CLK_60_100M_DIV42 0x0 |
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| 281 | #define GMAC_MII_CLK_100_150M_DIV62 0x1 |
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| 282 | #define GMAC_MII_CLK_25_35M_DIV16 0x2 |
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| 283 | #define GMAC_MII_CLK_35_60M_DIV26 0x3 |
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| 284 | #define GMAC_MII_CLK_150_250M_DIV102 0x4 |
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| 285 | #define GMAC_MII_CLK_250_300M_DIV124 0x5 |
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| 286 | #define GMAC_MII_CLK_DIV4 0x8 |
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| 287 | #define GMAC_MII_CLK_DIV6 0x9 |
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| 288 | #define GMAC_MII_CLK_DIV8 0xa |
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| 289 | #define GMAC_MII_CLK_DIV10 0xb |
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| 290 | #define GMAC_MII_CLK_DIV12 0xc |
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| 291 | #define GMAC_MII_CLK_DIV14 0xd |
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| 292 | #define GMAC_MII_CLK_DIV16 0xe |
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| 293 | #define GMAC_MII_CLK_DIV18 0xf |
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| 294 | |
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| 295 | #endif /* __IF_DWC_H__ */ |
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