1 | #include <machine/rtems-bsd-kernel-space.h> |
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2 | |
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3 | /*- |
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4 | * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> |
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5 | * All rights reserved. |
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6 | * |
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7 | * This software was developed by SRI International and the University of |
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8 | * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) |
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9 | * ("CTSRD"), as part of the DARPA CRASH research programme. |
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10 | * |
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11 | * Redistribution and use in source and binary forms, with or without |
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12 | * modification, are permitted provided that the following conditions |
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13 | * are met: |
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14 | * 1. Redistributions of source code must retain the above copyright |
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15 | * notice, this list of conditions and the following disclaimer. |
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16 | * 2. Redistributions in binary form must reproduce the above copyright |
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17 | * notice, this list of conditions and the following disclaimer in the |
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18 | * documentation and/or other materials provided with the distribution. |
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19 | * |
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20 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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21 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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22 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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23 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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24 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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25 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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26 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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27 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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28 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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29 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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30 | * SUCH DAMAGE. |
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31 | */ |
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32 | |
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33 | /* |
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34 | * Ethernet media access controller (EMAC) |
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35 | * Chapter 17, Altera Cyclone V Device Handbook (CV-5V2 2014.07.22) |
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36 | * |
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37 | * EMAC is an instance of the Synopsys DesignWare 3504-0 |
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38 | * Universal 10/100/1000 Ethernet MAC (DWC_gmac). |
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39 | */ |
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40 | |
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41 | #include <sys/cdefs.h> |
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42 | __FBSDID("$FreeBSD$"); |
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43 | |
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44 | #include <rtems/bsd/sys/param.h> |
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45 | #include <sys/systm.h> |
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46 | #include <sys/bus.h> |
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47 | #include <sys/kernel.h> |
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48 | #include <sys/module.h> |
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49 | #include <sys/malloc.h> |
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50 | #include <sys/rman.h> |
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51 | #include <sys/endian.h> |
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52 | #include <rtems/bsd/sys/lock.h> |
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53 | #include <sys/mbuf.h> |
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54 | #include <sys/mutex.h> |
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55 | #include <sys/socket.h> |
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56 | #include <sys/sockio.h> |
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57 | #include <sys/sysctl.h> |
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58 | |
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59 | #ifndef __rtems__ |
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60 | #include <dev/fdt/fdt_common.h> |
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61 | #include <dev/ofw/openfirm.h> |
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62 | #include <dev/ofw/ofw_bus.h> |
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63 | #include <dev/ofw/ofw_bus_subr.h> |
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64 | #endif /* __rtems__ */ |
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65 | |
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66 | #include <net/bpf.h> |
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67 | #include <net/if.h> |
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68 | #include <net/ethernet.h> |
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69 | #include <net/if_dl.h> |
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70 | #include <net/if_media.h> |
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71 | #include <net/if_types.h> |
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72 | #include <net/if_var.h> |
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73 | #include <net/if_vlan_var.h> |
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74 | |
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75 | #include <machine/bus.h> |
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76 | #ifndef __rtems__ |
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77 | #include <machine/fdt.h> |
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78 | #endif /* __rtems__ */ |
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79 | |
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80 | #include <dev/mii/mii.h> |
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81 | #include <dev/mii/miivar.h> |
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82 | #include <rtems/bsd/local/miibus_if.h> |
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83 | #ifdef __rtems__ |
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84 | #pragma GCC diagnostic ignored "-Wpointer-sign" |
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85 | #include <rtems/bsd/bsd.h> |
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86 | #endif /* __rtems__ */ |
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87 | |
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88 | #define READ4(_sc, _reg) \ |
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89 | bus_read_4((_sc)->res[0], _reg) |
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90 | #define WRITE4(_sc, _reg, _val) \ |
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91 | bus_write_4((_sc)->res[0], _reg, _val) |
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92 | |
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93 | #define MAC_RESET_TIMEOUT 100 |
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94 | #define WATCHDOG_TIMEOUT_SECS 5 |
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95 | #define STATS_HARVEST_INTERVAL 2 |
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96 | #define MII_CLK_VAL 2 |
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97 | |
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98 | #include <dev/dwc/if_dwc.h> |
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99 | |
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100 | #define DWC_LOCK(sc) mtx_lock(&(sc)->mtx) |
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101 | #define DWC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) |
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102 | #define DWC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED); |
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103 | #define DWC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED); |
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104 | |
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105 | #define DDESC_TDES0_OWN (1 << 31) |
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106 | #define DDESC_TDES0_TXINT (1 << 30) |
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107 | #define DDESC_TDES0_TXLAST (1 << 29) |
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108 | #define DDESC_TDES0_TXFIRST (1 << 28) |
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109 | #define DDESC_TDES0_TXCRCDIS (1 << 27) |
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110 | #define DDESC_TDES0_CIC_IP_HDR (0x1 << 22) |
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111 | #define DDESC_TDES0_CIC_IP_HDR_PYL (0x2 << 22) |
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112 | #define DDESC_TDES0_CIC_IP_HDR_PYL_PHDR (0x3 << 22) |
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113 | #define DDESC_TDES0_TXRINGEND (1 << 21) |
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114 | #define DDESC_TDES0_TXCHAIN (1 << 20) |
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115 | |
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116 | #define DDESC_RDES0_OWN (1 << 31) |
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117 | #define DDESC_RDES0_FL_MASK 0x3fff |
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118 | #define DDESC_RDES0_FL_SHIFT 16 /* Frame Length */ |
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119 | #define DDESC_RDES0_ESA (1 << 0) |
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120 | #define DDESC_RDES1_CHAINED (1 << 14) |
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121 | #define DDESC_RDES4_IP_PYL_ERR (1 << 4) |
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122 | #define DDESC_RDES4_IP_HDR_ERR (1 << 3) |
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123 | #define DDESC_RDES4_IP_PYL_TYPE_MSK 0x7 |
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124 | #define DDESC_RDES4_IP_PYL_UDP 1 |
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125 | #define DDESC_RDES4_IP_PYL_TCP 2 |
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126 | |
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127 | struct dwc_bufmap { |
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128 | #ifndef __rtems__ |
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129 | bus_dmamap_t map; |
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130 | #endif /* __rtems__ */ |
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131 | struct mbuf *mbuf; |
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132 | }; |
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133 | |
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134 | /* |
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135 | * A hardware buffer descriptor. Rx and Tx buffers have the same descriptor |
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136 | * layout, but the bits in the flags field have different meanings. |
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137 | */ |
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138 | struct dwc_hwdesc |
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139 | { |
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140 | uint32_t tdes0; |
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141 | uint32_t tdes1; |
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142 | uint32_t addr; /* pointer to buffer data */ |
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143 | uint32_t addr_next; /* link to next descriptor */ |
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144 | uint32_t tdes4; |
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145 | uint32_t tdes5; |
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146 | uint32_t timestamp_low; |
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147 | uint32_t timestamp_high; |
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148 | }; |
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149 | |
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150 | /* |
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151 | * Driver data and defines. |
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152 | */ |
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153 | #ifndef __rtems__ |
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154 | #define RX_DESC_COUNT 1024 |
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155 | #else /* __rtems__ */ |
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156 | #define RX_DESC_COUNT 256 |
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157 | #endif /* __rtems__ */ |
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158 | #define RX_DESC_SIZE (sizeof(struct dwc_hwdesc) * RX_DESC_COUNT) |
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159 | #define TX_DESC_COUNT 1024 |
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160 | #define TX_DESC_SIZE (sizeof(struct dwc_hwdesc) * TX_DESC_COUNT) |
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161 | #define TX_MAX_DMA_SEGS 8 /* maximum segs in a tx mbuf dma */ |
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162 | |
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163 | /* |
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164 | * The hardware imposes alignment restrictions on various objects involved in |
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165 | * DMA transfers. These values are expressed in bytes (not bits). |
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166 | */ |
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167 | #define DWC_DESC_RING_ALIGN 2048 |
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168 | |
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169 | #define DWC_CKSUM_ASSIST (CSUM_IP | CSUM_TCP | CSUM_UDP | \ |
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170 | CSUM_TCP_IPV6 | CSUM_UDP_IPV6) |
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171 | |
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172 | struct dwc_softc { |
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173 | struct resource *res[2]; |
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174 | bus_space_tag_t bst; |
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175 | bus_space_handle_t bsh; |
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176 | device_t dev; |
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177 | int mii_clk; |
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178 | device_t miibus; |
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179 | struct mii_data * mii_softc; |
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180 | struct ifnet *ifp; |
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181 | int if_flags; |
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182 | struct mtx mtx; |
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183 | void * intr_cookie; |
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184 | struct callout dwc_callout; |
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185 | uint8_t phy_conn_type; |
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186 | uint8_t mactype; |
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187 | boolean_t link_is_up; |
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188 | boolean_t is_attached; |
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189 | boolean_t is_detaching; |
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190 | int tx_watchdog_count; |
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191 | int stats_harvest_count; |
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192 | |
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193 | /* RX */ |
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194 | bus_dma_tag_t rxdesc_tag; |
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195 | bus_dmamap_t rxdesc_map; |
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196 | struct dwc_hwdesc *rxdesc_ring; |
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197 | #ifndef __rtems__ |
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198 | bus_addr_t rxdesc_ring_paddr; |
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199 | bus_dma_tag_t rxbuf_tag; |
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200 | #endif /* __rtems__ */ |
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201 | struct dwc_bufmap rxbuf_map[RX_DESC_COUNT]; |
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202 | uint32_t rx_idx; |
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203 | |
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204 | /* TX */ |
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205 | bus_dma_tag_t txdesc_tag; |
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206 | bus_dmamap_t txdesc_map; |
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207 | struct dwc_hwdesc *txdesc_ring; |
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208 | #ifndef __rtems__ |
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209 | bus_addr_t txdesc_ring_paddr; |
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210 | bus_dma_tag_t txbuf_tag; |
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211 | #endif /* __rtems__ */ |
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212 | struct dwc_bufmap txbuf_map[TX_DESC_COUNT]; |
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213 | uint32_t tx_idx_head; |
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214 | uint32_t tx_idx_tail; |
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215 | int txcount; |
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216 | }; |
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217 | |
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218 | static struct resource_spec dwc_spec[] = { |
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219 | { SYS_RES_MEMORY, 0, RF_ACTIVE }, |
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220 | { SYS_RES_IRQ, 0, RF_ACTIVE }, |
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221 | { -1, 0 } |
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222 | }; |
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223 | |
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224 | static void dwc_txfinish_locked(struct dwc_softc *sc); |
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225 | static void dwc_rxfinish_locked(struct dwc_softc *sc); |
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226 | static void dwc_stop_locked(struct dwc_softc *sc); |
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227 | static void dwc_setup_rxfilter(struct dwc_softc *sc); |
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228 | |
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229 | static inline uint32_t |
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230 | next_rxidx(struct dwc_softc *sc, uint32_t curidx) |
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231 | { |
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232 | |
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233 | return ((curidx + 1) % RX_DESC_COUNT); |
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234 | } |
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235 | |
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236 | static inline uint32_t |
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237 | next_txidx(struct dwc_softc *sc, uint32_t curidx, int inc) |
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238 | { |
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239 | |
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240 | return ((curidx + (uint32_t)inc) % TX_DESC_COUNT); |
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241 | } |
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242 | |
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243 | #ifndef __rtems__ |
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244 | static void |
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245 | dwc_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) |
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246 | { |
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247 | |
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248 | if (error != 0) |
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249 | return; |
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250 | *(bus_addr_t *)arg = segs[0].ds_addr; |
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251 | } |
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252 | #endif /* __rtems__ */ |
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253 | |
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254 | static void |
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255 | dwc_setup_txdesc(struct dwc_softc *sc, int csum_flags, int idx, |
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256 | bus_dma_segment_t segs[TX_MAX_DMA_SEGS], int nsegs) |
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257 | { |
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258 | int i; |
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259 | |
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260 | sc->txcount += nsegs; |
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261 | |
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262 | idx = next_txidx(sc, idx, nsegs); |
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263 | sc->tx_idx_head = idx; |
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264 | |
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265 | /* |
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266 | * Fill in the TX descriptors back to front so that OWN bit in first |
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267 | * descriptor is set last. |
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268 | */ |
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269 | for (i = nsegs - 1; i >= 0; i--) { |
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270 | uint32_t tdes0; |
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271 | |
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272 | idx = next_txidx(sc, idx, -1); |
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273 | |
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274 | sc->txdesc_ring[idx].addr = segs[i].ds_addr; |
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275 | sc->txdesc_ring[idx].tdes1 = segs[i].ds_len; |
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276 | wmb(); |
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277 | |
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278 | tdes0 = DDESC_TDES0_TXCHAIN | DDESC_TDES0_TXINT | |
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279 | DDESC_TDES0_OWN; |
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280 | |
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281 | if (i == 0) { |
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282 | tdes0 |= DDESC_TDES0_TXFIRST; |
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283 | |
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284 | if ((csum_flags & (CSUM_TCP | CSUM_UDP | |
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285 | CSUM_TCP_IPV6 | CSUM_UDP_IPV6)) != 0) |
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286 | tdes0 |= DDESC_TDES0_CIC_IP_HDR_PYL_PHDR; |
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287 | else if ((csum_flags & CSUM_IP) != 0) |
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288 | tdes0 |= DDESC_TDES0_CIC_IP_HDR; |
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289 | } |
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290 | |
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291 | if (i == nsegs - 1) |
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292 | tdes0 |= DDESC_TDES0_TXLAST; |
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293 | |
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294 | sc->txdesc_ring[idx].tdes0 = tdes0; |
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295 | wmb(); |
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296 | |
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297 | if (i != 0) |
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298 | sc->txbuf_map[idx].mbuf = NULL; |
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299 | } |
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300 | } |
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301 | |
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302 | #ifdef __rtems__ |
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303 | static int |
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304 | dwc_get_segs_for_tx(struct mbuf *m, bus_dma_segment_t segs[TX_MAX_DMA_SEGS], |
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305 | int *nsegs) |
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306 | { |
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307 | int i = 0; |
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308 | |
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309 | do { |
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310 | if (m->m_len > 0) { |
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311 | segs[i].ds_addr = mtod(m, bus_addr_t); |
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312 | segs[i].ds_len = m->m_len; |
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313 | rtems_cache_flush_multiple_data_lines(m->m_data, m->m_len); |
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314 | ++i; |
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315 | } |
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316 | |
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317 | m = m->m_next; |
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318 | |
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319 | if (m == NULL) { |
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320 | *nsegs = i; |
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321 | |
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322 | return (0); |
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323 | } |
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324 | } while (i < TX_MAX_DMA_SEGS); |
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325 | |
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326 | return (EFBIG); |
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327 | } |
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328 | #endif /* __rtems__ */ |
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329 | static void |
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330 | dwc_setup_txbuf(struct dwc_softc *sc, struct mbuf *m, int *start_tx) |
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331 | { |
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332 | bus_dma_segment_t segs[TX_MAX_DMA_SEGS]; |
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333 | int error, nsegs, idx; |
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334 | |
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335 | idx = sc->tx_idx_head; |
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336 | #ifndef __rtems__ |
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337 | error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map, |
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338 | m, &seg, &nsegs, BUS_DMA_NOWAIT); |
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339 | |
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340 | #else /* __rtems__ */ |
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341 | error = dwc_get_segs_for_tx(m, segs, &nsegs); |
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342 | #endif /* __rtems__ */ |
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343 | if (error == EFBIG) { |
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344 | /* Too many segments! Defrag and try again. */ |
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345 | struct mbuf *m2 = m_defrag(m, M_NOWAIT); |
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346 | |
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347 | if (m2 == NULL) { |
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348 | m_freem(m); |
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349 | return; |
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350 | } |
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351 | m = m2; |
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352 | #ifndef __rtems__ |
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353 | error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, |
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354 | sc->txbuf_map[idx].map, m, &seg, &nsegs, BUS_DMA_NOWAIT); |
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355 | #else /* __rtems__ */ |
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356 | error = dwc_get_segs_for_tx(m, segs, &nsegs); |
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357 | #endif /* __rtems__ */ |
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358 | } |
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359 | if (error != 0) { |
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360 | /* Give up. */ |
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361 | m_freem(m); |
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362 | return; |
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363 | } |
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364 | |
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365 | sc->txbuf_map[idx].mbuf = m; |
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366 | |
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367 | #ifndef __rtems__ |
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368 | bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map, |
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369 | BUS_DMASYNC_PREWRITE); |
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370 | #endif /* __rtems__ */ |
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371 | |
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372 | dwc_setup_txdesc(sc, m->m_pkthdr.csum_flags, idx, segs, nsegs); |
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373 | |
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374 | ETHER_BPF_MTAP(sc->ifp, m); |
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375 | *start_tx = 1; |
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376 | } |
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377 | |
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378 | static void |
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379 | dwc_txstart_locked(struct dwc_softc *sc) |
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380 | { |
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381 | struct ifnet *ifp; |
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382 | struct mbuf *m; |
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383 | int start_tx; |
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384 | |
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385 | DWC_ASSERT_LOCKED(sc); |
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386 | |
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387 | if (!sc->link_is_up) |
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388 | return; |
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389 | |
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390 | ifp = sc->ifp; |
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391 | |
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392 | start_tx = 0; |
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393 | |
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394 | for (;;) { |
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395 | if (sc->txcount >= (TX_DESC_COUNT - 1 - TX_MAX_DMA_SEGS)) { |
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396 | ifp->if_drv_flags |= IFF_DRV_OACTIVE; |
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397 | break; |
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398 | } |
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399 | |
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400 | IFQ_DRV_DEQUEUE(&ifp->if_snd, m); |
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401 | if (m == NULL) |
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402 | break; |
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403 | |
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404 | dwc_setup_txbuf(sc, m, &start_tx); |
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405 | } |
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406 | |
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407 | if (start_tx != 0) { |
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408 | WRITE4(sc, TRANSMIT_POLL_DEMAND, 0x1); |
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409 | sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS; |
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410 | } |
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411 | } |
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412 | |
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413 | static void |
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414 | dwc_txstart(struct ifnet *ifp) |
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415 | { |
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416 | struct dwc_softc *sc = ifp->if_softc; |
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417 | |
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418 | DWC_LOCK(sc); |
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419 | if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) |
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420 | dwc_txstart_locked(sc); |
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421 | DWC_UNLOCK(sc); |
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422 | } |
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423 | |
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424 | static void |
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425 | dwc_stop_locked(struct dwc_softc *sc) |
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426 | { |
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427 | struct ifnet *ifp; |
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428 | int reg; |
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429 | |
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430 | DWC_ASSERT_LOCKED(sc); |
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431 | |
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432 | ifp = sc->ifp; |
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433 | ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); |
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434 | sc->tx_watchdog_count = 0; |
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435 | sc->stats_harvest_count = 0; |
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436 | |
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437 | callout_stop(&sc->dwc_callout); |
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438 | |
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439 | /* Stop DMA TX */ |
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440 | reg = READ4(sc, OPERATION_MODE); |
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441 | reg &= ~(MODE_ST); |
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442 | WRITE4(sc, OPERATION_MODE, reg); |
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443 | |
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444 | /* Flush TX */ |
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445 | reg = READ4(sc, OPERATION_MODE); |
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446 | reg |= (MODE_FTF); |
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447 | WRITE4(sc, OPERATION_MODE, reg); |
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448 | |
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449 | /* Stop transmitters */ |
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450 | reg = READ4(sc, MAC_CONFIGURATION); |
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451 | reg &= ~(CONF_TE | CONF_RE); |
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452 | WRITE4(sc, MAC_CONFIGURATION, reg); |
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453 | |
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454 | /* Stop DMA RX */ |
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455 | reg = READ4(sc, OPERATION_MODE); |
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456 | reg &= ~(MODE_SR); |
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457 | WRITE4(sc, OPERATION_MODE, reg); |
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458 | } |
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459 | |
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460 | static void dwc_clear_stats(struct dwc_softc *sc) |
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461 | { |
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462 | int reg; |
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463 | |
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464 | reg = READ4(sc, MMC_CONTROL); |
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465 | reg |= (MMC_CONTROL_CNTRST); |
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466 | WRITE4(sc, MMC_CONTROL, reg); |
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467 | } |
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468 | |
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469 | static void |
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470 | dwc_harvest_stats(struct dwc_softc *sc) |
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471 | { |
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472 | struct ifnet *ifp; |
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473 | |
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474 | /* We don't need to harvest too often. */ |
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475 | if (++sc->stats_harvest_count < STATS_HARVEST_INTERVAL) |
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476 | return; |
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477 | |
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478 | sc->stats_harvest_count = 0; |
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479 | ifp = sc->ifp; |
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480 | |
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481 | #ifndef __rtems__ |
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482 | if_inc_counter(ifp, IFCOUNTER_IPACKETS, READ4(sc, RXFRAMECOUNT_GB)); |
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483 | if_inc_counter(ifp, IFCOUNTER_IMCASTS, READ4(sc, RXMULTICASTFRAMES_G)); |
---|
484 | if_inc_counter(ifp, IFCOUNTER_IERRORS, |
---|
485 | READ4(sc, RXOVERSIZE_G) + READ4(sc, RXUNDERSIZE_G) + |
---|
486 | READ4(sc, RXCRCERROR) + READ4(sc, RXALIGNMENTERROR) + |
---|
487 | READ4(sc, RXRUNTERROR) + READ4(sc, RXJABBERERROR) + |
---|
488 | READ4(sc, RXLENGTHERROR)); |
---|
489 | |
---|
490 | if_inc_counter(ifp, IFCOUNTER_OPACKETS, READ4(sc, TXFRAMECOUNT_G)); |
---|
491 | if_inc_counter(ifp, IFCOUNTER_OMCASTS, READ4(sc, TXMULTICASTFRAMES_G)); |
---|
492 | if_inc_counter(ifp, IFCOUNTER_OERRORS, |
---|
493 | READ4(sc, TXOVERSIZE_G) + READ4(sc, TXEXCESSDEF) + |
---|
494 | READ4(sc, TXCARRIERERR) + READ4(sc, TXUNDERFLOWERROR)); |
---|
495 | |
---|
496 | if_inc_counter(ifp, IFCOUNTER_COLLISIONS, |
---|
497 | READ4(sc, TXEXESSCOL) + READ4(sc, TXLATECOL)); |
---|
498 | #else /* __rtems__ */ |
---|
499 | ifp->if_ipackets += READ4(sc, RXFRAMECOUNT_GB); |
---|
500 | ifp->if_imcasts += READ4(sc, RXMULTICASTFRAMES_G); |
---|
501 | ifp->if_ierrors += |
---|
502 | READ4(sc, RXOVERSIZE_G) + READ4(sc, RXUNDERSIZE_G) + |
---|
503 | READ4(sc, RXCRCERROR) + READ4(sc, RXALIGNMENTERROR) + |
---|
504 | READ4(sc, RXRUNTERROR) + READ4(sc, RXJABBERERROR) + |
---|
505 | READ4(sc, RXLENGTHERROR); |
---|
506 | |
---|
507 | ifp->if_opackets += READ4(sc, TXFRAMECOUNT_G); |
---|
508 | ifp->if_omcasts += READ4(sc, TXMULTICASTFRAMES_G); |
---|
509 | ifp->if_oerrors += |
---|
510 | READ4(sc, TXOVERSIZE_G) + READ4(sc, TXEXCESSDEF) + |
---|
511 | READ4(sc, TXCARRIERERR) + READ4(sc, TXUNDERFLOWERROR); |
---|
512 | |
---|
513 | ifp->if_collisions += |
---|
514 | READ4(sc, TXEXESSCOL) + READ4(sc, TXLATECOL); |
---|
515 | #endif /* __rtems__ */ |
---|
516 | |
---|
517 | dwc_clear_stats(sc); |
---|
518 | } |
---|
519 | |
---|
520 | static void |
---|
521 | dwc_tick(void *arg) |
---|
522 | { |
---|
523 | struct dwc_softc *sc; |
---|
524 | struct ifnet *ifp; |
---|
525 | int link_was_up; |
---|
526 | |
---|
527 | sc = arg; |
---|
528 | |
---|
529 | DWC_ASSERT_LOCKED(sc); |
---|
530 | |
---|
531 | ifp = sc->ifp; |
---|
532 | |
---|
533 | if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) |
---|
534 | return; |
---|
535 | |
---|
536 | /* |
---|
537 | * Typical tx watchdog. If this fires it indicates that we enqueued |
---|
538 | * packets for output and never got a txdone interrupt for them. Maybe |
---|
539 | * it's a missed interrupt somehow, just pretend we got one. |
---|
540 | */ |
---|
541 | if (sc->tx_watchdog_count > 0) { |
---|
542 | if (--sc->tx_watchdog_count == 0) { |
---|
543 | dwc_txfinish_locked(sc); |
---|
544 | } |
---|
545 | } |
---|
546 | |
---|
547 | /* Gather stats from hardware counters. */ |
---|
548 | dwc_harvest_stats(sc); |
---|
549 | |
---|
550 | /* Check the media status. */ |
---|
551 | link_was_up = sc->link_is_up; |
---|
552 | mii_tick(sc->mii_softc); |
---|
553 | if (sc->link_is_up && !link_was_up) |
---|
554 | dwc_txstart_locked(sc); |
---|
555 | |
---|
556 | /* Schedule another check one second from now. */ |
---|
557 | callout_reset(&sc->dwc_callout, hz, dwc_tick, sc); |
---|
558 | } |
---|
559 | |
---|
560 | static void |
---|
561 | dwc_init_locked(struct dwc_softc *sc) |
---|
562 | { |
---|
563 | struct ifnet *ifp = sc->ifp; |
---|
564 | int reg; |
---|
565 | |
---|
566 | DWC_ASSERT_LOCKED(sc); |
---|
567 | |
---|
568 | if (ifp->if_drv_flags & IFF_DRV_RUNNING) |
---|
569 | return; |
---|
570 | |
---|
571 | ifp->if_drv_flags |= IFF_DRV_RUNNING; |
---|
572 | |
---|
573 | dwc_setup_rxfilter(sc); |
---|
574 | |
---|
575 | /* Initializa DMA and enable transmitters */ |
---|
576 | reg = READ4(sc, OPERATION_MODE); |
---|
577 | reg |= (MODE_TSF | MODE_OSF | MODE_FUF); |
---|
578 | reg &= ~(MODE_RSF); |
---|
579 | reg |= (MODE_RTC_LEV32 << MODE_RTC_SHIFT); |
---|
580 | WRITE4(sc, OPERATION_MODE, reg); |
---|
581 | |
---|
582 | WRITE4(sc, INTERRUPT_ENABLE, INT_EN_DEFAULT); |
---|
583 | |
---|
584 | /* Start DMA */ |
---|
585 | reg = READ4(sc, OPERATION_MODE); |
---|
586 | reg |= (MODE_ST | MODE_SR); |
---|
587 | WRITE4(sc, OPERATION_MODE, reg); |
---|
588 | |
---|
589 | /* Enable transmitters */ |
---|
590 | reg = READ4(sc, MAC_CONFIGURATION); |
---|
591 | reg |= (CONF_IPC); |
---|
592 | reg |= (CONF_JD | CONF_ACS | CONF_BE); |
---|
593 | reg |= (CONF_TE | CONF_RE); |
---|
594 | WRITE4(sc, MAC_CONFIGURATION, reg); |
---|
595 | |
---|
596 | /* |
---|
597 | * Call mii_mediachg() which will call back into dwc_miibus_statchg() |
---|
598 | * to set up the remaining config registers based on current media. |
---|
599 | */ |
---|
600 | mii_mediachg(sc->mii_softc); |
---|
601 | callout_reset(&sc->dwc_callout, hz, dwc_tick, sc); |
---|
602 | } |
---|
603 | |
---|
604 | static void |
---|
605 | dwc_init(void *if_softc) |
---|
606 | { |
---|
607 | struct dwc_softc *sc = if_softc; |
---|
608 | |
---|
609 | DWC_LOCK(sc); |
---|
610 | dwc_init_locked(sc); |
---|
611 | DWC_UNLOCK(sc); |
---|
612 | } |
---|
613 | |
---|
614 | inline static uint32_t |
---|
615 | dwc_setup_rxdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr) |
---|
616 | { |
---|
617 | uint32_t nidx; |
---|
618 | |
---|
619 | sc->rxdesc_ring[idx].addr = (uint32_t)paddr; |
---|
620 | nidx = next_rxidx(sc, idx); |
---|
621 | #ifndef __rtems__ |
---|
622 | sc->rxdesc_ring[idx].addr_next = sc->rxdesc_ring_paddr + \ |
---|
623 | (nidx * sizeof(struct dwc_hwdesc)); |
---|
624 | #else /* __rtems__ */ |
---|
625 | sc->rxdesc_ring[idx].addr_next = (uint32_t)&sc->rxdesc_ring[nidx]; |
---|
626 | #endif /* __rtems__ */ |
---|
627 | sc->rxdesc_ring[idx].tdes1 = DDESC_RDES1_CHAINED | MCLBYTES; |
---|
628 | |
---|
629 | wmb(); |
---|
630 | sc->rxdesc_ring[idx].tdes0 = DDESC_RDES0_OWN; |
---|
631 | wmb(); |
---|
632 | |
---|
633 | return (nidx); |
---|
634 | } |
---|
635 | |
---|
636 | static int |
---|
637 | dwc_setup_rxbuf(struct dwc_softc *sc, int idx, struct mbuf *m) |
---|
638 | { |
---|
639 | bus_dma_segment_t seg; |
---|
640 | #ifndef __rtems__ |
---|
641 | int error, nsegs; |
---|
642 | #endif /* __rtems__ */ |
---|
643 | |
---|
644 | m_adj(m, ETHER_ALIGN); |
---|
645 | |
---|
646 | #ifndef __rtems__ |
---|
647 | error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map, |
---|
648 | m, &seg, &nsegs, 0); |
---|
649 | if (error != 0) { |
---|
650 | return (error); |
---|
651 | } |
---|
652 | |
---|
653 | KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); |
---|
654 | |
---|
655 | bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, |
---|
656 | BUS_DMASYNC_PREREAD); |
---|
657 | #else /* __rtems__ */ |
---|
658 | rtems_cache_invalidate_multiple_data_lines(m->m_data, m->m_len); |
---|
659 | seg.ds_addr = mtod(m, bus_addr_t); |
---|
660 | #endif /* __rtems__ */ |
---|
661 | |
---|
662 | sc->rxbuf_map[idx].mbuf = m; |
---|
663 | dwc_setup_rxdesc(sc, idx, seg.ds_addr); |
---|
664 | |
---|
665 | return (0); |
---|
666 | } |
---|
667 | |
---|
668 | static struct mbuf * |
---|
669 | dwc_alloc_mbufcl(struct dwc_softc *sc) |
---|
670 | { |
---|
671 | struct mbuf *m; |
---|
672 | |
---|
673 | m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); |
---|
674 | if (m != NULL) |
---|
675 | m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; |
---|
676 | |
---|
677 | return (m); |
---|
678 | } |
---|
679 | |
---|
680 | static void |
---|
681 | dwc_media_status(struct ifnet * ifp, struct ifmediareq *ifmr) |
---|
682 | { |
---|
683 | struct dwc_softc *sc; |
---|
684 | struct mii_data *mii; |
---|
685 | |
---|
686 | sc = ifp->if_softc; |
---|
687 | mii = sc->mii_softc; |
---|
688 | DWC_LOCK(sc); |
---|
689 | mii_pollstat(mii); |
---|
690 | ifmr->ifm_active = mii->mii_media_active; |
---|
691 | ifmr->ifm_status = mii->mii_media_status; |
---|
692 | DWC_UNLOCK(sc); |
---|
693 | } |
---|
694 | |
---|
695 | static int |
---|
696 | dwc_media_change_locked(struct dwc_softc *sc) |
---|
697 | { |
---|
698 | |
---|
699 | return (mii_mediachg(sc->mii_softc)); |
---|
700 | } |
---|
701 | |
---|
702 | static int |
---|
703 | dwc_media_change(struct ifnet * ifp) |
---|
704 | { |
---|
705 | struct dwc_softc *sc; |
---|
706 | int error; |
---|
707 | |
---|
708 | sc = ifp->if_softc; |
---|
709 | |
---|
710 | DWC_LOCK(sc); |
---|
711 | error = dwc_media_change_locked(sc); |
---|
712 | DWC_UNLOCK(sc); |
---|
713 | return (error); |
---|
714 | } |
---|
715 | |
---|
716 | static const uint8_t nibbletab[] = { |
---|
717 | /* 0x0 0000 -> 0000 */ 0x0, |
---|
718 | /* 0x1 0001 -> 1000 */ 0x8, |
---|
719 | /* 0x2 0010 -> 0100 */ 0x4, |
---|
720 | /* 0x3 0011 -> 1100 */ 0xc, |
---|
721 | /* 0x4 0100 -> 0010 */ 0x2, |
---|
722 | /* 0x5 0101 -> 1010 */ 0xa, |
---|
723 | /* 0x6 0110 -> 0110 */ 0x6, |
---|
724 | /* 0x7 0111 -> 1110 */ 0xe, |
---|
725 | /* 0x8 1000 -> 0001 */ 0x1, |
---|
726 | /* 0x9 1001 -> 1001 */ 0x9, |
---|
727 | /* 0xa 1010 -> 0101 */ 0x5, |
---|
728 | /* 0xb 1011 -> 1101 */ 0xd, |
---|
729 | /* 0xc 1100 -> 0011 */ 0x3, |
---|
730 | /* 0xd 1101 -> 1011 */ 0xb, |
---|
731 | /* 0xe 1110 -> 0111 */ 0x7, |
---|
732 | /* 0xf 1111 -> 1111 */ 0xf, }; |
---|
733 | |
---|
734 | static uint8_t |
---|
735 | bitreverse(uint8_t x) |
---|
736 | { |
---|
737 | |
---|
738 | return (nibbletab[x & 0xf] << 4) | nibbletab[x >> 4]; |
---|
739 | } |
---|
740 | |
---|
741 | static void |
---|
742 | dwc_setup_rxfilter(struct dwc_softc *sc) |
---|
743 | { |
---|
744 | struct ifmultiaddr *ifma; |
---|
745 | struct ifnet *ifp; |
---|
746 | uint8_t *eaddr; |
---|
747 | uint32_t crc; |
---|
748 | uint8_t val; |
---|
749 | int hashbit; |
---|
750 | int hashreg; |
---|
751 | int ffval; |
---|
752 | int reg; |
---|
753 | int lo; |
---|
754 | int hi; |
---|
755 | |
---|
756 | DWC_ASSERT_LOCKED(sc); |
---|
757 | |
---|
758 | ifp = sc->ifp; |
---|
759 | |
---|
760 | /* |
---|
761 | * Set the multicast (group) filter hash. |
---|
762 | */ |
---|
763 | if ((ifp->if_flags & IFF_ALLMULTI)) |
---|
764 | ffval = (FRAME_FILTER_PM); |
---|
765 | else { |
---|
766 | ffval = (FRAME_FILTER_HMC); |
---|
767 | if_maddr_rlock(ifp); |
---|
768 | TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { |
---|
769 | if (ifma->ifma_addr->sa_family != AF_LINK) |
---|
770 | continue; |
---|
771 | crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) |
---|
772 | ifma->ifma_addr), ETHER_ADDR_LEN); |
---|
773 | |
---|
774 | /* Take lower 8 bits and reverse it */ |
---|
775 | val = bitreverse(~crc & 0xff); |
---|
776 | hashreg = (val >> 5); |
---|
777 | hashbit = (val & 31); |
---|
778 | |
---|
779 | reg = READ4(sc, HASH_TABLE_REG(hashreg)); |
---|
780 | reg |= (1 << hashbit); |
---|
781 | WRITE4(sc, HASH_TABLE_REG(hashreg), reg); |
---|
782 | } |
---|
783 | if_maddr_runlock(ifp); |
---|
784 | } |
---|
785 | |
---|
786 | /* |
---|
787 | * Set the individual address filter hash. |
---|
788 | */ |
---|
789 | if (ifp->if_flags & IFF_PROMISC) |
---|
790 | ffval |= (FRAME_FILTER_PR); |
---|
791 | |
---|
792 | /* |
---|
793 | * Set the primary address. |
---|
794 | */ |
---|
795 | eaddr = IF_LLADDR(ifp); |
---|
796 | lo = eaddr[0] | (eaddr[1] << 8) | (eaddr[2] << 16) | |
---|
797 | (eaddr[3] << 24); |
---|
798 | hi = eaddr[4] | (eaddr[5] << 8); |
---|
799 | WRITE4(sc, MAC_ADDRESS_LOW(0), lo); |
---|
800 | WRITE4(sc, MAC_ADDRESS_HIGH(0), hi); |
---|
801 | WRITE4(sc, MAC_FRAME_FILTER, ffval); |
---|
802 | } |
---|
803 | |
---|
804 | static int |
---|
805 | dwc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) |
---|
806 | { |
---|
807 | struct dwc_softc *sc; |
---|
808 | struct mii_data *mii; |
---|
809 | struct ifreq *ifr; |
---|
810 | int mask, error; |
---|
811 | |
---|
812 | sc = ifp->if_softc; |
---|
813 | ifr = (struct ifreq *)data; |
---|
814 | |
---|
815 | error = 0; |
---|
816 | switch (cmd) { |
---|
817 | case SIOCSIFFLAGS: |
---|
818 | DWC_LOCK(sc); |
---|
819 | if (ifp->if_flags & IFF_UP) { |
---|
820 | if (ifp->if_drv_flags & IFF_DRV_RUNNING) { |
---|
821 | if ((ifp->if_flags ^ sc->if_flags) & |
---|
822 | (IFF_PROMISC | IFF_ALLMULTI)) |
---|
823 | dwc_setup_rxfilter(sc); |
---|
824 | } else { |
---|
825 | if (!sc->is_detaching) |
---|
826 | dwc_init_locked(sc); |
---|
827 | } |
---|
828 | } else { |
---|
829 | if (ifp->if_drv_flags & IFF_DRV_RUNNING) |
---|
830 | dwc_stop_locked(sc); |
---|
831 | } |
---|
832 | sc->if_flags = ifp->if_flags; |
---|
833 | DWC_UNLOCK(sc); |
---|
834 | break; |
---|
835 | case SIOCADDMULTI: |
---|
836 | case SIOCDELMULTI: |
---|
837 | if (ifp->if_drv_flags & IFF_DRV_RUNNING) { |
---|
838 | DWC_LOCK(sc); |
---|
839 | dwc_setup_rxfilter(sc); |
---|
840 | DWC_UNLOCK(sc); |
---|
841 | } |
---|
842 | break; |
---|
843 | case SIOCSIFMEDIA: |
---|
844 | case SIOCGIFMEDIA: |
---|
845 | mii = sc->mii_softc; |
---|
846 | error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); |
---|
847 | break; |
---|
848 | case SIOCSIFCAP: |
---|
849 | mask = ifp->if_capenable ^ ifr->ifr_reqcap; |
---|
850 | if (mask & IFCAP_VLAN_MTU) { |
---|
851 | /* No work to do except acknowledge the change took */ |
---|
852 | ifp->if_capenable ^= IFCAP_VLAN_MTU; |
---|
853 | } |
---|
854 | break; |
---|
855 | |
---|
856 | default: |
---|
857 | error = ether_ioctl(ifp, cmd, data); |
---|
858 | break; |
---|
859 | } |
---|
860 | |
---|
861 | return (error); |
---|
862 | } |
---|
863 | |
---|
864 | static void |
---|
865 | dwc_txfinish_locked(struct dwc_softc *sc) |
---|
866 | { |
---|
867 | struct dwc_bufmap *bmap; |
---|
868 | struct dwc_hwdesc *desc; |
---|
869 | |
---|
870 | DWC_ASSERT_LOCKED(sc); |
---|
871 | |
---|
872 | while (sc->tx_idx_tail != sc->tx_idx_head) { |
---|
873 | desc = &sc->txdesc_ring[sc->tx_idx_tail]; |
---|
874 | if ((desc->tdes0 & DDESC_TDES0_OWN) != 0) |
---|
875 | break; |
---|
876 | bmap = &sc->txbuf_map[sc->tx_idx_tail]; |
---|
877 | #ifndef __rtems__ |
---|
878 | bus_dmamap_sync(sc->txbuf_tag, bmap->map, |
---|
879 | BUS_DMASYNC_POSTWRITE); |
---|
880 | bus_dmamap_unload(sc->txbuf_tag, bmap->map); |
---|
881 | #endif /* __rtems__ */ |
---|
882 | m_freem(bmap->mbuf); |
---|
883 | bmap->mbuf = NULL; |
---|
884 | --sc->txcount; |
---|
885 | sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail, 1); |
---|
886 | } |
---|
887 | |
---|
888 | sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; |
---|
889 | dwc_txstart_locked(sc); |
---|
890 | |
---|
891 | /* If there are no buffers outstanding, muzzle the watchdog. */ |
---|
892 | if (sc->tx_idx_tail == sc->tx_idx_head) { |
---|
893 | sc->tx_watchdog_count = 0; |
---|
894 | } |
---|
895 | } |
---|
896 | |
---|
897 | static void |
---|
898 | dwc_rxfinish_locked(struct dwc_softc *sc) |
---|
899 | { |
---|
900 | struct ifnet *ifp; |
---|
901 | struct mbuf *m0; |
---|
902 | struct mbuf *m; |
---|
903 | int error; |
---|
904 | uint32_t rdes0; |
---|
905 | uint32_t rdes4; |
---|
906 | int idx; |
---|
907 | int len; |
---|
908 | |
---|
909 | ifp = sc->ifp; |
---|
910 | |
---|
911 | for (;;) { |
---|
912 | idx = sc->rx_idx; |
---|
913 | |
---|
914 | rdes0 = sc->rxdesc_ring[idx].tdes0; |
---|
915 | if ((rdes0 & DDESC_RDES0_OWN) != 0) |
---|
916 | break; |
---|
917 | |
---|
918 | sc->rx_idx = next_rxidx(sc, idx); |
---|
919 | |
---|
920 | m = sc->rxbuf_map[idx].mbuf; |
---|
921 | |
---|
922 | m0 = dwc_alloc_mbufcl(sc); |
---|
923 | if (m0 == NULL) { |
---|
924 | m0 = m; |
---|
925 | |
---|
926 | /* Account for m_adj() in dwc_setup_rxbuf() */ |
---|
927 | m0->m_data = m0->m_ext.ext_buf; |
---|
928 | } |
---|
929 | |
---|
930 | if ((error = dwc_setup_rxbuf(sc, idx, m0)) != 0) { |
---|
931 | /* |
---|
932 | * XXX Now what? |
---|
933 | * We've got a hole in the rx ring. |
---|
934 | */ |
---|
935 | } |
---|
936 | |
---|
937 | if (m0 == m) { |
---|
938 | /* Discard frame and continue */ |
---|
939 | #ifndef __rtems__ |
---|
940 | if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1); |
---|
941 | #else /* __rtems__ */ |
---|
942 | ++ifp->if_iqdrops; |
---|
943 | #endif /* __rtems__ */ |
---|
944 | continue; |
---|
945 | } |
---|
946 | |
---|
947 | #ifndef __rtems__ |
---|
948 | bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, |
---|
949 | BUS_DMASYNC_POSTREAD); |
---|
950 | bus_dmamap_unload(sc->rxbuf_tag, sc->rxbuf_map[idx].map); |
---|
951 | #endif /* __rtems__ */ |
---|
952 | |
---|
953 | len = (rdes0 >> DDESC_RDES0_FL_SHIFT) & DDESC_RDES0_FL_MASK; |
---|
954 | if (len != 0) { |
---|
955 | m->m_pkthdr.rcvif = ifp; |
---|
956 | m->m_pkthdr.len = len; |
---|
957 | m->m_len = len; |
---|
958 | |
---|
959 | /* Check checksum offload flags. */ |
---|
960 | if ((rdes0 & DDESC_RDES0_ESA) != 0) { |
---|
961 | rdes4 = sc->rxdesc_ring[idx].tdes4; |
---|
962 | |
---|
963 | /* TCP or UDP checks out, IP checks out too. */ |
---|
964 | if ((rdes4 & DDESC_RDES4_IP_PYL_TYPE_MSK) == |
---|
965 | DDESC_RDES4_IP_PYL_UDP || |
---|
966 | (rdes4 & DDESC_RDES4_IP_PYL_TYPE_MSK) == |
---|
967 | DDESC_RDES4_IP_PYL_TCP) { |
---|
968 | m->m_pkthdr.csum_flags |= |
---|
969 | CSUM_IP_CHECKED | |
---|
970 | CSUM_IP_VALID | |
---|
971 | CSUM_DATA_VALID | |
---|
972 | CSUM_PSEUDO_HDR; |
---|
973 | m->m_pkthdr.csum_data = 0xffff; |
---|
974 | } else if ((rdes4 & (DDESC_RDES4_IP_PYL_ERR | |
---|
975 | DDESC_RDES4_IP_HDR_ERR)) == 0) { |
---|
976 | /* Only IP checks out. */ |
---|
977 | m->m_pkthdr.csum_flags |= |
---|
978 | CSUM_IP_CHECKED | |
---|
979 | CSUM_IP_VALID; |
---|
980 | m->m_pkthdr.csum_data = 0xffff; |
---|
981 | } |
---|
982 | } |
---|
983 | |
---|
984 | #ifndef __rtems__ |
---|
985 | if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); |
---|
986 | #else /* __rtems__ */ |
---|
987 | ++ifp->if_ipackets; |
---|
988 | rtems_cache_invalidate_multiple_data_lines(m->m_data, m->m_len); |
---|
989 | #endif /* __rtems__ */ |
---|
990 | |
---|
991 | DWC_UNLOCK(sc); |
---|
992 | (*ifp->if_input)(ifp, m); |
---|
993 | DWC_LOCK(sc); |
---|
994 | } else { |
---|
995 | /* XXX Zero-length packet ? */ |
---|
996 | } |
---|
997 | } |
---|
998 | } |
---|
999 | |
---|
1000 | static void |
---|
1001 | dwc_intr(void *arg) |
---|
1002 | { |
---|
1003 | struct dwc_softc *sc; |
---|
1004 | uint32_t reg; |
---|
1005 | |
---|
1006 | sc = arg; |
---|
1007 | |
---|
1008 | DWC_LOCK(sc); |
---|
1009 | |
---|
1010 | reg = READ4(sc, INTERRUPT_STATUS); |
---|
1011 | if (reg) { |
---|
1012 | mii_mediachg(sc->mii_softc); |
---|
1013 | READ4(sc, SGMII_RGMII_SMII_CTRL_STATUS); |
---|
1014 | } |
---|
1015 | |
---|
1016 | reg = READ4(sc, DMA_STATUS); |
---|
1017 | if (reg & DMA_STATUS_NIS) { |
---|
1018 | if (reg & DMA_STATUS_RI) |
---|
1019 | dwc_rxfinish_locked(sc); |
---|
1020 | |
---|
1021 | if (reg & DMA_STATUS_TI) |
---|
1022 | dwc_txfinish_locked(sc); |
---|
1023 | } |
---|
1024 | |
---|
1025 | if (reg & DMA_STATUS_AIS) { |
---|
1026 | if (reg & DMA_STATUS_FBI) { |
---|
1027 | /* Fatal bus error */ |
---|
1028 | device_printf(sc->dev, |
---|
1029 | "Ethernet DMA error, restarting controller.\n"); |
---|
1030 | dwc_stop_locked(sc); |
---|
1031 | dwc_init_locked(sc); |
---|
1032 | } |
---|
1033 | } |
---|
1034 | |
---|
1035 | WRITE4(sc, DMA_STATUS, reg & DMA_STATUS_INTR_MASK); |
---|
1036 | DWC_UNLOCK(sc); |
---|
1037 | } |
---|
1038 | |
---|
1039 | static int |
---|
1040 | setup_dma(struct dwc_softc *sc) |
---|
1041 | { |
---|
1042 | struct mbuf *m; |
---|
1043 | int error; |
---|
1044 | int nidx; |
---|
1045 | int idx; |
---|
1046 | |
---|
1047 | /* |
---|
1048 | * Set up TX descriptor ring, descriptors, and dma maps. |
---|
1049 | */ |
---|
1050 | error = bus_dma_tag_create( |
---|
1051 | bus_get_dma_tag(sc->dev), /* Parent tag. */ |
---|
1052 | DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */ |
---|
1053 | BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ |
---|
1054 | BUS_SPACE_MAXADDR, /* highaddr */ |
---|
1055 | NULL, NULL, /* filter, filterarg */ |
---|
1056 | TX_DESC_SIZE, 1, /* maxsize, nsegments */ |
---|
1057 | TX_DESC_SIZE, /* maxsegsize */ |
---|
1058 | 0, /* flags */ |
---|
1059 | NULL, NULL, /* lockfunc, lockarg */ |
---|
1060 | &sc->txdesc_tag); |
---|
1061 | if (error != 0) { |
---|
1062 | device_printf(sc->dev, |
---|
1063 | "could not create TX ring DMA tag.\n"); |
---|
1064 | goto out; |
---|
1065 | } |
---|
1066 | |
---|
1067 | error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring, |
---|
1068 | BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, |
---|
1069 | &sc->txdesc_map); |
---|
1070 | if (error != 0) { |
---|
1071 | device_printf(sc->dev, |
---|
1072 | "could not allocate TX descriptor ring.\n"); |
---|
1073 | goto out; |
---|
1074 | } |
---|
1075 | |
---|
1076 | #ifndef __rtems__ |
---|
1077 | error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, |
---|
1078 | sc->txdesc_ring, TX_DESC_SIZE, dwc_get1paddr, |
---|
1079 | &sc->txdesc_ring_paddr, 0); |
---|
1080 | if (error != 0) { |
---|
1081 | device_printf(sc->dev, |
---|
1082 | "could not load TX descriptor ring map.\n"); |
---|
1083 | goto out; |
---|
1084 | } |
---|
1085 | #endif /* __rtems__ */ |
---|
1086 | |
---|
1087 | for (idx = 0; idx < TX_DESC_COUNT; idx++) { |
---|
1088 | sc->txdesc_ring[idx].addr = 0; |
---|
1089 | sc->txdesc_ring[idx].tdes0 = DDESC_TDES0_TXCHAIN; |
---|
1090 | sc->txdesc_ring[idx].tdes1 = 0; |
---|
1091 | nidx = next_txidx(sc, idx, 1); |
---|
1092 | #ifndef __rtems__ |
---|
1093 | sc->txdesc_ring[idx].addr_next = sc->txdesc_ring_paddr + \ |
---|
1094 | (nidx * sizeof(struct dwc_hwdesc)); |
---|
1095 | #else /* __rtems__ */ |
---|
1096 | sc->txdesc_ring[idx].addr_next = |
---|
1097 | (uint32_t)&sc->txdesc_ring[nidx]; |
---|
1098 | #endif /* __rtems__ */ |
---|
1099 | } |
---|
1100 | |
---|
1101 | #ifndef __rtems__ |
---|
1102 | error = bus_dma_tag_create( |
---|
1103 | bus_get_dma_tag(sc->dev), /* Parent tag. */ |
---|
1104 | 1, 0, /* alignment, boundary */ |
---|
1105 | BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ |
---|
1106 | BUS_SPACE_MAXADDR, /* highaddr */ |
---|
1107 | NULL, NULL, /* filter, filterarg */ |
---|
1108 | MCLBYTES, TX_MAX_DMA_SEGS, /* maxsize, nsegments */ |
---|
1109 | MCLBYTES, /* maxsegsize */ |
---|
1110 | 0, /* flags */ |
---|
1111 | NULL, NULL, /* lockfunc, lockarg */ |
---|
1112 | &sc->txbuf_tag); |
---|
1113 | if (error != 0) { |
---|
1114 | device_printf(sc->dev, |
---|
1115 | "could not create TX ring DMA tag.\n"); |
---|
1116 | goto out; |
---|
1117 | } |
---|
1118 | #endif /* __rtems__ */ |
---|
1119 | |
---|
1120 | for (idx = 0; idx < TX_DESC_COUNT; idx++) { |
---|
1121 | #ifndef __rtems__ |
---|
1122 | error = bus_dmamap_create(sc->txbuf_tag, BUS_DMA_COHERENT, |
---|
1123 | &sc->txbuf_map[idx].map); |
---|
1124 | if (error != 0) { |
---|
1125 | device_printf(sc->dev, |
---|
1126 | "could not create TX buffer DMA map.\n"); |
---|
1127 | goto out; |
---|
1128 | } |
---|
1129 | #endif /* __rtems__ */ |
---|
1130 | } |
---|
1131 | |
---|
1132 | /* |
---|
1133 | * Set up RX descriptor ring, descriptors, dma maps, and mbufs. |
---|
1134 | */ |
---|
1135 | error = bus_dma_tag_create( |
---|
1136 | bus_get_dma_tag(sc->dev), /* Parent tag. */ |
---|
1137 | DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */ |
---|
1138 | BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ |
---|
1139 | BUS_SPACE_MAXADDR, /* highaddr */ |
---|
1140 | NULL, NULL, /* filter, filterarg */ |
---|
1141 | RX_DESC_SIZE, 1, /* maxsize, nsegments */ |
---|
1142 | RX_DESC_SIZE, /* maxsegsize */ |
---|
1143 | 0, /* flags */ |
---|
1144 | NULL, NULL, /* lockfunc, lockarg */ |
---|
1145 | &sc->rxdesc_tag); |
---|
1146 | if (error != 0) { |
---|
1147 | device_printf(sc->dev, |
---|
1148 | "could not create RX ring DMA tag.\n"); |
---|
1149 | goto out; |
---|
1150 | } |
---|
1151 | |
---|
1152 | error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring, |
---|
1153 | BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, |
---|
1154 | &sc->rxdesc_map); |
---|
1155 | if (error != 0) { |
---|
1156 | device_printf(sc->dev, |
---|
1157 | "could not allocate RX descriptor ring.\n"); |
---|
1158 | goto out; |
---|
1159 | } |
---|
1160 | |
---|
1161 | #ifndef __rtems__ |
---|
1162 | error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, |
---|
1163 | sc->rxdesc_ring, RX_DESC_SIZE, dwc_get1paddr, |
---|
1164 | &sc->rxdesc_ring_paddr, 0); |
---|
1165 | if (error != 0) { |
---|
1166 | device_printf(sc->dev, |
---|
1167 | "could not load RX descriptor ring map.\n"); |
---|
1168 | goto out; |
---|
1169 | } |
---|
1170 | |
---|
1171 | error = bus_dma_tag_create( |
---|
1172 | bus_get_dma_tag(sc->dev), /* Parent tag. */ |
---|
1173 | 1, 0, /* alignment, boundary */ |
---|
1174 | BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ |
---|
1175 | BUS_SPACE_MAXADDR, /* highaddr */ |
---|
1176 | NULL, NULL, /* filter, filterarg */ |
---|
1177 | MCLBYTES, 1, /* maxsize, nsegments */ |
---|
1178 | MCLBYTES, /* maxsegsize */ |
---|
1179 | 0, /* flags */ |
---|
1180 | NULL, NULL, /* lockfunc, lockarg */ |
---|
1181 | &sc->rxbuf_tag); |
---|
1182 | if (error != 0) { |
---|
1183 | device_printf(sc->dev, |
---|
1184 | "could not create RX buf DMA tag.\n"); |
---|
1185 | goto out; |
---|
1186 | } |
---|
1187 | #endif /* __rtems__ */ |
---|
1188 | |
---|
1189 | for (idx = 0; idx < RX_DESC_COUNT; idx++) { |
---|
1190 | #ifndef __rtems__ |
---|
1191 | error = bus_dmamap_create(sc->rxbuf_tag, BUS_DMA_COHERENT, |
---|
1192 | &sc->rxbuf_map[idx].map); |
---|
1193 | if (error != 0) { |
---|
1194 | device_printf(sc->dev, |
---|
1195 | "could not create RX buffer DMA map.\n"); |
---|
1196 | goto out; |
---|
1197 | } |
---|
1198 | #endif /* __rtems__ */ |
---|
1199 | if ((m = dwc_alloc_mbufcl(sc)) == NULL) { |
---|
1200 | device_printf(sc->dev, "Could not alloc mbuf\n"); |
---|
1201 | error = ENOMEM; |
---|
1202 | goto out; |
---|
1203 | } |
---|
1204 | if ((error = dwc_setup_rxbuf(sc, idx, m)) != 0) { |
---|
1205 | device_printf(sc->dev, |
---|
1206 | "could not create new RX buffer.\n"); |
---|
1207 | goto out; |
---|
1208 | } |
---|
1209 | sc->rxdesc_ring[idx].tdes4 = 0; |
---|
1210 | } |
---|
1211 | |
---|
1212 | out: |
---|
1213 | if (error != 0) |
---|
1214 | return (ENXIO); |
---|
1215 | |
---|
1216 | return (0); |
---|
1217 | } |
---|
1218 | |
---|
1219 | static int |
---|
1220 | dwc_get_hwaddr(struct dwc_softc *sc, uint8_t *hwaddr) |
---|
1221 | { |
---|
1222 | #ifndef __rtems__ |
---|
1223 | int rnd; |
---|
1224 | #endif /* __rtems__ */ |
---|
1225 | int lo; |
---|
1226 | int hi; |
---|
1227 | |
---|
1228 | /* |
---|
1229 | * Try to recover a MAC address from the running hardware. If there's |
---|
1230 | * something non-zero there, assume the bootloader did the right thing |
---|
1231 | * and just use it. |
---|
1232 | * |
---|
1233 | * Otherwise, set the address to a convenient locally assigned address, |
---|
1234 | * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally |
---|
1235 | * assigned bit set, and the broadcast/multicast bit clear. |
---|
1236 | */ |
---|
1237 | lo = READ4(sc, MAC_ADDRESS_LOW(0)); |
---|
1238 | hi = READ4(sc, MAC_ADDRESS_HIGH(0)) & 0xffff; |
---|
1239 | if ((lo != 0xffffffff) || (hi != 0xffff)) { |
---|
1240 | hwaddr[0] = (lo >> 0) & 0xff; |
---|
1241 | hwaddr[1] = (lo >> 8) & 0xff; |
---|
1242 | hwaddr[2] = (lo >> 16) & 0xff; |
---|
1243 | hwaddr[3] = (lo >> 24) & 0xff; |
---|
1244 | hwaddr[4] = (hi >> 0) & 0xff; |
---|
1245 | hwaddr[5] = (hi >> 8) & 0xff; |
---|
1246 | } else { |
---|
1247 | #ifndef __rtems__ |
---|
1248 | rnd = arc4random() & 0x00ffffff; |
---|
1249 | hwaddr[0] = 'b'; |
---|
1250 | hwaddr[1] = 's'; |
---|
1251 | hwaddr[2] = 'd'; |
---|
1252 | hwaddr[3] = rnd >> 16; |
---|
1253 | hwaddr[4] = rnd >> 8; |
---|
1254 | hwaddr[5] = rnd >> 0; |
---|
1255 | #else /* __rtems__ */ |
---|
1256 | rtems_bsd_get_mac_address(device_get_name(sc->dev), |
---|
1257 | device_get_unit(sc->dev), hwaddr); |
---|
1258 | #endif /* __rtems__ */ |
---|
1259 | } |
---|
1260 | |
---|
1261 | return (0); |
---|
1262 | } |
---|
1263 | |
---|
1264 | static int |
---|
1265 | dwc_probe(device_t dev) |
---|
1266 | { |
---|
1267 | |
---|
1268 | #ifndef __rtems__ |
---|
1269 | if (!ofw_bus_status_okay(dev)) |
---|
1270 | return (ENXIO); |
---|
1271 | |
---|
1272 | if (!ofw_bus_is_compatible(dev, "snps,dwmac")) |
---|
1273 | return (ENXIO); |
---|
1274 | #endif /* __rtems__ */ |
---|
1275 | |
---|
1276 | device_set_desc(dev, "Gigabit Ethernet Controller"); |
---|
1277 | return (BUS_PROBE_DEFAULT); |
---|
1278 | } |
---|
1279 | |
---|
1280 | static int |
---|
1281 | dwc_attach(device_t dev) |
---|
1282 | { |
---|
1283 | uint8_t macaddr[ETHER_ADDR_LEN]; |
---|
1284 | struct dwc_softc *sc; |
---|
1285 | struct ifnet *ifp; |
---|
1286 | int error; |
---|
1287 | int reg; |
---|
1288 | int i; |
---|
1289 | |
---|
1290 | sc = device_get_softc(dev); |
---|
1291 | sc->dev = dev; |
---|
1292 | sc->mii_clk = MII_CLK_VAL; |
---|
1293 | sc->rx_idx = 0; |
---|
1294 | sc->txcount = 0; |
---|
1295 | |
---|
1296 | if (bus_alloc_resources(dev, dwc_spec, sc->res)) { |
---|
1297 | device_printf(dev, "could not allocate resources\n"); |
---|
1298 | return (ENXIO); |
---|
1299 | } |
---|
1300 | |
---|
1301 | /* Memory interface */ |
---|
1302 | sc->bst = rman_get_bustag(sc->res[0]); |
---|
1303 | sc->bsh = rman_get_bushandle(sc->res[0]); |
---|
1304 | |
---|
1305 | /* Read MAC before reset */ |
---|
1306 | if (dwc_get_hwaddr(sc, macaddr)) { |
---|
1307 | device_printf(sc->dev, "can't get mac\n"); |
---|
1308 | return (ENXIO); |
---|
1309 | } |
---|
1310 | |
---|
1311 | /* Reset */ |
---|
1312 | reg = READ4(sc, BUS_MODE); |
---|
1313 | reg |= (BUS_MODE_SWR); |
---|
1314 | WRITE4(sc, BUS_MODE, reg); |
---|
1315 | |
---|
1316 | for (i = 0; i < MAC_RESET_TIMEOUT; i++) { |
---|
1317 | if ((READ4(sc, BUS_MODE) & BUS_MODE_SWR) == 0) |
---|
1318 | break; |
---|
1319 | DELAY(10); |
---|
1320 | } |
---|
1321 | if (i >= MAC_RESET_TIMEOUT) { |
---|
1322 | device_printf(sc->dev, "Can't reset DWC.\n"); |
---|
1323 | return (ENXIO); |
---|
1324 | } |
---|
1325 | |
---|
1326 | reg = READ4(sc, BUS_MODE); |
---|
1327 | reg |= (BUS_MODE_ATDS); |
---|
1328 | reg |= (BUS_MODE_EIGHTXPBL); |
---|
1329 | reg |= (BUS_MODE_PBL_BEATS_8 << BUS_MODE_PBL_SHIFT); |
---|
1330 | WRITE4(sc, BUS_MODE, reg); |
---|
1331 | |
---|
1332 | /* |
---|
1333 | * DMA must be stop while changing descriptor list addresses. |
---|
1334 | */ |
---|
1335 | reg = READ4(sc, OPERATION_MODE); |
---|
1336 | reg &= ~(MODE_ST | MODE_SR); |
---|
1337 | WRITE4(sc, OPERATION_MODE, reg); |
---|
1338 | |
---|
1339 | if (setup_dma(sc)) |
---|
1340 | return (ENXIO); |
---|
1341 | |
---|
1342 | /* Setup addresses */ |
---|
1343 | #ifndef __rtems__ |
---|
1344 | WRITE4(sc, RX_DESCR_LIST_ADDR, sc->rxdesc_ring_paddr); |
---|
1345 | WRITE4(sc, TX_DESCR_LIST_ADDR, sc->txdesc_ring_paddr); |
---|
1346 | #else /* __rtems__ */ |
---|
1347 | WRITE4(sc, RX_DESCR_LIST_ADDR, (uint32_t)&sc->rxdesc_ring[0]); |
---|
1348 | WRITE4(sc, TX_DESCR_LIST_ADDR, (uint32_t)&sc->txdesc_ring[0]); |
---|
1349 | #endif /* __rtems__ */ |
---|
1350 | |
---|
1351 | mtx_init(&sc->mtx, device_get_nameunit(sc->dev), |
---|
1352 | MTX_NETWORK_LOCK, MTX_DEF); |
---|
1353 | |
---|
1354 | callout_init_mtx(&sc->dwc_callout, &sc->mtx, 0); |
---|
1355 | |
---|
1356 | /* Set up the ethernet interface. */ |
---|
1357 | sc->ifp = ifp = if_alloc(IFT_ETHER); |
---|
1358 | |
---|
1359 | ifp->if_softc = sc; |
---|
1360 | if_initname(ifp, device_get_name(dev), device_get_unit(dev)); |
---|
1361 | ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; |
---|
1362 | ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6 | |
---|
1363 | IFCAP_VLAN_MTU | IFCAP_VLAN_HWCSUM; |
---|
1364 | ifp->if_capenable = ifp->if_capabilities; |
---|
1365 | ifp->if_hwassist = DWC_CKSUM_ASSIST; |
---|
1366 | ifp->if_start = dwc_txstart; |
---|
1367 | ifp->if_ioctl = dwc_ioctl; |
---|
1368 | ifp->if_init = dwc_init; |
---|
1369 | IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1); |
---|
1370 | ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1; |
---|
1371 | IFQ_SET_READY(&ifp->if_snd); |
---|
1372 | ifp->if_hdrlen = sizeof(struct ether_vlan_header); |
---|
1373 | |
---|
1374 | /* Attach the mii driver. */ |
---|
1375 | error = mii_attach(dev, &sc->miibus, ifp, dwc_media_change, |
---|
1376 | dwc_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, |
---|
1377 | MII_OFFSET_ANY, 0); |
---|
1378 | |
---|
1379 | if (error != 0) { |
---|
1380 | device_printf(dev, "PHY attach failed\n"); |
---|
1381 | return (ENXIO); |
---|
1382 | } |
---|
1383 | sc->mii_softc = device_get_softc(sc->miibus); |
---|
1384 | |
---|
1385 | /* Setup interrupt handler. */ |
---|
1386 | error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE, |
---|
1387 | NULL, dwc_intr, sc, &sc->intr_cookie); |
---|
1388 | if (error != 0) { |
---|
1389 | device_printf(dev, "could not setup interrupt handler.\n"); |
---|
1390 | return (ENXIO); |
---|
1391 | } |
---|
1392 | |
---|
1393 | /* All ready to run, attach the ethernet interface. */ |
---|
1394 | ether_ifattach(ifp, macaddr); |
---|
1395 | sc->is_attached = true; |
---|
1396 | |
---|
1397 | return (0); |
---|
1398 | } |
---|
1399 | |
---|
1400 | static int |
---|
1401 | dwc_miibus_read_reg(device_t dev, int phy, int reg) |
---|
1402 | { |
---|
1403 | struct dwc_softc *sc; |
---|
1404 | uint16_t mii; |
---|
1405 | size_t cnt; |
---|
1406 | int rv = 0; |
---|
1407 | |
---|
1408 | sc = device_get_softc(dev); |
---|
1409 | |
---|
1410 | mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT) |
---|
1411 | | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT) |
---|
1412 | | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT) |
---|
1413 | | GMII_ADDRESS_GB; /* Busy flag */ |
---|
1414 | |
---|
1415 | WRITE4(sc, GMII_ADDRESS, mii); |
---|
1416 | |
---|
1417 | for (cnt = 0; cnt < 1000; cnt++) { |
---|
1418 | if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) { |
---|
1419 | rv = READ4(sc, GMII_DATA); |
---|
1420 | break; |
---|
1421 | } |
---|
1422 | DELAY(10); |
---|
1423 | } |
---|
1424 | |
---|
1425 | return rv; |
---|
1426 | } |
---|
1427 | |
---|
1428 | static int |
---|
1429 | dwc_miibus_write_reg(device_t dev, int phy, int reg, int val) |
---|
1430 | { |
---|
1431 | struct dwc_softc *sc; |
---|
1432 | uint16_t mii; |
---|
1433 | size_t cnt; |
---|
1434 | |
---|
1435 | sc = device_get_softc(dev); |
---|
1436 | |
---|
1437 | mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT) |
---|
1438 | | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT) |
---|
1439 | | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT) |
---|
1440 | | GMII_ADDRESS_GB | GMII_ADDRESS_GW; |
---|
1441 | |
---|
1442 | WRITE4(sc, GMII_DATA, val); |
---|
1443 | WRITE4(sc, GMII_ADDRESS, mii); |
---|
1444 | |
---|
1445 | for (cnt = 0; cnt < 1000; cnt++) { |
---|
1446 | if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) { |
---|
1447 | break; |
---|
1448 | } |
---|
1449 | DELAY(10); |
---|
1450 | } |
---|
1451 | |
---|
1452 | return (0); |
---|
1453 | } |
---|
1454 | |
---|
1455 | static void |
---|
1456 | dwc_miibus_statchg(device_t dev) |
---|
1457 | { |
---|
1458 | struct dwc_softc *sc; |
---|
1459 | struct mii_data *mii; |
---|
1460 | int reg; |
---|
1461 | |
---|
1462 | /* |
---|
1463 | * Called by the MII bus driver when the PHY establishes |
---|
1464 | * link to set the MAC interface registers. |
---|
1465 | */ |
---|
1466 | |
---|
1467 | sc = device_get_softc(dev); |
---|
1468 | |
---|
1469 | DWC_ASSERT_LOCKED(sc); |
---|
1470 | |
---|
1471 | mii = sc->mii_softc; |
---|
1472 | |
---|
1473 | if (mii->mii_media_status & IFM_ACTIVE) |
---|
1474 | sc->link_is_up = true; |
---|
1475 | else |
---|
1476 | sc->link_is_up = false; |
---|
1477 | |
---|
1478 | reg = READ4(sc, MAC_CONFIGURATION); |
---|
1479 | switch (IFM_SUBTYPE(mii->mii_media_active)) { |
---|
1480 | case IFM_1000_T: |
---|
1481 | case IFM_1000_SX: |
---|
1482 | reg &= ~(CONF_FES | CONF_PS); |
---|
1483 | break; |
---|
1484 | case IFM_100_TX: |
---|
1485 | reg |= (CONF_FES | CONF_PS); |
---|
1486 | break; |
---|
1487 | case IFM_10_T: |
---|
1488 | reg &= ~(CONF_FES); |
---|
1489 | reg |= (CONF_PS); |
---|
1490 | break; |
---|
1491 | case IFM_NONE: |
---|
1492 | sc->link_is_up = false; |
---|
1493 | return; |
---|
1494 | default: |
---|
1495 | sc->link_is_up = false; |
---|
1496 | device_printf(dev, "Unsupported media %u\n", |
---|
1497 | IFM_SUBTYPE(mii->mii_media_active)); |
---|
1498 | return; |
---|
1499 | } |
---|
1500 | if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) |
---|
1501 | reg |= (CONF_DM); |
---|
1502 | else |
---|
1503 | reg &= ~(CONF_DM); |
---|
1504 | WRITE4(sc, MAC_CONFIGURATION, reg); |
---|
1505 | } |
---|
1506 | |
---|
1507 | static device_method_t dwc_methods[] = { |
---|
1508 | DEVMETHOD(device_probe, dwc_probe), |
---|
1509 | DEVMETHOD(device_attach, dwc_attach), |
---|
1510 | |
---|
1511 | /* MII Interface */ |
---|
1512 | DEVMETHOD(miibus_readreg, dwc_miibus_read_reg), |
---|
1513 | DEVMETHOD(miibus_writereg, dwc_miibus_write_reg), |
---|
1514 | DEVMETHOD(miibus_statchg, dwc_miibus_statchg), |
---|
1515 | |
---|
1516 | { 0, 0 } |
---|
1517 | }; |
---|
1518 | |
---|
1519 | static driver_t dwc_driver = { |
---|
1520 | "dwc", |
---|
1521 | dwc_methods, |
---|
1522 | sizeof(struct dwc_softc), |
---|
1523 | }; |
---|
1524 | |
---|
1525 | static devclass_t dwc_devclass; |
---|
1526 | |
---|
1527 | #ifndef __rtems__ |
---|
1528 | DRIVER_MODULE(dwc, simplebus, dwc_driver, dwc_devclass, 0, 0); |
---|
1529 | #else /* __rtems__ */ |
---|
1530 | DRIVER_MODULE(dwc, nexus, dwc_driver, dwc_devclass, 0, 0); |
---|
1531 | #endif /* __rtems__ */ |
---|
1532 | DRIVER_MODULE(miibus, dwc, miibus_driver, miibus_devclass, 0, 0); |
---|
1533 | |
---|
1534 | MODULE_DEPEND(dwc, ether, 1, 1, 1); |
---|
1535 | MODULE_DEPEND(dwc, miibus, 1, 1, 1); |
---|