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source: rtems-libbsd/freebsd/sys/dev/dwc/if_dwc.c @ d5ad68a

4.1155-freebsd-126-freebsd-12freebsd-9.3

Last change on this file since d5ad68a was d5ad68a, checked in by Sebastian Huber <sebastian.huber@…>, on 03/27/15 at 10:14:44
if_dwc: Move interrupt handler install
Property mode set to `100644`
File size: 32.0 KB

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1	#include <machine/rtems-bsd-kernel-space.h>
2
3	/*-
4	* Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
5	* All rights reserved.
6	*
7	* This software was developed by SRI International and the University of
8	* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
9	* ("CTSRD"), as part of the DARPA CRASH research programme.
10	*
11	* Redistribution and use in source and binary forms, with or without
12	* modification, are permitted provided that the following conditions
13	* are met:
14	* 1. Redistributions of source code must retain the above copyright
15	* notice, this list of conditions and the following disclaimer.
16	* 2. Redistributions in binary form must reproduce the above copyright
17	* notice, this list of conditions and the following disclaimer in the
18	* documentation and/or other materials provided with the distribution.
19	*
20	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30	* SUCH DAMAGE.
31	*/
32
33	/*
34	* Ethernet media access controller (EMAC)
35	* Chapter 17, Altera Cyclone V Device Handbook (CV-5V2 2014.07.22)
36	*
37	* EMAC is an instance of the Synopsys DesignWare 3504-0
38	* Universal 10/100/1000 Ethernet MAC (DWC_gmac).
39	*/
40
41	#include <sys/cdefs.h>
42	__FBSDID("$FreeBSD$");
43
44	#include <rtems/bsd/sys/param.h>
45	#include <sys/systm.h>
46	#include <sys/bus.h>
47	#include <sys/kernel.h>
48	#include <sys/module.h>
49	#include <sys/malloc.h>
50	#include <sys/rman.h>
51	#include <sys/endian.h>
52	#include <rtems/bsd/sys/lock.h>
53	#include <sys/mbuf.h>
54	#include <sys/mutex.h>
55	#include <sys/socket.h>
56	#include <sys/sockio.h>
57	#include <sys/sysctl.h>
58
59	#ifndef __rtems__
60	#include <dev/fdt/fdt_common.h>
61	#include <dev/ofw/openfirm.h>
62	#include <dev/ofw/ofw_bus.h>
63	#include <dev/ofw/ofw_bus_subr.h>
64	#endif /* __rtems__ */
65
66	#include <net/bpf.h>
67	#include <net/if.h>
68	#include <net/ethernet.h>
69	#include <net/if_dl.h>
70	#include <net/if_media.h>
71	#include <net/if_types.h>
72	#include <net/if_var.h>
73	#include <net/if_vlan_var.h>
74
75	#include <machine/bus.h>
76	#ifndef __rtems__
77	#include <machine/fdt.h>
78	#endif /* __rtems__ */
79
80	#include <dev/mii/mii.h>
81	#include <dev/mii/miivar.h>
82	#include <rtems/bsd/local/miibus_if.h>
83	#ifdef __rtems__
84	#pragma GCC diagnostic ignored "-Wpointer-sign"
85	#include <rtems/bsd/bsd.h>
86	#endif /* __rtems__ */
87
88	#define READ4(_sc, _reg) \
89	bus_read_4((_sc)->res[0], _reg)
90	#define WRITE4(_sc, _reg, _val) \
91	bus_write_4((_sc)->res[0], _reg, _val)
92
93	#define MAC_RESET_TIMEOUT 100
94	#define WATCHDOG_TIMEOUT_SECS 5
95	#define STATS_HARVEST_INTERVAL 2
96	#define MII_CLK_VAL 2
97
98	#include <dev/dwc/if_dwc.h>
99
100	#define DWC_LOCK(sc) mtx_lock(&(sc)->mtx)
101	#define DWC_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
102	#define DWC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED);
103	#define DWC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED);
104
105	#define DDESC_TDES0_OWN (1 << 31)
106	#define DDESC_TDES0_TXINT (1 << 30)
107	#define DDESC_TDES0_TXLAST (1 << 29)
108	#define DDESC_TDES0_TXFIRST (1 << 28)
109	#define DDESC_TDES0_TXCRCDIS (1 << 27)
110	#define DDESC_TDES0_TXRINGEND (1 << 21)
111	#define DDESC_TDES0_TXCHAIN (1 << 20)
112
113	#define DDESC_RDES0_OWN (1 << 31)
114	#define DDESC_RDES0_FL_MASK 0x3fff
115	#define DDESC_RDES0_FL_SHIFT 16 /* Frame Length */
116	#define DDESC_RDES1_CHAINED (1 << 14)
117
118	struct dwc_bufmap {
119	bus_dmamap_t map;
120	struct mbuf *mbuf;
121	};
122
123	/*
124	* A hardware buffer descriptor. Rx and Tx buffers have the same descriptor
125	* layout, but the bits in the flags field have different meanings.
126	*/
127	struct dwc_hwdesc
128	{
129	uint32_t tdes0;
130	uint32_t tdes1;
131	uint32_t addr; /* pointer to buffer data */
132	uint32_t addr_next; /* link to next descriptor */
133	};
134
135	/*
136	* Driver data and defines.
137	*/
138	#ifndef __rtems__
139	#define RX_DESC_COUNT 1024
140	#else /* __rtems__ */
141	#define RX_DESC_COUNT 64
142	#endif /* __rtems__ */
143	#define RX_DESC_SIZE (sizeof(struct dwc_hwdesc) * RX_DESC_COUNT)
144	#ifndef __rtems__
145	#define TX_DESC_COUNT 1024
146	#else /* __rtems__ */
147	#define TX_DESC_COUNT 64
148	#endif /* __rtems__ */
149	#define TX_DESC_SIZE (sizeof(struct dwc_hwdesc) * TX_DESC_COUNT)
150
151	/*
152	* The hardware imposes alignment restrictions on various objects involved in
153	* DMA transfers. These values are expressed in bytes (not bits).
154	*/
155	#define DWC_DESC_RING_ALIGN 2048
156
157	struct dwc_softc {
158	struct resource *res[2];
159	bus_space_tag_t bst;
160	bus_space_handle_t bsh;
161	device_t dev;
162	int mii_clk;
163	device_t miibus;
164	struct mii_data * mii_softc;
165	struct ifnet *ifp;
166	int if_flags;
167	struct mtx mtx;
168	void * intr_cookie;
169	struct callout dwc_callout;
170	uint8_t phy_conn_type;
171	uint8_t mactype;
172	boolean_t link_is_up;
173	boolean_t is_attached;
174	boolean_t is_detaching;
175	int tx_watchdog_count;
176	int stats_harvest_count;
177
178	/* RX */
179	bus_dma_tag_t rxdesc_tag;
180	bus_dmamap_t rxdesc_map;
181	struct dwc_hwdesc *rxdesc_ring;
182	bus_addr_t rxdesc_ring_paddr;
183	bus_dma_tag_t rxbuf_tag;
184	struct dwc_bufmap rxbuf_map[RX_DESC_COUNT];
185	uint32_t rx_idx;
186
187	/* TX */
188	bus_dma_tag_t txdesc_tag;
189	bus_dmamap_t txdesc_map;
190	struct dwc_hwdesc *txdesc_ring;
191	bus_addr_t txdesc_ring_paddr;
192	bus_dma_tag_t txbuf_tag;
193	struct dwc_bufmap txbuf_map[RX_DESC_COUNT];
194	uint32_t tx_idx_head;
195	uint32_t tx_idx_tail;
196	int txcount;
197	};
198
199	static struct resource_spec dwc_spec[] = {
200	{ SYS_RES_MEMORY, 0, RF_ACTIVE },
201	{ SYS_RES_IRQ, 0, RF_ACTIVE },
202	{ -1, 0 }
203	};
204
205	static void dwc_txfinish_locked(struct dwc_softc *sc);
206	static void dwc_rxfinish_locked(struct dwc_softc *sc);
207	static void dwc_stop_locked(struct dwc_softc *sc);
208	static void dwc_setup_rxfilter(struct dwc_softc *sc);
209
210	static inline uint32_t
211	next_rxidx(struct dwc_softc *sc, uint32_t curidx)
212	{
213
214	return ((curidx + 1) % RX_DESC_COUNT);
215	}
216
217	static inline uint32_t
218	next_txidx(struct dwc_softc *sc, uint32_t curidx)
219	{
220
221	return ((curidx + 1) % TX_DESC_COUNT);
222	}
223
224	static void
225	dwc_get1paddr(void arg, bus_dma_segment_t segs, int nsegs, int error)
226	{
227
228	if (error != 0)
229	return;
230	(bus_addr_t )arg = segs[0].ds_addr;
231	}
232
233	inline static uint32_t
234	dwc_setup_txdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr,
235	uint32_t len)
236	{
237	uint32_t flags;
238	uint32_t nidx;
239
240	nidx = next_txidx(sc, idx);
241
242	/* Addr/len 0 means we're clearing the descriptor after xmit done. */
243	if (paddr == 0 \|\| len == 0) {
244	flags = 0;
245	--sc->txcount;
246	} else {
247	flags = DDESC_TDES0_TXCHAIN \| DDESC_TDES0_TXFIRST
248	\| DDESC_TDES0_TXLAST \| DDESC_TDES0_TXINT;
249	++sc->txcount;
250	}
251
252	sc->txdesc_ring[idx].addr = (uint32_t)(paddr);
253	sc->txdesc_ring[idx].tdes0 = flags;
254	sc->txdesc_ring[idx].tdes1 = len;
255
256	if (paddr && len) {
257	wmb();
258	sc->txdesc_ring[idx].tdes0 \|= DDESC_TDES0_OWN;
259	wmb();
260	}
261
262	return (nidx);
263	}
264
265	static int
266	dwc_setup_txbuf(struct dwc_softc sc, int idx, struct mbuf *mp)
267	{
268	struct bus_dma_segment seg;
269	int error, nsegs;
270	struct mbuf * m;
271
272	if ((m = m_defrag(*mp, M_NOWAIT)) == NULL)
273	return (ENOMEM);
274	*mp = m;
275
276	error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map,
277	m, &seg, &nsegs, 0);
278	if (error != 0) {
279	return (ENOMEM);
280	}
281
282	KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
283
284	bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map,
285	BUS_DMASYNC_PREWRITE);
286
287	sc->txbuf_map[idx].mbuf = m;
288
289	dwc_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len);
290
291	return (0);
292	}
293
294	static void
295	dwc_txstart_locked(struct dwc_softc *sc)
296	{
297	struct ifnet *ifp;
298	struct mbuf *m;
299	int enqueued;
300
301	DWC_ASSERT_LOCKED(sc);
302
303	if (!sc->link_is_up)
304	return;
305
306	ifp = sc->ifp;
307
308	if (ifp->if_drv_flags & IFF_DRV_OACTIVE) {
309	return;
310	}
311
312	enqueued = 0;
313
314	for (;;) {
315	if (sc->txcount == (TX_DESC_COUNT-1)) {
316	ifp->if_drv_flags \|= IFF_DRV_OACTIVE;
317	break;
318	}
319
320	IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
321	if (m == NULL)
322	break;
323	if (dwc_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) {
324	IFQ_DRV_PREPEND(&ifp->if_snd, m);
325	break;
326	}
327	BPF_MTAP(ifp, m);
328	sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head);
329	++enqueued;
330	}
331
332	if (enqueued != 0) {
333	WRITE4(sc, TRANSMIT_POLL_DEMAND, 0x1);
334	sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS;
335	}
336	}
337
338	static void
339	dwc_txstart(struct ifnet *ifp)
340	{
341	struct dwc_softc *sc = ifp->if_softc;
342
343	DWC_LOCK(sc);
344	dwc_txstart_locked(sc);
345	DWC_UNLOCK(sc);
346	}
347
348	static void
349	dwc_stop_locked(struct dwc_softc *sc)
350	{
351	struct ifnet *ifp;
352	int reg;
353
354	DWC_ASSERT_LOCKED(sc);
355
356	ifp = sc->ifp;
357	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING \| IFF_DRV_OACTIVE);
358	sc->tx_watchdog_count = 0;
359	sc->stats_harvest_count = 0;
360
361	callout_stop(&sc->dwc_callout);
362
363	/* Stop DMA TX */
364	reg = READ4(sc, OPERATION_MODE);
365	reg &= ~(MODE_ST);
366	WRITE4(sc, OPERATION_MODE, reg);
367
368	/* Flush TX */
369	reg = READ4(sc, OPERATION_MODE);
370	reg \|= (MODE_FTF);
371	WRITE4(sc, OPERATION_MODE, reg);
372
373	/* Stop transmitters */
374	reg = READ4(sc, MAC_CONFIGURATION);
375	reg &= ~(CONF_TE \| CONF_RE);
376	WRITE4(sc, MAC_CONFIGURATION, reg);
377
378	/* Stop DMA RX */
379	reg = READ4(sc, OPERATION_MODE);
380	reg &= ~(MODE_SR);
381	WRITE4(sc, OPERATION_MODE, reg);
382	}
383
384	static void dwc_clear_stats(struct dwc_softc *sc)
385	{
386	int reg;
387
388	reg = READ4(sc, MMC_CONTROL);
389	reg \|= (MMC_CONTROL_CNTRST);
390	WRITE4(sc, MMC_CONTROL, reg);
391	}
392
393	static void
394	dwc_harvest_stats(struct dwc_softc *sc)
395	{
396	struct ifnet *ifp;
397
398	/* We don't need to harvest too often. */
399	if (++sc->stats_harvest_count < STATS_HARVEST_INTERVAL)
400	return;
401
402	sc->stats_harvest_count = 0;
403	ifp = sc->ifp;
404
405	#ifndef __rtems__
406	if_inc_counter(ifp, IFCOUNTER_IPACKETS, READ4(sc, RXFRAMECOUNT_GB));
407	if_inc_counter(ifp, IFCOUNTER_IMCASTS, READ4(sc, RXMULTICASTFRAMES_G));
408	if_inc_counter(ifp, IFCOUNTER_IERRORS,
409	READ4(sc, RXOVERSIZE_G) + READ4(sc, RXUNDERSIZE_G) +
410	READ4(sc, RXCRCERROR) + READ4(sc, RXALIGNMENTERROR) +
411	READ4(sc, RXRUNTERROR) + READ4(sc, RXJABBERERROR) +
412	READ4(sc, RXLENGTHERROR));
413
414	if_inc_counter(ifp, IFCOUNTER_OPACKETS, READ4(sc, TXFRAMECOUNT_G));
415	if_inc_counter(ifp, IFCOUNTER_OMCASTS, READ4(sc, TXMULTICASTFRAMES_G));
416	if_inc_counter(ifp, IFCOUNTER_OERRORS,
417	READ4(sc, TXOVERSIZE_G) + READ4(sc, TXEXCESSDEF) +
418	READ4(sc, TXCARRIERERR) + READ4(sc, TXUNDERFLOWERROR));
419
420	if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
421	READ4(sc, TXEXESSCOL) + READ4(sc, TXLATECOL));
422	#else /* __rtems__ */
423	ifp->if_ipackets += READ4(sc, RXFRAMECOUNT_GB);
424	ifp->if_imcasts += READ4(sc, RXMULTICASTFRAMES_G);
425	ifp->if_ierrors +=
426	READ4(sc, RXOVERSIZE_G) + READ4(sc, RXUNDERSIZE_G) +
427	READ4(sc, RXCRCERROR) + READ4(sc, RXALIGNMENTERROR) +
428	READ4(sc, RXRUNTERROR) + READ4(sc, RXJABBERERROR) +
429	READ4(sc, RXLENGTHERROR);
430
431	ifp->if_opackets += READ4(sc, TXFRAMECOUNT_G);
432	ifp->if_omcasts += READ4(sc, TXMULTICASTFRAMES_G);
433	ifp->if_oerrors +=
434	READ4(sc, TXOVERSIZE_G) + READ4(sc, TXEXCESSDEF) +
435	READ4(sc, TXCARRIERERR) + READ4(sc, TXUNDERFLOWERROR);
436
437	ifp->if_collisions +=
438	READ4(sc, TXEXESSCOL) + READ4(sc, TXLATECOL);
439	#endif /* __rtems__ */
440
441	dwc_clear_stats(sc);
442	}
443
444	static void
445	dwc_tick(void *arg)
446	{
447	struct dwc_softc *sc;
448	struct ifnet *ifp;
449	int link_was_up;
450
451	sc = arg;
452
453	DWC_ASSERT_LOCKED(sc);
454
455	ifp = sc->ifp;
456
457	if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
458	return;
459
460	/*
461	* Typical tx watchdog. If this fires it indicates that we enqueued
462	* packets for output and never got a txdone interrupt for them. Maybe
463	* it's a missed interrupt somehow, just pretend we got one.
464	*/
465	if (sc->tx_watchdog_count > 0) {
466	if (--sc->tx_watchdog_count == 0) {
467	dwc_txfinish_locked(sc);
468	}
469	}
470
471	/* Gather stats from hardware counters. */
472	dwc_harvest_stats(sc);
473
474	/* Check the media status. */
475	link_was_up = sc->link_is_up;
476	mii_tick(sc->mii_softc);
477	if (sc->link_is_up && !link_was_up)
478	dwc_txstart_locked(sc);
479
480	/* Schedule another check one second from now. */
481	callout_reset(&sc->dwc_callout, hz, dwc_tick, sc);
482	}
483
484	static void
485	dwc_init_locked(struct dwc_softc *sc)
486	{
487	struct ifnet *ifp = sc->ifp;
488	int reg;
489
490	DWC_ASSERT_LOCKED(sc);
491
492	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
493	return;
494
495	ifp->if_drv_flags \|= IFF_DRV_RUNNING;
496
497	dwc_setup_rxfilter(sc);
498
499	/* Initializa DMA and enable transmitters */
500	reg = READ4(sc, OPERATION_MODE);
501	reg \|= (MODE_TSF \| MODE_OSF \| MODE_FUF);
502	reg &= ~(MODE_RSF);
503	reg \|= (MODE_RTC_LEV32 << MODE_RTC_SHIFT);
504	WRITE4(sc, OPERATION_MODE, reg);
505
506	WRITE4(sc, INTERRUPT_ENABLE, INT_EN_DEFAULT);
507
508	/* Start DMA */
509	reg = READ4(sc, OPERATION_MODE);
510	reg \|= (MODE_ST \| MODE_SR);
511	WRITE4(sc, OPERATION_MODE, reg);
512
513	/* Enable transmitters */
514	reg = READ4(sc, MAC_CONFIGURATION);
515	reg \|= (CONF_JD \| CONF_ACS \| CONF_BE);
516	reg \|= (CONF_TE \| CONF_RE);
517	WRITE4(sc, MAC_CONFIGURATION, reg);
518
519	/*
520	* Call mii_mediachg() which will call back into dwc_miibus_statchg()
521	* to set up the remaining config registers based on current media.
522	*/
523	mii_mediachg(sc->mii_softc);
524	callout_reset(&sc->dwc_callout, hz, dwc_tick, sc);
525	}
526
527	static void
528	dwc_init(void *if_softc)
529	{
530	struct dwc_softc *sc = if_softc;
531
532	DWC_LOCK(sc);
533	dwc_init_locked(sc);
534	DWC_UNLOCK(sc);
535	}
536
537	inline static uint32_t
538	dwc_setup_rxdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr)
539	{
540	uint32_t nidx;
541
542	sc->rxdesc_ring[idx].addr = (uint32_t)paddr;
543	nidx = next_rxidx(sc, idx);
544	sc->rxdesc_ring[idx].addr_next = sc->rxdesc_ring_paddr + \
545	(nidx * sizeof(struct dwc_hwdesc));
546	sc->rxdesc_ring[idx].tdes1 = DDESC_RDES1_CHAINED \| MCLBYTES;
547
548	wmb();
549	sc->rxdesc_ring[idx].tdes0 = DDESC_RDES0_OWN;
550	wmb();
551
552	return (nidx);
553	}
554
555	static int
556	dwc_setup_rxbuf(struct dwc_softc sc, int idx, struct mbuf m)
557	{
558	struct bus_dma_segment seg;
559	int error, nsegs;
560
561	m_adj(m, ETHER_ALIGN);
562
563	error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
564	m, &seg, &nsegs, 0);
565	if (error != 0) {
566	return (error);
567	}
568
569	KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
570
571	bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
572	BUS_DMASYNC_PREREAD);
573
574	sc->rxbuf_map[idx].mbuf = m;
575	dwc_setup_rxdesc(sc, idx, seg.ds_addr);
576
577	return (0);
578	}
579
580	static struct mbuf *
581	dwc_alloc_mbufcl(struct dwc_softc *sc)
582	{
583	struct mbuf *m;
584
585	m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
586	m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
587
588	return (m);
589	}
590
591	static void
592	dwc_media_status(struct ifnet * ifp, struct ifmediareq *ifmr)
593	{
594	struct dwc_softc *sc;
595	struct mii_data *mii;
596
597	sc = ifp->if_softc;
598	mii = sc->mii_softc;
599	DWC_LOCK(sc);
600	mii_pollstat(mii);
601	ifmr->ifm_active = mii->mii_media_active;
602	ifmr->ifm_status = mii->mii_media_status;
603	DWC_UNLOCK(sc);
604	}
605
606	static int
607	dwc_media_change_locked(struct dwc_softc *sc)
608	{
609
610	return (mii_mediachg(sc->mii_softc));
611	}
612
613	static int
614	dwc_media_change(struct ifnet * ifp)
615	{
616	struct dwc_softc *sc;
617	int error;
618
619	sc = ifp->if_softc;
620
621	DWC_LOCK(sc);
622	error = dwc_media_change_locked(sc);
623	DWC_UNLOCK(sc);
624	return (error);
625	}
626
627	static const uint8_t nibbletab[] = {
628	/* 0x0 0000 -> 0000 */ 0x0,
629	/* 0x1 0001 -> 1000 */ 0x8,
630	/* 0x2 0010 -> 0100 */ 0x4,
631	/* 0x3 0011 -> 1100 */ 0xc,
632	/* 0x4 0100 -> 0010 */ 0x2,
633	/* 0x5 0101 -> 1010 */ 0xa,
634	/* 0x6 0110 -> 0110 */ 0x6,
635	/* 0x7 0111 -> 1110 */ 0xe,
636	/* 0x8 1000 -> 0001 */ 0x1,
637	/* 0x9 1001 -> 1001 */ 0x9,
638	/* 0xa 1010 -> 0101 */ 0x5,
639	/* 0xb 1011 -> 1101 */ 0xd,
640	/* 0xc 1100 -> 0011 */ 0x3,
641	/* 0xd 1101 -> 1011 */ 0xb,
642	/* 0xe 1110 -> 0111 */ 0x7,
643	/* 0xf 1111 -> 1111 */ 0xf, };
644
645	static uint8_t
646	bitreverse(uint8_t x)
647	{
648
649	return (nibbletab[x & 0xf] << 4) \| nibbletab[x >> 4];
650	}
651
652	static void
653	dwc_setup_rxfilter(struct dwc_softc *sc)
654	{
655	struct ifmultiaddr *ifma;
656	struct ifnet *ifp;
657	uint8_t *eaddr;
658	uint32_t crc;
659	uint8_t val;
660	int hashbit;
661	int hashreg;
662	int ffval;
663	int reg;
664	int lo;
665	int hi;
666
667	DWC_ASSERT_LOCKED(sc);
668
669	ifp = sc->ifp;
670
671	/*
672	* Set the multicast (group) filter hash.
673	*/
674	if ((ifp->if_flags & IFF_ALLMULTI))
675	ffval = (FRAME_FILTER_PM);
676	else {
677	ffval = (FRAME_FILTER_HMC);
678	if_maddr_rlock(ifp);
679	TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) {
680	if (ifma->ifma_addr->sa_family != AF_LINK)
681	continue;
682	crc = ether_crc32_le(LLADDR((struct sockaddr_dl *)
683	ifma->ifma_addr), ETHER_ADDR_LEN);
684
685	/* Take lower 8 bits and reverse it */
686	val = bitreverse(~crc & 0xff);
687	hashreg = (val >> 5);
688	hashbit = (val & 31);
689
690	reg = READ4(sc, HASH_TABLE_REG(hashreg));
691	reg \|= (1 << hashbit);
692	WRITE4(sc, HASH_TABLE_REG(hashreg), reg);
693	}
694	if_maddr_runlock(ifp);
695	}
696
697	/*
698	* Set the individual address filter hash.
699	*/
700	if (ifp->if_flags & IFF_PROMISC)
701	ffval \|= (FRAME_FILTER_PR);
702
703	/*
704	* Set the primary address.
705	*/
706	eaddr = IF_LLADDR(ifp);
707	lo = eaddr[0] \| (eaddr[1] << 8) \| (eaddr[2] << 16) \|
708	(eaddr[3] << 24);
709	hi = eaddr[4] \| (eaddr[5] << 8);
710	WRITE4(sc, MAC_ADDRESS_LOW(0), lo);
711	WRITE4(sc, MAC_ADDRESS_HIGH(0), hi);
712	WRITE4(sc, MAC_FRAME_FILTER, ffval);
713	}
714
715	static int
716	dwc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
717	{
718	struct dwc_softc *sc;
719	struct mii_data *mii;
720	struct ifreq *ifr;
721	int mask, error;
722
723	sc = ifp->if_softc;
724	ifr = (struct ifreq *)data;
725
726	error = 0;
727	switch (cmd) {
728	case SIOCSIFFLAGS:
729	DWC_LOCK(sc);
730	if (ifp->if_flags & IFF_UP) {
731	if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
732	if ((ifp->if_flags ^ sc->if_flags) &
733	(IFF_PROMISC \| IFF_ALLMULTI))
734	dwc_setup_rxfilter(sc);
735	} else {
736	if (!sc->is_detaching)
737	dwc_init_locked(sc);
738	}
739	} else {
740	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
741	dwc_stop_locked(sc);
742	}
743	sc->if_flags = ifp->if_flags;
744	DWC_UNLOCK(sc);
745	break;
746	case SIOCADDMULTI:
747	case SIOCDELMULTI:
748	if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
749	DWC_LOCK(sc);
750	dwc_setup_rxfilter(sc);
751	DWC_UNLOCK(sc);
752	}
753	break;
754	case SIOCSIFMEDIA:
755	case SIOCGIFMEDIA:
756	mii = sc->mii_softc;
757	error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
758	break;
759	case SIOCSIFCAP:
760	mask = ifp->if_capenable ^ ifr->ifr_reqcap;
761	if (mask & IFCAP_VLAN_MTU) {
762	/* No work to do except acknowledge the change took */
763	ifp->if_capenable ^= IFCAP_VLAN_MTU;
764	}
765	break;
766
767	default:
768	error = ether_ioctl(ifp, cmd, data);
769	break;
770	}
771
772	return (error);
773	}
774
775	static void
776	dwc_txfinish_locked(struct dwc_softc *sc)
777	{
778	struct dwc_bufmap *bmap;
779	struct dwc_hwdesc *desc;
780	struct ifnet *ifp;
781
782	DWC_ASSERT_LOCKED(sc);
783
784	ifp = sc->ifp;
785
786	while (sc->tx_idx_tail != sc->tx_idx_head) {
787	desc = &sc->txdesc_ring[sc->tx_idx_tail];
788	if ((desc->tdes0 & DDESC_TDES0_OWN) != 0)
789	break;
790	bmap = &sc->txbuf_map[sc->tx_idx_tail];
791	bus_dmamap_sync(sc->txbuf_tag, bmap->map,
792	BUS_DMASYNC_POSTWRITE);
793	bus_dmamap_unload(sc->txbuf_tag, bmap->map);
794	m_freem(bmap->mbuf);
795	bmap->mbuf = NULL;
796	dwc_setup_txdesc(sc, sc->tx_idx_tail, 0, 0);
797	sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail);
798	}
799
800	/* If there are no buffers outstanding, muzzle the watchdog. */
801	if (sc->tx_idx_tail == sc->tx_idx_head) {
802	sc->tx_watchdog_count = 0;
803	}
804	}
805
806	static void
807	dwc_rxfinish_locked(struct dwc_softc *sc)
808	{
809	struct ifnet *ifp;
810	struct mbuf *m0;
811	struct mbuf *m;
812	int error;
813	int rdes0;
814	int idx;
815	int len;
816
817	ifp = sc->ifp;
818
819	for (;;) {
820	idx = sc->rx_idx;
821
822	rdes0 = sc->rxdesc_ring[idx].tdes0;
823	if ((rdes0 & DDESC_RDES0_OWN) != 0)
824	break;
825
826	bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
827	BUS_DMASYNC_POSTREAD);
828	bus_dmamap_unload(sc->rxbuf_tag, sc->rxbuf_map[idx].map);
829
830	len = (rdes0 >> DDESC_RDES0_FL_SHIFT) & DDESC_RDES0_FL_MASK;
831	if (len != 0) {
832	m = sc->rxbuf_map[idx].mbuf;
833	m->m_pkthdr.rcvif = ifp;
834	m->m_pkthdr.len = len;
835	m->m_len = len;
836	#ifndef __rtems__
837	if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
838	#else /* __rtems__ */
839	++ifp->if_ipackets;
840	#endif /* __rtems__ */
841
842	DWC_UNLOCK(sc);
843	(*ifp->if_input)(ifp, m);
844	DWC_LOCK(sc);
845	} else {
846	/* XXX Zero-length packet ? */
847	}
848
849	if ((m0 = dwc_alloc_mbufcl(sc)) != NULL) {
850	if ((error = dwc_setup_rxbuf(sc, idx, m0)) != 0) {
851	/*
852	* XXX Now what?
853	* We've got a hole in the rx ring.
854	*/
855	}
856	} else
857	#ifndef __rtems__
858	if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1);
859	#else /* __rtems__ */
860	++ifp->if_iqdrops;
861	#endif /* __rtems__ */
862
863	sc->rx_idx = next_rxidx(sc, sc->rx_idx);
864	}
865	}
866
867	static void
868	dwc_intr(void *arg)
869	{
870	struct dwc_softc *sc;
871	uint32_t reg;
872
873	sc = arg;
874
875	DWC_LOCK(sc);
876
877	reg = READ4(sc, INTERRUPT_STATUS);
878	if (reg) {
879	mii_mediachg(sc->mii_softc);
880	READ4(sc, SGMII_RGMII_SMII_CTRL_STATUS);
881	}
882
883	reg = READ4(sc, DMA_STATUS);
884	if (reg & DMA_STATUS_NIS) {
885	if (reg & DMA_STATUS_RI)
886	dwc_rxfinish_locked(sc);
887
888	if (reg & DMA_STATUS_TI)
889	dwc_txfinish_locked(sc);
890	}
891
892	if (reg & DMA_STATUS_AIS) {
893	if (reg & DMA_STATUS_FBI) {
894	/* Fatal bus error */
895	device_printf(sc->dev,
896	"Ethernet DMA error, restarting controller.\n");
897	dwc_stop_locked(sc);
898	dwc_init_locked(sc);
899	}
900	}
901
902	WRITE4(sc, DMA_STATUS, reg & DMA_STATUS_INTR_MASK);
903	DWC_UNLOCK(sc);
904	}
905
906	static int
907	setup_dma(struct dwc_softc *sc)
908	{
909	struct mbuf *m;
910	int error;
911	int nidx;
912	int idx;
913
914	/*
915	* Set up TX descriptor ring, descriptors, and dma maps.
916	*/
917	error = bus_dma_tag_create(
918	bus_get_dma_tag(sc->dev), /* Parent tag. */
919	DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */
920	BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
921	BUS_SPACE_MAXADDR, /* highaddr */
922	NULL, NULL, /* filter, filterarg */
923	TX_DESC_SIZE, 1, /* maxsize, nsegments */
924	TX_DESC_SIZE, /* maxsegsize */
925	0, /* flags */
926	NULL, NULL, /* lockfunc, lockarg */
927	&sc->txdesc_tag);
928	if (error != 0) {
929	device_printf(sc->dev,
930	"could not create TX ring DMA tag.\n");
931	goto out;
932	}
933
934	error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring,
935	BUS_DMA_COHERENT \| BUS_DMA_WAITOK \| BUS_DMA_ZERO,
936	&sc->txdesc_map);
937	if (error != 0) {
938	device_printf(sc->dev,
939	"could not allocate TX descriptor ring.\n");
940	goto out;
941	}
942
943	error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map,
944	sc->txdesc_ring, TX_DESC_SIZE, dwc_get1paddr,
945	&sc->txdesc_ring_paddr, 0);
946	if (error != 0) {
947	device_printf(sc->dev,
948	"could not load TX descriptor ring map.\n");
949	goto out;
950	}
951
952	for (idx = 0; idx < TX_DESC_COUNT; idx++) {
953	sc->txdesc_ring[idx].tdes0 = DDESC_TDES0_TXCHAIN;
954	sc->txdesc_ring[idx].tdes1 = 0;
955	nidx = next_txidx(sc, idx);
956	sc->txdesc_ring[idx].addr_next = sc->txdesc_ring_paddr + \
957	(nidx * sizeof(struct dwc_hwdesc));
958	}
959
960	error = bus_dma_tag_create(
961	bus_get_dma_tag(sc->dev), /* Parent tag. */
962	1, 0, /* alignment, boundary */
963	BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
964	BUS_SPACE_MAXADDR, /* highaddr */
965	NULL, NULL, /* filter, filterarg */
966	MCLBYTES, 1, /* maxsize, nsegments */
967	MCLBYTES, /* maxsegsize */
968	0, /* flags */
969	NULL, NULL, /* lockfunc, lockarg */
970	&sc->txbuf_tag);
971	if (error != 0) {
972	device_printf(sc->dev,
973	"could not create TX ring DMA tag.\n");
974	goto out;
975	}
976
977	for (idx = 0; idx < TX_DESC_COUNT; idx++) {
978	error = bus_dmamap_create(sc->txbuf_tag, BUS_DMA_COHERENT,
979	&sc->txbuf_map[idx].map);
980	if (error != 0) {
981	device_printf(sc->dev,
982	"could not create TX buffer DMA map.\n");
983	goto out;
984	}
985	dwc_setup_txdesc(sc, idx, 0, 0);
986	}
987
988	/*
989	* Set up RX descriptor ring, descriptors, dma maps, and mbufs.
990	*/
991	error = bus_dma_tag_create(
992	bus_get_dma_tag(sc->dev), /* Parent tag. */
993	DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */
994	BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
995	BUS_SPACE_MAXADDR, /* highaddr */
996	NULL, NULL, /* filter, filterarg */
997	RX_DESC_SIZE, 1, /* maxsize, nsegments */
998	RX_DESC_SIZE, /* maxsegsize */
999	0, /* flags */
1000	NULL, NULL, /* lockfunc, lockarg */
1001	&sc->rxdesc_tag);
1002	if (error != 0) {
1003	device_printf(sc->dev,
1004	"could not create RX ring DMA tag.\n");
1005	goto out;
1006	}
1007
1008	error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring,
1009	BUS_DMA_COHERENT \| BUS_DMA_WAITOK \| BUS_DMA_ZERO,
1010	&sc->rxdesc_map);
1011	if (error != 0) {
1012	device_printf(sc->dev,
1013	"could not allocate RX descriptor ring.\n");
1014	goto out;
1015	}
1016
1017	error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map,
1018	sc->rxdesc_ring, RX_DESC_SIZE, dwc_get1paddr,
1019	&sc->rxdesc_ring_paddr, 0);
1020	if (error != 0) {
1021	device_printf(sc->dev,
1022	"could not load RX descriptor ring map.\n");
1023	goto out;
1024	}
1025
1026	error = bus_dma_tag_create(
1027	bus_get_dma_tag(sc->dev), /* Parent tag. */
1028	1, 0, /* alignment, boundary */
1029	BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1030	BUS_SPACE_MAXADDR, /* highaddr */
1031	NULL, NULL, /* filter, filterarg */
1032	MCLBYTES, 1, /* maxsize, nsegments */
1033	MCLBYTES, /* maxsegsize */
1034	0, /* flags */
1035	NULL, NULL, /* lockfunc, lockarg */
1036	&sc->rxbuf_tag);
1037	if (error != 0) {
1038	device_printf(sc->dev,
1039	"could not create RX buf DMA tag.\n");
1040	goto out;
1041	}
1042
1043	for (idx = 0; idx < RX_DESC_COUNT; idx++) {
1044	error = bus_dmamap_create(sc->rxbuf_tag, BUS_DMA_COHERENT,
1045	&sc->rxbuf_map[idx].map);
1046	if (error != 0) {
1047	device_printf(sc->dev,
1048	"could not create RX buffer DMA map.\n");
1049	goto out;
1050	}
1051	if ((m = dwc_alloc_mbufcl(sc)) == NULL) {
1052	device_printf(sc->dev, "Could not alloc mbuf\n");
1053	error = ENOMEM;
1054	goto out;
1055	}
1056	if ((error = dwc_setup_rxbuf(sc, idx, m)) != 0) {
1057	device_printf(sc->dev,
1058	"could not create new RX buffer.\n");
1059	goto out;
1060	}
1061	}
1062
1063	out:
1064	if (error != 0)
1065	return (ENXIO);
1066
1067	return (0);
1068	}
1069
1070	static int
1071	dwc_get_hwaddr(struct dwc_softc sc, uint8_t hwaddr)
1072	{
1073	#ifndef __rtems__
1074	int rnd;
1075	#endif /* __rtems__ */
1076	int lo;
1077	int hi;
1078
1079	/*
1080	* Try to recover a MAC address from the running hardware. If there's
1081	* something non-zero there, assume the bootloader did the right thing
1082	* and just use it.
1083	*
1084	* Otherwise, set the address to a convenient locally assigned address,
1085	* 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally
1086	* assigned bit set, and the broadcast/multicast bit clear.
1087	*/
1088	lo = READ4(sc, MAC_ADDRESS_LOW(0));
1089	hi = READ4(sc, MAC_ADDRESS_HIGH(0)) & 0xffff;
1090	if ((lo != 0xffffffff) \|\| (hi != 0xffff)) {
1091	hwaddr[0] = (lo >> 0) & 0xff;
1092	hwaddr[1] = (lo >> 8) & 0xff;
1093	hwaddr[2] = (lo >> 16) & 0xff;
1094	hwaddr[3] = (lo >> 24) & 0xff;
1095	hwaddr[4] = (hi >> 0) & 0xff;
1096	hwaddr[5] = (hi >> 8) & 0xff;
1097	} else {
1098	#ifndef __rtems__
1099	rnd = arc4random() & 0x00ffffff;
1100	hwaddr[0] = 'b';
1101	hwaddr[1] = 's';
1102	hwaddr[2] = 'd';
1103	hwaddr[3] = rnd >> 16;
1104	hwaddr[4] = rnd >> 8;
1105	hwaddr[5] = rnd >> 0;
1106	#else /* __rtems__ */
1107	rtems_bsd_get_mac_address(device_get_name(sc->dev),
1108	device_get_unit(sc->dev), hwaddr);
1109	#endif /* __rtems__ */
1110	}
1111
1112	return (0);
1113	}
1114
1115	static int
1116	dwc_probe(device_t dev)
1117	{
1118
1119	#ifndef __rtems__
1120	if (!ofw_bus_status_okay(dev))
1121	return (ENXIO);
1122
1123	if (!ofw_bus_is_compatible(dev, "snps,dwmac"))
1124	return (ENXIO);
1125	#endif /* __rtems__ */
1126
1127	device_set_desc(dev, "Gigabit Ethernet Controller");
1128	return (BUS_PROBE_DEFAULT);
1129	}
1130
1131	static int
1132	dwc_attach(device_t dev)
1133	{
1134	uint8_t macaddr[ETHER_ADDR_LEN];
1135	struct dwc_softc *sc;
1136	struct ifnet *ifp;
1137	int error;
1138	int reg;
1139	int i;
1140
1141	sc = device_get_softc(dev);
1142	sc->dev = dev;
1143	sc->mii_clk = MII_CLK_VAL;
1144	sc->rx_idx = 0;
1145
1146	sc->txcount = TX_DESC_COUNT;
1147
1148	if (bus_alloc_resources(dev, dwc_spec, sc->res)) {
1149	device_printf(dev, "could not allocate resources\n");
1150	return (ENXIO);
1151	}
1152
1153	/* Memory interface */
1154	sc->bst = rman_get_bustag(sc->res[0]);
1155	sc->bsh = rman_get_bushandle(sc->res[0]);
1156
1157	/* Read MAC before reset */
1158	if (dwc_get_hwaddr(sc, macaddr)) {
1159	device_printf(sc->dev, "can't get mac\n");
1160	return (ENXIO);
1161	}
1162
1163	/* Reset */
1164	reg = READ4(sc, BUS_MODE);
1165	reg \|= (BUS_MODE_SWR);
1166	WRITE4(sc, BUS_MODE, reg);
1167
1168	for (i = 0; i < MAC_RESET_TIMEOUT; i++) {
1169	if ((READ4(sc, BUS_MODE) & BUS_MODE_SWR) == 0)
1170	break;
1171	DELAY(10);
1172	}
1173	if (i >= MAC_RESET_TIMEOUT) {
1174	device_printf(sc->dev, "Can't reset DWC.\n");
1175	return (ENXIO);
1176	}
1177
1178	reg = READ4(sc, BUS_MODE);
1179	reg \|= (BUS_MODE_EIGHTXPBL);
1180	reg \|= (BUS_MODE_PBL_BEATS_8 << BUS_MODE_PBL_SHIFT);
1181	WRITE4(sc, BUS_MODE, reg);
1182
1183	/*
1184	* DMA must be stop while changing descriptor list addresses.
1185	*/
1186	reg = READ4(sc, OPERATION_MODE);
1187	reg &= ~(MODE_ST \| MODE_SR);
1188	WRITE4(sc, OPERATION_MODE, reg);
1189
1190	if (setup_dma(sc))
1191	return (ENXIO);
1192
1193	/* Setup addresses */
1194	WRITE4(sc, RX_DESCR_LIST_ADDR, sc->rxdesc_ring_paddr);
1195	WRITE4(sc, TX_DESCR_LIST_ADDR, sc->txdesc_ring_paddr);
1196
1197	mtx_init(&sc->mtx, device_get_nameunit(sc->dev),
1198	MTX_NETWORK_LOCK, MTX_DEF);
1199
1200	callout_init_mtx(&sc->dwc_callout, &sc->mtx, 0);
1201
1202	/* Set up the ethernet interface. */
1203	sc->ifp = ifp = if_alloc(IFT_ETHER);
1204
1205	ifp->if_softc = sc;
1206	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1207	ifp->if_flags = IFF_BROADCAST \| IFF_SIMPLEX \| IFF_MULTICAST;
1208	ifp->if_capabilities = IFCAP_VLAN_MTU;
1209	ifp->if_capenable = ifp->if_capabilities;
1210	ifp->if_start = dwc_txstart;
1211	ifp->if_ioctl = dwc_ioctl;
1212	ifp->if_init = dwc_init;
1213	IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1);
1214	ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1;
1215	IFQ_SET_READY(&ifp->if_snd);
1216	ifp->if_hdrlen = sizeof(struct ether_vlan_header);
1217
1218	/* Attach the mii driver. */
1219	error = mii_attach(dev, &sc->miibus, ifp, dwc_media_change,
1220	dwc_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY,
1221	MII_OFFSET_ANY, 0);
1222
1223	if (error != 0) {
1224	device_printf(dev, "PHY attach failed\n");
1225	return (ENXIO);
1226	}
1227	sc->mii_softc = device_get_softc(sc->miibus);
1228
1229	/* Setup interrupt handler. */
1230	error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET \| INTR_MPSAFE,
1231	NULL, dwc_intr, sc, &sc->intr_cookie);
1232	if (error != 0) {
1233	device_printf(dev, "could not setup interrupt handler.\n");
1234	return (ENXIO);
1235	}
1236
1237	/* All ready to run, attach the ethernet interface. */
1238	ether_ifattach(ifp, macaddr);
1239	sc->is_attached = true;
1240
1241	return (0);
1242	}
1243
1244	static int
1245	dwc_miibus_read_reg(device_t dev, int phy, int reg)
1246	{
1247	struct dwc_softc *sc;
1248	uint16_t mii;
1249	size_t cnt;
1250	int rv = 0;
1251
1252	sc = device_get_softc(dev);
1253
1254	mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT)
1255	\| ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT)
1256	\| (sc->mii_clk << GMII_ADDRESS_CR_SHIFT)
1257	\| GMII_ADDRESS_GB; /* Busy flag */
1258
1259	WRITE4(sc, GMII_ADDRESS, mii);
1260
1261	for (cnt = 0; cnt < 1000; cnt++) {
1262	if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) {
1263	rv = READ4(sc, GMII_DATA);
1264	break;
1265	}
1266	DELAY(10);
1267	}
1268
1269	return rv;
1270	}
1271
1272	static int
1273	dwc_miibus_write_reg(device_t dev, int phy, int reg, int val)
1274	{
1275	struct dwc_softc *sc;
1276	uint16_t mii;
1277	size_t cnt;
1278
1279	sc = device_get_softc(dev);
1280
1281	mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT)
1282	\| ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT)
1283	\| (sc->mii_clk << GMII_ADDRESS_CR_SHIFT)
1284	\| GMII_ADDRESS_GB \| GMII_ADDRESS_GW;
1285
1286	WRITE4(sc, GMII_DATA, val);
1287	WRITE4(sc, GMII_ADDRESS, mii);
1288
1289	for (cnt = 0; cnt < 1000; cnt++) {
1290	if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) {
1291	break;
1292	}
1293	DELAY(10);
1294	}
1295
1296	return (0);
1297	}
1298
1299	static void
1300	dwc_miibus_statchg(device_t dev)
1301	{
1302	struct dwc_softc *sc;
1303	struct mii_data *mii;
1304	int reg;
1305
1306	/*
1307	* Called by the MII bus driver when the PHY establishes
1308	* link to set the MAC interface registers.
1309	*/
1310
1311	sc = device_get_softc(dev);
1312
1313	DWC_ASSERT_LOCKED(sc);
1314
1315	mii = sc->mii_softc;
1316
1317	if (mii->mii_media_status & IFM_ACTIVE)
1318	sc->link_is_up = true;
1319	else
1320	sc->link_is_up = false;
1321
1322	reg = READ4(sc, MAC_CONFIGURATION);
1323	switch (IFM_SUBTYPE(mii->mii_media_active)) {
1324	case IFM_1000_T:
1325	case IFM_1000_SX:
1326	reg &= ~(CONF_FES \| CONF_PS);
1327	break;
1328	case IFM_100_TX:
1329	reg \|= (CONF_FES \| CONF_PS);
1330	break;
1331	case IFM_10_T:
1332	reg &= ~(CONF_FES);
1333	reg \|= (CONF_PS);
1334	break;
1335	case IFM_NONE:
1336	sc->link_is_up = false;
1337	return;
1338	default:
1339	sc->link_is_up = false;
1340	device_printf(dev, "Unsupported media %u\n",
1341	IFM_SUBTYPE(mii->mii_media_active));
1342	return;
1343	}
1344	if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
1345	reg \|= (CONF_DM);
1346	else
1347	reg &= ~(CONF_DM);
1348	WRITE4(sc, MAC_CONFIGURATION, reg);
1349	}
1350
1351	static device_method_t dwc_methods[] = {
1352	DEVMETHOD(device_probe, dwc_probe),
1353	DEVMETHOD(device_attach, dwc_attach),
1354
1355	/* MII Interface */
1356	DEVMETHOD(miibus_readreg, dwc_miibus_read_reg),
1357	DEVMETHOD(miibus_writereg, dwc_miibus_write_reg),
1358	DEVMETHOD(miibus_statchg, dwc_miibus_statchg),
1359
1360	{ 0, 0 }
1361	};
1362
1363	static driver_t dwc_driver = {
1364	"dwc",
1365	dwc_methods,
1366	sizeof(struct dwc_softc),
1367	};
1368
1369	static devclass_t dwc_devclass;
1370
1371	#ifndef __rtems__
1372	DRIVER_MODULE(dwc, simplebus, dwc_driver, dwc_devclass, 0, 0);
1373	#else /* __rtems__ */
1374	DRIVER_MODULE(dwc, nexus, dwc_driver, dwc_devclass, 0, 0);
1375	#endif /* __rtems__ */
1376	DRIVER_MODULE(miibus, dwc, miibus_driver, miibus_devclass, 0, 0);
1377
1378	MODULE_DEPEND(dwc, ether, 1, 1, 1);
1379	MODULE_DEPEND(dwc, miibus, 1, 1, 1);

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