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source: rtems-libbsd/freebsd/sys/dev/cadence/if_cgem.c @ 14ecf75d

4.1155-freebsd-126-freebsd-12freebsd-9.3

Last change on this file since 14ecf75d was 14ecf75d, checked in by Sebastian Huber <sebastian.huber@…>, on 11/20/14 at 06:59:45
if_cgem: Workaround for missing FDT support
Property mode set to `100644`
File size: 51.6 KB

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1	#include <machine/rtems-bsd-kernel-space.h>
2
3	/*-
4	* Copyright (c) 2012-2014 Thomas Skibo <thomasskibo@yahoo.com>
5	* All rights reserved.
6	*
7	* Redistribution and use in source and binary forms, with or without
8	* modification, are permitted provided that the following conditions
9	* are met:
10	* 1. Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.
12	* 2. Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.
15	*
16	* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19	* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
20	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26	* SUCH DAMAGE.
27	*/
28
29	/*
30	* A network interface driver for Cadence GEM Gigabit Ethernet
31	* interface such as the one used in Xilinx Zynq-7000 SoC.
32	*
33	* Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
34	* (v1.4) November 16, 2012. Xilinx doc UG585. GEM is covered in Ch. 16
35	* and register definitions are in appendix B.18.
36	*/
37
38	#include <sys/cdefs.h>
39	__FBSDID("$FreeBSD$");
40
41	#include <rtems/bsd/sys/param.h>
42	#include <sys/systm.h>
43	#include <sys/bus.h>
44	#include <sys/kernel.h>
45	#include <sys/malloc.h>
46	#include <sys/mbuf.h>
47	#include <sys/module.h>
48	#include <sys/rman.h>
49	#include <sys/socket.h>
50	#include <sys/sockio.h>
51	#include <sys/sysctl.h>
52
53	#include <machine/bus.h>
54
55	#include <net/ethernet.h>
56	#include <net/if.h>
57	#include <net/if_var.h>
58	#include <net/if_arp.h>
59	#include <net/if_dl.h>
60	#include <net/if_media.h>
61	#include <net/if_mib.h>
62	#include <net/if_types.h>
63
64	#ifdef INET
65	#include <netinet/in.h>
66	#include <netinet/in_systm.h>
67	#include <netinet/in_var.h>
68	#include <netinet/ip.h>
69	#endif
70
71	#include <net/bpf.h>
72	#include <net/bpfdesc.h>
73
74	#ifndef __rtems__
75	#include <dev/fdt/fdt_common.h>
76	#include <dev/ofw/ofw_bus.h>
77	#include <dev/ofw/ofw_bus_subr.h>
78	#endif /* __rtems__ */
79
80	#include <dev/mii/mii.h>
81	#include <dev/mii/miivar.h>
82
83	#include <dev/cadence/if_cgem_hw.h>
84
85	#include <rtems/bsd/local/miibus_if.h>
86
87	#define IF_CGEM_NAME "cgem"
88
89	#define CGEM_NUM_RX_DESCS 512 /* size of receive descriptor ring */
90	#define CGEM_NUM_TX_DESCS 512 /* size of transmit descriptor ring */
91
92	#define MAX_DESC_RING_SIZE (MAX(CGEM_NUM_RX_DESCS*sizeof(struct cgem_rx_desc),\
93	CGEM_NUM_TX_DESCS*sizeof(struct cgem_tx_desc)))
94
95
96	/* Default for sysctl rxbufs. Must be < CGEM_NUM_RX_DESCS of course. */
97	#define DEFAULT_NUM_RX_BUFS 256 /* number of receive bufs to queue. */
98
99	#define TX_MAX_DMA_SEGS 8 /* maximum segs in a tx mbuf dma */
100
101	#define CGEM_CKSUM_ASSIST (CSUM_IP \| CSUM_TCP \| CSUM_UDP \| \
102	CSUM_TCP_IPV6 \| CSUM_UDP_IPV6)
103
104	struct cgem_softc {
105	struct ifnet *ifp;
106	struct mtx sc_mtx;
107	device_t dev;
108	device_t miibus;
109	u_int mii_media_active; /* last active media */
110	int if_old_flags;
111	struct resource *mem_res;
112	struct resource *irq_res;
113	void *intrhand;
114	struct callout tick_ch;
115	uint32_t net_ctl_shadow;
116	int ref_clk_num;
117	u_char eaddr[6];
118
119	bus_dma_tag_t desc_dma_tag;
120	bus_dma_tag_t mbuf_dma_tag;
121
122	/* receive descriptor ring */
123	struct cgem_rx_desc *rxring;
124	bus_addr_t rxring_physaddr;
125	struct mbuf *rxring_m[CGEM_NUM_RX_DESCS];
126	bus_dmamap_t rxring_m_dmamap[CGEM_NUM_RX_DESCS];
127	int rxring_hd_ptr; /* where to put rcv bufs */
128	int rxring_tl_ptr; /* where to get receives */
129	int rxring_queued; /* how many rcv bufs queued */
130	bus_dmamap_t rxring_dma_map;
131	int rxbufs; /* tunable number rcv bufs */
132	int rxhangwar; /* rx hang work-around */
133	u_int rxoverruns; /* rx overruns */
134	u_int rxnobufs; /* rx buf ring empty events */
135	u_int rxdmamapfails; /* rx dmamap failures */
136	uint32_t rx_frames_prev;
137
138	/* transmit descriptor ring */
139	struct cgem_tx_desc *txring;
140	bus_addr_t txring_physaddr;
141	struct mbuf *txring_m[CGEM_NUM_TX_DESCS];
142	bus_dmamap_t txring_m_dmamap[CGEM_NUM_TX_DESCS];
143	int txring_hd_ptr; /* where to put next xmits */
144	int txring_tl_ptr; /* next xmit mbuf to free */
145	int txring_queued; /* num xmits segs queued */
146	bus_dmamap_t txring_dma_map;
147	u_int txfull; /* tx ring full events */
148	u_int txdefrags; /* tx calls to m_defrag() */
149	u_int txdefragfails; /* tx m_defrag() failures */
150	u_int txdmamapfails; /* tx dmamap failures */
151
152	/* hardware provided statistics */
153	struct cgem_hw_stats {
154	uint64_t tx_bytes;
155	uint32_t tx_frames;
156	uint32_t tx_frames_bcast;
157	uint32_t tx_frames_multi;
158	uint32_t tx_frames_pause;
159	uint32_t tx_frames_64b;
160	uint32_t tx_frames_65to127b;
161	uint32_t tx_frames_128to255b;
162	uint32_t tx_frames_256to511b;
163	uint32_t tx_frames_512to1023b;
164	uint32_t tx_frames_1024to1536b;
165	uint32_t tx_under_runs;
166	uint32_t tx_single_collisn;
167	uint32_t tx_multi_collisn;
168	uint32_t tx_excsv_collisn;
169	uint32_t tx_late_collisn;
170	uint32_t tx_deferred_frames;
171	uint32_t tx_carrier_sense_errs;
172
173	uint64_t rx_bytes;
174	uint32_t rx_frames;
175	uint32_t rx_frames_bcast;
176	uint32_t rx_frames_multi;
177	uint32_t rx_frames_pause;
178	uint32_t rx_frames_64b;
179	uint32_t rx_frames_65to127b;
180	uint32_t rx_frames_128to255b;
181	uint32_t rx_frames_256to511b;
182	uint32_t rx_frames_512to1023b;
183	uint32_t rx_frames_1024to1536b;
184	uint32_t rx_frames_undersize;
185	uint32_t rx_frames_oversize;
186	uint32_t rx_frames_jabber;
187	uint32_t rx_frames_fcs_errs;
188	uint32_t rx_frames_length_errs;
189	uint32_t rx_symbol_errs;
190	uint32_t rx_align_errs;
191	uint32_t rx_resource_errs;
192	uint32_t rx_overrun_errs;
193	uint32_t rx_ip_hdr_csum_errs;
194	uint32_t rx_tcp_csum_errs;
195	uint32_t rx_udp_csum_errs;
196	} stats;
197	};
198
199	#define RD4(sc, off) (bus_read_4((sc)->mem_res, (off)))
200	#define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val)))
201	#define BARRIER(sc, off, len, flags) \
202	(bus_barrier((sc)->mem_res, (off), (len), (flags))
203
204	#define CGEM_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
205	#define CGEM_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
206	#define CGEM_LOCK_INIT(sc) \
207	mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \
208	MTX_NETWORK_LOCK, MTX_DEF)
209	#define CGEM_LOCK_DESTROY(sc) mtx_destroy(&(sc)->sc_mtx)
210	#define CGEM_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED)
211
212	/* Allow platforms to optionally provide a way to set the reference clock. */
213	int cgem_set_ref_clk(int unit, int frequency);
214
215	static devclass_t cgem_devclass;
216
217	static int cgem_probe(device_t dev);
218	static int cgem_attach(device_t dev);
219	static int cgem_detach(device_t dev);
220	static void cgem_tick(void *);
221	static void cgem_intr(void *);
222
223	static void cgem_mediachange(struct cgem_softc , struct mii_data );
224
225	static void
226	cgem_get_mac(struct cgem_softc *sc, u_char eaddr[])
227	{
228	int i;
229	uint32_t rnd;
230
231	/* See if boot loader gave us a MAC address already. */
232	for (i = 0; i < 4; i++) {
233	uint32_t low = RD4(sc, CGEM_SPEC_ADDR_LOW(i));
234	uint32_t high = RD4(sc, CGEM_SPEC_ADDR_HI(i)) & 0xffff;
235	if (low != 0 \|\| high != 0) {
236	eaddr[0] = low & 0xff;
237	eaddr[1] = (low >> 8) & 0xff;
238	eaddr[2] = (low >> 16) & 0xff;
239	eaddr[3] = (low >> 24) & 0xff;
240	eaddr[4] = high & 0xff;
241	eaddr[5] = (high >> 8) & 0xff;
242	break;
243	}
244	}
245
246	/* No MAC from boot loader? Assign a random one. */
247	if (i == 4) {
248	rnd = arc4random();
249
250	eaddr[0] = 'b';
251	eaddr[1] = 's';
252	eaddr[2] = 'd';
253	eaddr[3] = (rnd >> 16) & 0xff;
254	eaddr[4] = (rnd >> 8) & 0xff;
255	eaddr[5] = rnd & 0xff;
256
257	device_printf(sc->dev, "no mac address found, assigning "
258	"random: %02x:%02x:%02x:%02x:%02x:%02x\n",
259	eaddr[0], eaddr[1], eaddr[2],
260	eaddr[3], eaddr[4], eaddr[5]);
261	}
262
263	/* Move address to first slot and zero out the rest. */
264	WR4(sc, CGEM_SPEC_ADDR_LOW(0), (eaddr[3] << 24) \|
265	(eaddr[2] << 16) \| (eaddr[1] << 8) \| eaddr[0]);
266	WR4(sc, CGEM_SPEC_ADDR_HI(0), (eaddr[5] << 8) \| eaddr[4]);
267
268	for (i = 1; i < 4; i++) {
269	WR4(sc, CGEM_SPEC_ADDR_LOW(i), 0);
270	WR4(sc, CGEM_SPEC_ADDR_HI(i), 0);
271	}
272	}
273
274	/* cgem_mac_hash(): map 48-bit address to a 6-bit hash.
275	* The 6-bit hash corresponds to a bit in a 64-bit hash
276	* register. Setting that bit in the hash register enables
277	* reception of all frames with a destination address that hashes
278	* to that 6-bit value.
279	*
280	* The hash function is described in sec. 16.2.3 in the Zynq-7000 Tech
281	* Reference Manual. Bits 0-5 in the hash are the exclusive-or of
282	* every sixth bit in the destination address.
283	*/
284	static int
285	cgem_mac_hash(u_char eaddr[])
286	{
287	int hash;
288	int i, j;
289
290	hash = 0;
291	for (i = 0; i < 6; i++)
292	for (j = i; j < 48; j += 6)
293	if ((eaddr[j >> 3] & (1 << (j & 7))) != 0)
294	hash ^= (1 << i);
295
296	return hash;
297	}
298
299	/* After any change in rx flags or multi-cast addresses, set up
300	* hash registers and net config register bits.
301	*/
302	static void
303	cgem_rx_filter(struct cgem_softc *sc)
304	{
305	struct ifnet *ifp = sc->ifp;
306	struct ifmultiaddr *ifma;
307	int index;
308	uint32_t hash_hi, hash_lo;
309	uint32_t net_cfg;
310
311	hash_hi = 0;
312	hash_lo = 0;
313
314	net_cfg = RD4(sc, CGEM_NET_CFG);
315
316	net_cfg &= ~(CGEM_NET_CFG_MULTI_HASH_EN \|
317	CGEM_NET_CFG_NO_BCAST \|
318	CGEM_NET_CFG_COPY_ALL);
319
320	if ((ifp->if_flags & IFF_PROMISC) != 0)
321	net_cfg \|= CGEM_NET_CFG_COPY_ALL;
322	else {
323	if ((ifp->if_flags & IFF_BROADCAST) == 0)
324	net_cfg \|= CGEM_NET_CFG_NO_BCAST;
325	if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
326	hash_hi = 0xffffffff;
327	hash_lo = 0xffffffff;
328	} else {
329	if_maddr_rlock(ifp);
330	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
331	if (ifma->ifma_addr->sa_family != AF_LINK)
332	continue;
333	index = cgem_mac_hash(
334	LLADDR((struct sockaddr_dl *)
335	ifma->ifma_addr));
336	if (index > 31)
337	hash_hi \|= (1<<(index-32));
338	else
339	hash_lo \|= (1<<index);
340	}
341	if_maddr_runlock(ifp);
342	}
343
344	if (hash_hi != 0 \|\| hash_lo != 0)
345	net_cfg \|= CGEM_NET_CFG_MULTI_HASH_EN;
346	}
347
348	WR4(sc, CGEM_HASH_TOP, hash_hi);
349	WR4(sc, CGEM_HASH_BOT, hash_lo);
350	WR4(sc, CGEM_NET_CFG, net_cfg);
351	}
352
353	/* For bus_dmamap_load() callback. */
354	static void
355	cgem_getaddr(void arg, bus_dma_segment_t segs, int nsegs, int error)
356	{
357
358	if (nsegs != 1 \|\| error != 0)
359	return;
360	(bus_addr_t )arg = segs[0].ds_addr;
361	}
362
363	/* Create DMA'able descriptor rings. */
364	static int
365	cgem_setup_descs(struct cgem_softc *sc)
366	{
367	int i, err;
368
369	sc->txring = NULL;
370	sc->rxring = NULL;
371
372	/* Allocate non-cached DMA space for RX and TX descriptors.
373	*/
374	err = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
375	BUS_SPACE_MAXADDR_32BIT,
376	BUS_SPACE_MAXADDR,
377	NULL, NULL,
378	MAX_DESC_RING_SIZE,
379	1,
380	MAX_DESC_RING_SIZE,
381	0,
382	busdma_lock_mutex,
383	&sc->sc_mtx,
384	&sc->desc_dma_tag);
385	if (err)
386	return (err);
387
388	/* Set up a bus_dma_tag for mbufs. */
389	err = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
390	BUS_SPACE_MAXADDR_32BIT,
391	BUS_SPACE_MAXADDR,
392	NULL, NULL,
393	MCLBYTES,
394	TX_MAX_DMA_SEGS,
395	MCLBYTES,
396	0,
397	busdma_lock_mutex,
398	&sc->sc_mtx,
399	&sc->mbuf_dma_tag);
400	if (err)
401	return (err);
402
403	/* Allocate DMA memory in non-cacheable space. */
404	err = bus_dmamem_alloc(sc->desc_dma_tag,
405	(void **)&sc->rxring,
406	BUS_DMA_NOWAIT \| BUS_DMA_COHERENT,
407	&sc->rxring_dma_map);
408	if (err)
409	return (err);
410
411	/* Load descriptor DMA memory. */
412	err = bus_dmamap_load(sc->desc_dma_tag, sc->rxring_dma_map,
413	(void *)sc->rxring,
414	CGEM_NUM_RX_DESCS*sizeof(struct cgem_rx_desc),
415	cgem_getaddr, &sc->rxring_physaddr,
416	BUS_DMA_NOWAIT);
417	if (err)
418	return (err);
419
420	/* Initialize RX descriptors. */
421	for (i = 0; i < CGEM_NUM_RX_DESCS; i++) {
422	sc->rxring[i].addr = CGEM_RXDESC_OWN;
423	sc->rxring[i].ctl = 0;
424	sc->rxring_m[i] = NULL;
425	err = bus_dmamap_create(sc->mbuf_dma_tag, 0,
426	&sc->rxring_m_dmamap[i]);
427	if (err)
428	return (err);
429	}
430	sc->rxring[CGEM_NUM_RX_DESCS - 1].addr \|= CGEM_RXDESC_WRAP;
431
432	sc->rxring_hd_ptr = 0;
433	sc->rxring_tl_ptr = 0;
434	sc->rxring_queued = 0;
435
436	/* Allocate DMA memory for TX descriptors in non-cacheable space. */
437	err = bus_dmamem_alloc(sc->desc_dma_tag,
438	(void **)&sc->txring,
439	BUS_DMA_NOWAIT \| BUS_DMA_COHERENT,
440	&sc->txring_dma_map);
441	if (err)
442	return (err);
443
444	/* Load TX descriptor DMA memory. */
445	err = bus_dmamap_load(sc->desc_dma_tag, sc->txring_dma_map,
446	(void *)sc->txring,
447	CGEM_NUM_TX_DESCS*sizeof(struct cgem_tx_desc),
448	cgem_getaddr, &sc->txring_physaddr,
449	BUS_DMA_NOWAIT);
450	if (err)
451	return (err);
452
453	/* Initialize TX descriptor ring. */
454	for (i = 0; i < CGEM_NUM_TX_DESCS; i++) {
455	sc->txring[i].addr = 0;
456	sc->txring[i].ctl = CGEM_TXDESC_USED;
457	sc->txring_m[i] = NULL;
458	err = bus_dmamap_create(sc->mbuf_dma_tag, 0,
459	&sc->txring_m_dmamap[i]);
460	if (err)
461	return (err);
462	}
463	sc->txring[CGEM_NUM_TX_DESCS - 1].ctl \|= CGEM_TXDESC_WRAP;
464
465	sc->txring_hd_ptr = 0;
466	sc->txring_tl_ptr = 0;
467	sc->txring_queued = 0;
468
469	return (0);
470	}
471
472	/* Fill receive descriptor ring with mbufs. */
473	static void
474	cgem_fill_rqueue(struct cgem_softc *sc)
475	{
476	struct mbuf *m = NULL;
477	bus_dma_segment_t segs[TX_MAX_DMA_SEGS];
478	int nsegs;
479
480	CGEM_ASSERT_LOCKED(sc);
481
482	while (sc->rxring_queued < sc->rxbufs) {
483	/* Get a cluster mbuf. */
484	m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
485	if (m == NULL)
486	break;
487
488	m->m_len = MCLBYTES;
489	m->m_pkthdr.len = MCLBYTES;
490	m->m_pkthdr.rcvif = sc->ifp;
491
492	/* Load map and plug in physical address. */
493	if (bus_dmamap_load_mbuf_sg(sc->mbuf_dma_tag,
494	sc->rxring_m_dmamap[sc->rxring_hd_ptr], m,
495	segs, &nsegs, BUS_DMA_NOWAIT)) {
496	sc->rxdmamapfails++;
497	m_free(m);
498	break;
499	}
500	sc->rxring_m[sc->rxring_hd_ptr] = m;
501
502	/* Sync cache with receive buffer. */
503	bus_dmamap_sync(sc->mbuf_dma_tag,
504	sc->rxring_m_dmamap[sc->rxring_hd_ptr],
505	BUS_DMASYNC_PREREAD);
506
507	/* Write rx descriptor and increment head pointer. */
508	sc->rxring[sc->rxring_hd_ptr].ctl = 0;
509	if (sc->rxring_hd_ptr == CGEM_NUM_RX_DESCS - 1) {
510	sc->rxring[sc->rxring_hd_ptr].addr = segs[0].ds_addr \|
511	CGEM_RXDESC_WRAP;
512	sc->rxring_hd_ptr = 0;
513	} else
514	sc->rxring[sc->rxring_hd_ptr++].addr = segs[0].ds_addr;
515
516	sc->rxring_queued++;
517	}
518	}
519
520	/* Pull received packets off of receive descriptor ring. */
521	static void
522	cgem_recv(struct cgem_softc *sc)
523	{
524	struct ifnet *ifp = sc->ifp;
525	struct mbuf m, m_hd, **m_tl;
526	uint32_t ctl;
527
528	CGEM_ASSERT_LOCKED(sc);
529
530	/* Pick up all packets in which the OWN bit is set. */
531	m_hd = NULL;
532	m_tl = &m_hd;
533	while (sc->rxring_queued > 0 &&
534	(sc->rxring[sc->rxring_tl_ptr].addr & CGEM_RXDESC_OWN) != 0) {
535
536	ctl = sc->rxring[sc->rxring_tl_ptr].ctl;
537
538	/* Grab filled mbuf. */
539	m = sc->rxring_m[sc->rxring_tl_ptr];
540	sc->rxring_m[sc->rxring_tl_ptr] = NULL;
541
542	/* Sync cache with receive buffer. */
543	bus_dmamap_sync(sc->mbuf_dma_tag,
544	sc->rxring_m_dmamap[sc->rxring_tl_ptr],
545	BUS_DMASYNC_POSTREAD);
546
547	/* Unload dmamap. */
548	bus_dmamap_unload(sc->mbuf_dma_tag,
549	sc->rxring_m_dmamap[sc->rxring_tl_ptr]);
550
551	/* Increment tail pointer. */
552	if (++sc->rxring_tl_ptr == CGEM_NUM_RX_DESCS)
553	sc->rxring_tl_ptr = 0;
554	sc->rxring_queued--;
555
556	/* Check FCS and make sure entire packet landed in one mbuf
557	* cluster (which is much bigger than the largest ethernet
558	* packet).
559	*/
560	if ((ctl & CGEM_RXDESC_BAD_FCS) != 0 \|\|
561	(ctl & (CGEM_RXDESC_SOF \| CGEM_RXDESC_EOF)) !=
562	(CGEM_RXDESC_SOF \| CGEM_RXDESC_EOF)) {
563	/* discard. */
564	m_free(m);
565	#ifndef __rtems__
566	if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
567	#else /* __rtems__ */
568	ifp->if_ierrors++;
569	#endif /* __rtems__ */
570	continue;
571	}
572
573	/* Ready it to hand off to upper layers. */
574	m->m_data += ETHER_ALIGN;
575	m->m_len = (ctl & CGEM_RXDESC_LENGTH_MASK);
576	m->m_pkthdr.rcvif = ifp;
577	m->m_pkthdr.len = m->m_len;
578
579	/* Are we using hardware checksumming? Check the
580	* status in the receive descriptor.
581	*/
582	if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
583	/* TCP or UDP checks out, IP checks out too. */
584	if ((ctl & CGEM_RXDESC_CKSUM_STAT_MASK) ==
585	CGEM_RXDESC_CKSUM_STAT_TCP_GOOD \|\|
586	(ctl & CGEM_RXDESC_CKSUM_STAT_MASK) ==
587	CGEM_RXDESC_CKSUM_STAT_UDP_GOOD) {
588	m->m_pkthdr.csum_flags \|=
589	CSUM_IP_CHECKED \| CSUM_IP_VALID \|
590	CSUM_DATA_VALID \| CSUM_PSEUDO_HDR;
591	m->m_pkthdr.csum_data = 0xffff;
592	} else if ((ctl & CGEM_RXDESC_CKSUM_STAT_MASK) ==
593	CGEM_RXDESC_CKSUM_STAT_IP_GOOD) {
594	/* Only IP checks out. */
595	m->m_pkthdr.csum_flags \|=
596	CSUM_IP_CHECKED \| CSUM_IP_VALID;
597	m->m_pkthdr.csum_data = 0xffff;
598	}
599	}
600
601	/* Queue it up for delivery below. */
602	*m_tl = m;
603	m_tl = &m->m_next;
604	}
605
606	/* Replenish receive buffers. */
607	cgem_fill_rqueue(sc);
608
609	/* Unlock and send up packets. */
610	CGEM_UNLOCK(sc);
611	while (m_hd != NULL) {
612	m = m_hd;
613	m_hd = m_hd->m_next;
614	m->m_next = NULL;
615	#ifndef __rtems__
616	if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
617	#else /* __rtems__ */
618	ifp->if_ipackets++;
619	#endif /* __rtems__ */
620	(*ifp->if_input)(ifp, m);
621	}
622	CGEM_LOCK(sc);
623	}
624
625	/* Find completed transmits and free their mbufs. */
626	static void
627	cgem_clean_tx(struct cgem_softc *sc)
628	{
629	struct mbuf *m;
630	uint32_t ctl;
631
632	CGEM_ASSERT_LOCKED(sc);
633
634	/* free up finished transmits. */
635	while (sc->txring_queued > 0 &&
636	((ctl = sc->txring[sc->txring_tl_ptr].ctl) &
637	CGEM_TXDESC_USED) != 0) {
638
639	/* Sync cache. nop? */
640	bus_dmamap_sync(sc->mbuf_dma_tag,
641	sc->txring_m_dmamap[sc->txring_tl_ptr],
642	BUS_DMASYNC_POSTWRITE);
643
644	/* Unload DMA map. */
645	bus_dmamap_unload(sc->mbuf_dma_tag,
646	sc->txring_m_dmamap[sc->txring_tl_ptr]);
647
648	/* Free up the mbuf. */
649	m = sc->txring_m[sc->txring_tl_ptr];
650	sc->txring_m[sc->txring_tl_ptr] = NULL;
651	m_freem(m);
652
653	/* Check the status. */
654	if ((ctl & CGEM_TXDESC_AHB_ERR) != 0) {
655	/* Serious bus error. log to console. */
656	device_printf(sc->dev, "cgem_clean_tx: Whoa! "
657	"AHB error, addr=0x%x\n",
658	sc->txring[sc->txring_tl_ptr].addr);
659	} else if ((ctl & (CGEM_TXDESC_RETRY_ERR \|
660	CGEM_TXDESC_LATE_COLL)) != 0) {
661	#ifndef __rtems__
662	if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, 1);
663	#else /* __rtems__ */
664	sc->ifp->if_oerrors++;
665	#endif /* __rtems__ */
666	} else
667	#ifndef __rtems__
668	if_inc_counter(sc->ifp, IFCOUNTER_OPACKETS, 1);
669	#else /* __rtems__ */
670	sc->ifp->if_opackets++;
671	#endif /* __rtems__ */
672
673	/* If the packet spanned more than one tx descriptor,
674	* skip descriptors until we find the end so that only
675	* start-of-frame descriptors are processed.
676	*/
677	while ((ctl & CGEM_TXDESC_LAST_BUF) == 0) {
678	if ((ctl & CGEM_TXDESC_WRAP) != 0)
679	sc->txring_tl_ptr = 0;
680	else
681	sc->txring_tl_ptr++;
682	sc->txring_queued--;
683
684	ctl = sc->txring[sc->txring_tl_ptr].ctl;
685
686	sc->txring[sc->txring_tl_ptr].ctl =
687	ctl \| CGEM_TXDESC_USED;
688	}
689
690	/* Next descriptor. */
691	if ((ctl & CGEM_TXDESC_WRAP) != 0)
692	sc->txring_tl_ptr = 0;
693	else
694	sc->txring_tl_ptr++;
695	sc->txring_queued--;
696
697	sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
698	}
699	}
700
701	/* Start transmits. */
702	static void
703	cgem_start_locked(struct ifnet *ifp)
704	{
705	struct cgem_softc sc = (struct cgem_softc ) ifp->if_softc;
706	struct mbuf *m;
707	bus_dma_segment_t segs[TX_MAX_DMA_SEGS];
708	uint32_t ctl;
709	int i, nsegs, wrap, err;
710
711	CGEM_ASSERT_LOCKED(sc);
712
713	if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0)
714	return;
715
716	for (;;) {
717	/* Check that there is room in the descriptor ring. */
718	if (sc->txring_queued >=
719	CGEM_NUM_TX_DESCS - TX_MAX_DMA_SEGS * 2) {
720
721	/* Try to make room. */
722	cgem_clean_tx(sc);
723
724	/* Still no room? */
725	if (sc->txring_queued >=
726	CGEM_NUM_TX_DESCS - TX_MAX_DMA_SEGS * 2) {
727	ifp->if_drv_flags \|= IFF_DRV_OACTIVE;
728	sc->txfull++;
729	break;
730	}
731	}
732
733	/* Grab next transmit packet. */
734	IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
735	if (m == NULL)
736	break;
737
738	/* Load DMA map. */
739	err = bus_dmamap_load_mbuf_sg(sc->mbuf_dma_tag,
740	sc->txring_m_dmamap[sc->txring_hd_ptr],
741	m, segs, &nsegs, BUS_DMA_NOWAIT);
742	if (err == EFBIG) {
743	/* Too many segments! defrag and try again. */
744	struct mbuf *m2 = m_defrag(m, M_NOWAIT);
745
746	if (m2 == NULL) {
747	sc->txdefragfails++;
748	m_freem(m);
749	continue;
750	}
751	m = m2;
752	err = bus_dmamap_load_mbuf_sg(sc->mbuf_dma_tag,
753	sc->txring_m_dmamap[sc->txring_hd_ptr],
754	m, segs, &nsegs, BUS_DMA_NOWAIT);
755	sc->txdefrags++;
756	}
757	if (err) {
758	/* Give up. */
759	m_freem(m);
760	sc->txdmamapfails++;
761	continue;
762	}
763	sc->txring_m[sc->txring_hd_ptr] = m;
764
765	/* Sync tx buffer with cache. */
766	bus_dmamap_sync(sc->mbuf_dma_tag,
767	sc->txring_m_dmamap[sc->txring_hd_ptr],
768	BUS_DMASYNC_PREWRITE);
769
770	/* Set wrap flag if next packet might run off end of ring. */
771	wrap = sc->txring_hd_ptr + nsegs + TX_MAX_DMA_SEGS >=
772	CGEM_NUM_TX_DESCS;
773
774	/* Fill in the TX descriptors back to front so that USED
775	* bit in first descriptor is cleared last.
776	*/
777	for (i = nsegs - 1; i >= 0; i--) {
778	/* Descriptor address. */
779	sc->txring[sc->txring_hd_ptr + i].addr =
780	segs[i].ds_addr;
781
782	/* Descriptor control word. */
783	ctl = segs[i].ds_len;
784	if (i == nsegs - 1) {
785	ctl \|= CGEM_TXDESC_LAST_BUF;
786	if (wrap)
787	ctl \|= CGEM_TXDESC_WRAP;
788	}
789	sc->txring[sc->txring_hd_ptr + i].ctl = ctl;
790
791	if (i != 0)
792	sc->txring_m[sc->txring_hd_ptr + i] = NULL;
793	}
794
795	if (wrap)
796	sc->txring_hd_ptr = 0;
797	else
798	sc->txring_hd_ptr += nsegs;
799	sc->txring_queued += nsegs;
800
801	/* Kick the transmitter. */
802	WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow \|
803	CGEM_NET_CTRL_START_TX);
804
805	/* If there is a BPF listener, bounce a copy to to him. */
806	ETHER_BPF_MTAP(ifp, m);
807	}
808	}
809
810	static void
811	cgem_start(struct ifnet *ifp)
812	{
813	struct cgem_softc sc = (struct cgem_softc ) ifp->if_softc;
814
815	CGEM_LOCK(sc);
816	cgem_start_locked(ifp);
817	CGEM_UNLOCK(sc);
818	}
819
820	static void
821	cgem_poll_hw_stats(struct cgem_softc *sc)
822	{
823	uint32_t n;
824
825	CGEM_ASSERT_LOCKED(sc);
826
827	sc->stats.tx_bytes += RD4(sc, CGEM_OCTETS_TX_BOT);
828	sc->stats.tx_bytes += (uint64_t)RD4(sc, CGEM_OCTETS_TX_TOP) << 32;
829
830	sc->stats.tx_frames += RD4(sc, CGEM_FRAMES_TX);
831	sc->stats.tx_frames_bcast += RD4(sc, CGEM_BCAST_FRAMES_TX);
832	sc->stats.tx_frames_multi += RD4(sc, CGEM_MULTI_FRAMES_TX);
833	sc->stats.tx_frames_pause += RD4(sc, CGEM_PAUSE_FRAMES_TX);
834	sc->stats.tx_frames_64b += RD4(sc, CGEM_FRAMES_64B_TX);
835	sc->stats.tx_frames_65to127b += RD4(sc, CGEM_FRAMES_65_127B_TX);
836	sc->stats.tx_frames_128to255b += RD4(sc, CGEM_FRAMES_128_255B_TX);
837	sc->stats.tx_frames_256to511b += RD4(sc, CGEM_FRAMES_256_511B_TX);
838	sc->stats.tx_frames_512to1023b += RD4(sc, CGEM_FRAMES_512_1023B_TX);
839	sc->stats.tx_frames_1024to1536b += RD4(sc, CGEM_FRAMES_1024_1518B_TX);
840	sc->stats.tx_under_runs += RD4(sc, CGEM_TX_UNDERRUNS);
841
842	n = RD4(sc, CGEM_SINGLE_COLL_FRAMES);
843	sc->stats.tx_single_collisn += n;
844	#ifndef __rtems__
845	if_inc_counter(sc->ifp, IFCOUNTER_COLLISIONS, n);
846	#else /* __rtems__ */
847	sc->ifp->if_collisions += n;
848	#endif /* __rtems__ */
849	n = RD4(sc, CGEM_MULTI_COLL_FRAMES);
850	sc->stats.tx_multi_collisn += n;
851	#ifndef __rtems__
852	if_inc_counter(sc->ifp, IFCOUNTER_COLLISIONS, n);
853	#else /* __rtems__ */
854	sc->ifp->if_collisions += n;
855	#endif /* __rtems__ */
856	n = RD4(sc, CGEM_EXCESSIVE_COLL_FRAMES);
857	sc->stats.tx_excsv_collisn += n;
858	#ifndef __rtems__
859	if_inc_counter(sc->ifp, IFCOUNTER_COLLISIONS, n);
860	#else /* __rtems__ */
861	sc->ifp->if_collisions += n;
862	#endif /* __rtems__ */
863	n = RD4(sc, CGEM_LATE_COLL);
864	sc->stats.tx_late_collisn += n;
865	#ifndef __rtems__
866	if_inc_counter(sc->ifp, IFCOUNTER_COLLISIONS, n);
867	#else /* __rtems__ */
868	sc->ifp->if_collisions += n;
869	#endif /* __rtems__ */
870
871	sc->stats.tx_deferred_frames += RD4(sc, CGEM_DEFERRED_TX_FRAMES);
872	sc->stats.tx_carrier_sense_errs += RD4(sc, CGEM_CARRIER_SENSE_ERRS);
873
874	sc->stats.rx_bytes += RD4(sc, CGEM_OCTETS_RX_BOT);
875	sc->stats.rx_bytes += (uint64_t)RD4(sc, CGEM_OCTETS_RX_TOP) << 32;
876
877	sc->stats.rx_frames += RD4(sc, CGEM_FRAMES_RX);
878	sc->stats.rx_frames_bcast += RD4(sc, CGEM_BCAST_FRAMES_RX);
879	sc->stats.rx_frames_multi += RD4(sc, CGEM_MULTI_FRAMES_RX);
880	sc->stats.rx_frames_pause += RD4(sc, CGEM_PAUSE_FRAMES_RX);
881	sc->stats.rx_frames_64b += RD4(sc, CGEM_FRAMES_64B_RX);
882	sc->stats.rx_frames_65to127b += RD4(sc, CGEM_FRAMES_65_127B_RX);
883	sc->stats.rx_frames_128to255b += RD4(sc, CGEM_FRAMES_128_255B_RX);
884	sc->stats.rx_frames_256to511b += RD4(sc, CGEM_FRAMES_256_511B_RX);
885	sc->stats.rx_frames_512to1023b += RD4(sc, CGEM_FRAMES_512_1023B_RX);
886	sc->stats.rx_frames_1024to1536b += RD4(sc, CGEM_FRAMES_1024_1518B_RX);
887	sc->stats.rx_frames_undersize += RD4(sc, CGEM_UNDERSZ_RX);
888	sc->stats.rx_frames_oversize += RD4(sc, CGEM_OVERSZ_RX);
889	sc->stats.rx_frames_jabber += RD4(sc, CGEM_JABBERS_RX);
890	sc->stats.rx_frames_fcs_errs += RD4(sc, CGEM_FCS_ERRS);
891	sc->stats.rx_frames_length_errs += RD4(sc, CGEM_LENGTH_FIELD_ERRS);
892	sc->stats.rx_symbol_errs += RD4(sc, CGEM_RX_SYMBOL_ERRS);
893	sc->stats.rx_align_errs += RD4(sc, CGEM_ALIGN_ERRS);
894	sc->stats.rx_resource_errs += RD4(sc, CGEM_RX_RESOURCE_ERRS);
895	sc->stats.rx_overrun_errs += RD4(sc, CGEM_RX_OVERRUN_ERRS);
896	sc->stats.rx_ip_hdr_csum_errs += RD4(sc, CGEM_IP_HDR_CKSUM_ERRS);
897	sc->stats.rx_tcp_csum_errs += RD4(sc, CGEM_TCP_CKSUM_ERRS);
898	sc->stats.rx_udp_csum_errs += RD4(sc, CGEM_UDP_CKSUM_ERRS);
899	}
900
901	static void
902	cgem_tick(void *arg)
903	{
904	struct cgem_softc sc = (struct cgem_softc )arg;
905	struct mii_data *mii;
906
907	CGEM_ASSERT_LOCKED(sc);
908
909	/* Poll the phy. */
910	if (sc->miibus != NULL) {
911	mii = device_get_softc(sc->miibus);
912	mii_tick(mii);
913	}
914
915	/* Poll statistics registers. */
916	cgem_poll_hw_stats(sc);
917
918	/* Check for receiver hang. */
919	if (sc->rxhangwar && sc->rx_frames_prev == sc->stats.rx_frames) {
920	/*
921	* Reset receiver logic by toggling RX_EN bit. 1usec
922	* delay is necessary especially when operating at 100mbps
923	* and 10mbps speeds.
924	*/
925	WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow &
926	~CGEM_NET_CTRL_RX_EN);
927	DELAY(1);
928	WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow);
929	}
930	sc->rx_frames_prev = sc->stats.rx_frames;
931
932	/* Next callout in one second. */
933	callout_reset(&sc->tick_ch, hz, cgem_tick, sc);
934	}
935
936	/* Interrupt handler. */
937	static void
938	cgem_intr(void *arg)
939	{
940	struct cgem_softc sc = (struct cgem_softc )arg;
941	uint32_t istatus;
942
943	CGEM_LOCK(sc);
944
945	if ((sc->ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
946	CGEM_UNLOCK(sc);
947	return;
948	}
949
950	/* Read interrupt status and immediately clear the bits. */
951	istatus = RD4(sc, CGEM_INTR_STAT);
952	WR4(sc, CGEM_INTR_STAT, istatus);
953
954	/* Packets received. */
955	if ((istatus & CGEM_INTR_RX_COMPLETE) != 0)
956	cgem_recv(sc);
957
958	/* Free up any completed transmit buffers. */
959	cgem_clean_tx(sc);
960
961	/* Hresp not ok. Something is very bad with DMA. Try to clear. */
962	if ((istatus & CGEM_INTR_HRESP_NOT_OK) != 0) {
963	device_printf(sc->dev, "cgem_intr: hresp not okay! "
964	"rx_status=0x%x\n", RD4(sc, CGEM_RX_STAT));
965	WR4(sc, CGEM_RX_STAT, CGEM_RX_STAT_HRESP_NOT_OK);
966	}
967
968	/* Receiver overrun. */
969	if ((istatus & CGEM_INTR_RX_OVERRUN) != 0) {
970	/* Clear status bit. */
971	WR4(sc, CGEM_RX_STAT, CGEM_RX_STAT_OVERRUN);
972	sc->rxoverruns++;
973	}
974
975	/* Receiver ran out of bufs. */
976	if ((istatus & CGEM_INTR_RX_USED_READ) != 0) {
977	WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow \|
978	CGEM_NET_CTRL_FLUSH_DPRAM_PKT);
979	cgem_fill_rqueue(sc);
980	sc->rxnobufs++;
981	}
982
983	/* Restart transmitter if needed. */
984	if (!IFQ_DRV_IS_EMPTY(&sc->ifp->if_snd))
985	cgem_start_locked(sc->ifp);
986
987	CGEM_UNLOCK(sc);
988	}
989
990	/* Reset hardware. */
991	static void
992	cgem_reset(struct cgem_softc *sc)
993	{
994
995	CGEM_ASSERT_LOCKED(sc);
996
997	WR4(sc, CGEM_NET_CTRL, 0);
998	WR4(sc, CGEM_NET_CFG, 0);
999	WR4(sc, CGEM_NET_CTRL, CGEM_NET_CTRL_CLR_STAT_REGS);
1000	WR4(sc, CGEM_TX_STAT, CGEM_TX_STAT_ALL);
1001	WR4(sc, CGEM_RX_STAT, CGEM_RX_STAT_ALL);
1002	WR4(sc, CGEM_INTR_DIS, CGEM_INTR_ALL);
1003	WR4(sc, CGEM_HASH_BOT, 0);
1004	WR4(sc, CGEM_HASH_TOP, 0);
1005	WR4(sc, CGEM_TX_QBAR, 0); /* manual says do this. */
1006	WR4(sc, CGEM_RX_QBAR, 0);
1007
1008	/* Get management port running even if interface is down. */
1009	WR4(sc, CGEM_NET_CFG,
1010	CGEM_NET_CFG_DBUS_WIDTH_32 \|
1011	CGEM_NET_CFG_MDC_CLK_DIV_64);
1012
1013	sc->net_ctl_shadow = CGEM_NET_CTRL_MGMT_PORT_EN;
1014	WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow);
1015	}
1016
1017	/* Bring up the hardware. */
1018	static void
1019	cgem_config(struct cgem_softc *sc)
1020	{
1021	uint32_t net_cfg;
1022	uint32_t dma_cfg;
1023	u_char *eaddr = IF_LLADDR(sc->ifp);
1024
1025	CGEM_ASSERT_LOCKED(sc);
1026
1027	/* Program Net Config Register. */
1028	net_cfg = CGEM_NET_CFG_DBUS_WIDTH_32 \|
1029	CGEM_NET_CFG_MDC_CLK_DIV_64 \|
1030	CGEM_NET_CFG_FCS_REMOVE \|
1031	CGEM_NET_CFG_RX_BUF_OFFSET(ETHER_ALIGN) \|
1032	CGEM_NET_CFG_GIGE_EN \|
1033	CGEM_NET_CFG_1536RXEN \|
1034	CGEM_NET_CFG_FULL_DUPLEX \|
1035	CGEM_NET_CFG_SPEED100;
1036
1037	/* Enable receive checksum offloading? */
1038	if ((sc->ifp->if_capenable & IFCAP_RXCSUM) != 0)
1039	net_cfg \|= CGEM_NET_CFG_RX_CHKSUM_OFFLD_EN;
1040
1041	WR4(sc, CGEM_NET_CFG, net_cfg);
1042
1043	/* Program DMA Config Register. */
1044	dma_cfg = CGEM_DMA_CFG_RX_BUF_SIZE(MCLBYTES) \|
1045	CGEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL_8K \|
1046	CGEM_DMA_CFG_TX_PKTBUF_MEMSZ_SEL \|
1047	CGEM_DMA_CFG_AHB_FIXED_BURST_LEN_16 \|
1048	CGEM_DMA_CFG_DISC_WHEN_NO_AHB;
1049
1050	/* Enable transmit checksum offloading? */
1051	if ((sc->ifp->if_capenable & IFCAP_TXCSUM) != 0)
1052	dma_cfg \|= CGEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN;
1053
1054	WR4(sc, CGEM_DMA_CFG, dma_cfg);
1055
1056	/* Write the rx and tx descriptor ring addresses to the QBAR regs. */
1057	WR4(sc, CGEM_RX_QBAR, (uint32_t) sc->rxring_physaddr);
1058	WR4(sc, CGEM_TX_QBAR, (uint32_t) sc->txring_physaddr);
1059
1060	/* Enable rx and tx. */
1061	sc->net_ctl_shadow \|= (CGEM_NET_CTRL_TX_EN \| CGEM_NET_CTRL_RX_EN);
1062	WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow);
1063
1064	/* Set receive address in case it changed. */
1065	WR4(sc, CGEM_SPEC_ADDR_LOW(0), (eaddr[3] << 24) \|
1066	(eaddr[2] << 16) \| (eaddr[1] << 8) \| eaddr[0]);
1067	WR4(sc, CGEM_SPEC_ADDR_HI(0), (eaddr[5] << 8) \| eaddr[4]);
1068
1069	/* Set up interrupts. */
1070	WR4(sc, CGEM_INTR_EN,
1071	CGEM_INTR_RX_COMPLETE \| CGEM_INTR_RX_OVERRUN \|
1072	CGEM_INTR_TX_USED_READ \| CGEM_INTR_RX_USED_READ \|
1073	CGEM_INTR_HRESP_NOT_OK);
1074	}
1075
1076	/* Turn on interface and load up receive ring with buffers. */
1077	static void
1078	cgem_init_locked(struct cgem_softc *sc)
1079	{
1080	struct mii_data *mii;
1081
1082	CGEM_ASSERT_LOCKED(sc);
1083
1084	if ((sc->ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1085	return;
1086
1087	cgem_config(sc);
1088	cgem_fill_rqueue(sc);
1089
1090	sc->ifp->if_drv_flags \|= IFF_DRV_RUNNING;
1091	sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1092
1093	mii = device_get_softc(sc->miibus);
1094	mii_mediachg(mii);
1095
1096	callout_reset(&sc->tick_ch, hz, cgem_tick, sc);
1097	}
1098
1099	static void
1100	cgem_init(void *arg)
1101	{
1102	struct cgem_softc sc = (struct cgem_softc )arg;
1103
1104	CGEM_LOCK(sc);
1105	cgem_init_locked(sc);
1106	CGEM_UNLOCK(sc);
1107	}
1108
1109	/* Turn off interface. Free up any buffers in transmit or receive queues. */
1110	static void
1111	cgem_stop(struct cgem_softc *sc)
1112	{
1113	int i;
1114
1115	CGEM_ASSERT_LOCKED(sc);
1116
1117	callout_stop(&sc->tick_ch);
1118
1119	/* Shut down hardware. */
1120	cgem_reset(sc);
1121
1122	/* Clear out transmit queue. */
1123	for (i = 0; i < CGEM_NUM_TX_DESCS; i++) {
1124	sc->txring[i].ctl = CGEM_TXDESC_USED;
1125	sc->txring[i].addr = 0;
1126	if (sc->txring_m[i]) {
1127	bus_dmamap_unload(sc->mbuf_dma_tag,
1128	sc->txring_m_dmamap[i]);
1129	m_freem(sc->txring_m[i]);
1130	sc->txring_m[i] = NULL;
1131	}
1132	}
1133	sc->txring[CGEM_NUM_TX_DESCS - 1].ctl \|= CGEM_TXDESC_WRAP;
1134
1135	sc->txring_hd_ptr = 0;
1136	sc->txring_tl_ptr = 0;
1137	sc->txring_queued = 0;
1138
1139	/* Clear out receive queue. */
1140	for (i = 0; i < CGEM_NUM_RX_DESCS; i++) {
1141	sc->rxring[i].addr = CGEM_RXDESC_OWN;
1142	sc->rxring[i].ctl = 0;
1143	if (sc->rxring_m[i]) {
1144	/* Unload dmamap. */
1145	bus_dmamap_unload(sc->mbuf_dma_tag,
1146	sc->rxring_m_dmamap[sc->rxring_tl_ptr]);
1147
1148	m_freem(sc->rxring_m[i]);
1149	sc->rxring_m[i] = NULL;
1150	}
1151	}
1152	sc->rxring[CGEM_NUM_RX_DESCS - 1].addr \|= CGEM_RXDESC_WRAP;
1153
1154	sc->rxring_hd_ptr = 0;
1155	sc->rxring_tl_ptr = 0;
1156	sc->rxring_queued = 0;
1157
1158	/* Force next statchg or linkchg to program net config register. */
1159	sc->mii_media_active = 0;
1160	}
1161
1162
1163	static int
1164	cgem_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1165	{
1166	struct cgem_softc *sc = ifp->if_softc;
1167	struct ifreq ifr = (struct ifreq )data;
1168	struct mii_data *mii;
1169	int error = 0, mask;
1170
1171	switch (cmd) {
1172	case SIOCSIFFLAGS:
1173	CGEM_LOCK(sc);
1174	if ((ifp->if_flags & IFF_UP) != 0) {
1175	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1176	if (((ifp->if_flags ^ sc->if_old_flags) &
1177	(IFF_PROMISC \| IFF_ALLMULTI)) != 0) {
1178	cgem_rx_filter(sc);
1179	}
1180	} else {
1181	cgem_init_locked(sc);
1182	}
1183	} else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1184	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1185	cgem_stop(sc);
1186	}
1187	sc->if_old_flags = ifp->if_flags;
1188	CGEM_UNLOCK(sc);
1189	break;
1190
1191	case SIOCADDMULTI:
1192	case SIOCDELMULTI:
1193	/* Set up multi-cast filters. */
1194	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1195	CGEM_LOCK(sc);
1196	cgem_rx_filter(sc);
1197	CGEM_UNLOCK(sc);
1198	}
1199	break;
1200
1201	case SIOCSIFMEDIA:
1202	case SIOCGIFMEDIA:
1203	mii = device_get_softc(sc->miibus);
1204	error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1205	break;
1206
1207	case SIOCSIFCAP:
1208	CGEM_LOCK(sc);
1209	mask = ifp->if_capenable ^ ifr->ifr_reqcap;
1210
1211	if ((mask & IFCAP_TXCSUM) != 0) {
1212	if ((ifr->ifr_reqcap & IFCAP_TXCSUM) != 0) {
1213	/* Turn on TX checksumming. */
1214	ifp->if_capenable \|= (IFCAP_TXCSUM \|
1215	IFCAP_TXCSUM_IPV6);
1216	ifp->if_hwassist \|= CGEM_CKSUM_ASSIST;
1217
1218	WR4(sc, CGEM_DMA_CFG,
1219	RD4(sc, CGEM_DMA_CFG) \|
1220	CGEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN);
1221	} else {
1222	/* Turn off TX checksumming. */
1223	ifp->if_capenable &= ~(IFCAP_TXCSUM \|
1224	IFCAP_TXCSUM_IPV6);
1225	ifp->if_hwassist &= ~CGEM_CKSUM_ASSIST;
1226
1227	WR4(sc, CGEM_DMA_CFG,
1228	RD4(sc, CGEM_DMA_CFG) &
1229	~CGEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN);
1230	}
1231	}
1232	if ((mask & IFCAP_RXCSUM) != 0) {
1233	if ((ifr->ifr_reqcap & IFCAP_RXCSUM) != 0) {
1234	/* Turn on RX checksumming. */
1235	ifp->if_capenable \|= (IFCAP_RXCSUM \|
1236	IFCAP_RXCSUM_IPV6);
1237	WR4(sc, CGEM_NET_CFG,
1238	RD4(sc, CGEM_NET_CFG) \|
1239	CGEM_NET_CFG_RX_CHKSUM_OFFLD_EN);
1240	} else {
1241	/* Turn off RX checksumming. */
1242	ifp->if_capenable &= ~(IFCAP_RXCSUM \|
1243	IFCAP_RXCSUM_IPV6);
1244	WR4(sc, CGEM_NET_CFG,
1245	RD4(sc, CGEM_NET_CFG) &
1246	~CGEM_NET_CFG_RX_CHKSUM_OFFLD_EN);
1247	}
1248	}
1249	if ((ifp->if_capenable & (IFCAP_RXCSUM \| IFCAP_TXCSUM)) ==
1250	(IFCAP_RXCSUM \| IFCAP_TXCSUM))
1251	ifp->if_capenable \|= IFCAP_VLAN_HWCSUM;
1252	else
1253	ifp->if_capenable &= ~IFCAP_VLAN_HWCSUM;
1254
1255	CGEM_UNLOCK(sc);
1256	break;
1257	default:
1258	error = ether_ioctl(ifp, cmd, data);
1259	break;
1260	}
1261
1262	return (error);
1263	}
1264
1265	/* MII bus support routines.
1266	*/
1267	static void
1268	cgem_child_detached(device_t dev, device_t child)
1269	{
1270	struct cgem_softc *sc = device_get_softc(dev);
1271
1272	if (child == sc->miibus)
1273	sc->miibus = NULL;
1274	}
1275
1276	static int
1277	cgem_ifmedia_upd(struct ifnet *ifp)
1278	{
1279	struct cgem_softc sc = (struct cgem_softc ) ifp->if_softc;
1280	struct mii_data *mii;
1281	struct mii_softc *miisc;
1282	int error = 0;
1283
1284	mii = device_get_softc(sc->miibus);
1285	CGEM_LOCK(sc);
1286	if ((ifp->if_flags & IFF_UP) != 0) {
1287	LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1288	PHY_RESET(miisc);
1289	error = mii_mediachg(mii);
1290	}
1291	CGEM_UNLOCK(sc);
1292
1293	return (error);
1294	}
1295
1296	static void
1297	cgem_ifmedia_sts(struct ifnet ifp, struct ifmediareq ifmr)
1298	{
1299	struct cgem_softc sc = (struct cgem_softc ) ifp->if_softc;
1300	struct mii_data *mii;
1301
1302	mii = device_get_softc(sc->miibus);
1303	CGEM_LOCK(sc);
1304	mii_pollstat(mii);
1305	ifmr->ifm_active = mii->mii_media_active;
1306	ifmr->ifm_status = mii->mii_media_status;
1307	CGEM_UNLOCK(sc);
1308	}
1309
1310	static int
1311	cgem_miibus_readreg(device_t dev, int phy, int reg)
1312	{
1313	struct cgem_softc *sc = device_get_softc(dev);
1314	int tries, val;
1315
1316	WR4(sc, CGEM_PHY_MAINT,
1317	CGEM_PHY_MAINT_CLAUSE_22 \| CGEM_PHY_MAINT_MUST_10 \|
1318	CGEM_PHY_MAINT_OP_READ \|
1319	(phy << CGEM_PHY_MAINT_PHY_ADDR_SHIFT) \|
1320	(reg << CGEM_PHY_MAINT_REG_ADDR_SHIFT));
1321
1322	/* Wait for completion. */
1323	tries=0;
1324	while ((RD4(sc, CGEM_NET_STAT) & CGEM_NET_STAT_PHY_MGMT_IDLE) == 0) {
1325	DELAY(5);
1326	if (++tries > 200) {
1327	device_printf(dev, "phy read timeout: %d\n", reg);
1328	return (-1);
1329	}
1330	}
1331
1332	val = RD4(sc, CGEM_PHY_MAINT) & CGEM_PHY_MAINT_DATA_MASK;
1333
1334	if (reg == MII_EXTSR)
1335	/*
1336	* MAC does not support half-duplex at gig speeds.
1337	* Let mii(4) exclude the capability.
1338	*/
1339	val &= ~(EXTSR_1000XHDX \| EXTSR_1000THDX);
1340
1341	return (val);
1342	}
1343
1344	static int
1345	cgem_miibus_writereg(device_t dev, int phy, int reg, int data)
1346	{
1347	struct cgem_softc *sc = device_get_softc(dev);
1348	int tries;
1349
1350	WR4(sc, CGEM_PHY_MAINT,
1351	CGEM_PHY_MAINT_CLAUSE_22 \| CGEM_PHY_MAINT_MUST_10 \|
1352	CGEM_PHY_MAINT_OP_WRITE \|
1353	(phy << CGEM_PHY_MAINT_PHY_ADDR_SHIFT) \|
1354	(reg << CGEM_PHY_MAINT_REG_ADDR_SHIFT) \|
1355	(data & CGEM_PHY_MAINT_DATA_MASK));
1356
1357	/* Wait for completion. */
1358	tries = 0;
1359	while ((RD4(sc, CGEM_NET_STAT) & CGEM_NET_STAT_PHY_MGMT_IDLE) == 0) {
1360	DELAY(5);
1361	if (++tries > 200) {
1362	device_printf(dev, "phy write timeout: %d\n", reg);
1363	return (-1);
1364	}
1365	}
1366
1367	return (0);
1368	}
1369
1370	static void
1371	cgem_miibus_statchg(device_t dev)
1372	{
1373	struct cgem_softc *sc = device_get_softc(dev);
1374	struct mii_data *mii = device_get_softc(sc->miibus);
1375
1376	CGEM_ASSERT_LOCKED(sc);
1377
1378	if ((mii->mii_media_status & (IFM_ACTIVE \| IFM_AVALID)) ==
1379	(IFM_ACTIVE \| IFM_AVALID) &&
1380	sc->mii_media_active != mii->mii_media_active)
1381	cgem_mediachange(sc, mii);
1382	}
1383
1384	static void
1385	cgem_miibus_linkchg(device_t dev)
1386	{
1387	struct cgem_softc *sc = device_get_softc(dev);
1388	struct mii_data *mii = device_get_softc(sc->miibus);
1389
1390	CGEM_ASSERT_LOCKED(sc);
1391
1392	if ((mii->mii_media_status & (IFM_ACTIVE \| IFM_AVALID)) ==
1393	(IFM_ACTIVE \| IFM_AVALID) &&
1394	sc->mii_media_active != mii->mii_media_active)
1395	cgem_mediachange(sc, mii);
1396	}
1397
1398	/*
1399	* Overridable weak symbol cgem_set_ref_clk(). This allows platforms to
1400	* provide a function to set the cgem's reference clock.
1401	*/
1402	static int __used
1403	cgem_default_set_ref_clk(int unit, int frequency)
1404	{
1405
1406	return 0;
1407	}
1408	__weak_reference(cgem_default_set_ref_clk, cgem_set_ref_clk);
1409
1410	/* Call to set reference clock and network config bits according to media. */
1411	static void
1412	cgem_mediachange(struct cgem_softc sc, struct mii_data mii)
1413	{
1414	uint32_t net_cfg;
1415	int ref_clk_freq;
1416
1417	CGEM_ASSERT_LOCKED(sc);
1418
1419	/* Update hardware to reflect media. */
1420	net_cfg = RD4(sc, CGEM_NET_CFG);
1421	net_cfg &= ~(CGEM_NET_CFG_SPEED100 \| CGEM_NET_CFG_GIGE_EN \|
1422	CGEM_NET_CFG_FULL_DUPLEX);
1423
1424	switch (IFM_SUBTYPE(mii->mii_media_active)) {
1425	case IFM_1000_T:
1426	net_cfg \|= (CGEM_NET_CFG_SPEED100 \|
1427	CGEM_NET_CFG_GIGE_EN);
1428	ref_clk_freq = 125000000;
1429	break;
1430	case IFM_100_TX:
1431	net_cfg \|= CGEM_NET_CFG_SPEED100;
1432	ref_clk_freq = 25000000;
1433	break;
1434	default:
1435	ref_clk_freq = 2500000;
1436	}
1437
1438	if ((mii->mii_media_active & IFM_FDX) != 0)
1439	net_cfg \|= CGEM_NET_CFG_FULL_DUPLEX;
1440
1441	WR4(sc, CGEM_NET_CFG, net_cfg);
1442
1443	/* Set the reference clock if necessary. */
1444	if (cgem_set_ref_clk(sc->ref_clk_num, ref_clk_freq))
1445	device_printf(sc->dev, "cgem_mediachange: "
1446	"could not set ref clk%d to %d.\n",
1447	sc->ref_clk_num, ref_clk_freq);
1448
1449	sc->mii_media_active = mii->mii_media_active;
1450	}
1451
1452	static void
1453	cgem_add_sysctls(device_t dev)
1454	{
1455	struct cgem_softc *sc = device_get_softc(dev);
1456	struct sysctl_ctx_list *ctx;
1457	struct sysctl_oid_list *child;
1458	struct sysctl_oid *tree;
1459
1460	ctx = device_get_sysctl_ctx(dev);
1461	child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
1462
1463	SYSCTL_ADD_INT(ctx, child, OID_AUTO, "rxbufs", CTLFLAG_RW,
1464	&sc->rxbufs, 0,
1465	"Number receive buffers to provide");
1466
1467	SYSCTL_ADD_INT(ctx, child, OID_AUTO, "rxhangwar", CTLFLAG_RW,
1468	&sc->rxhangwar, 0,
1469	"Enable receive hang work-around");
1470
1471	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_rxoverruns", CTLFLAG_RD,
1472	&sc->rxoverruns, 0,
1473	"Receive overrun events");
1474
1475	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_rxnobufs", CTLFLAG_RD,
1476	&sc->rxnobufs, 0,
1477	"Receive buf queue empty events");
1478
1479	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_rxdmamapfails", CTLFLAG_RD,
1480	&sc->rxdmamapfails, 0,
1481	"Receive DMA map failures");
1482
1483	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_txfull", CTLFLAG_RD,
1484	&sc->txfull, 0,
1485	"Transmit ring full events");
1486
1487	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_txdmamapfails", CTLFLAG_RD,
1488	&sc->txdmamapfails, 0,
1489	"Transmit DMA map failures");
1490
1491	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_txdefrags", CTLFLAG_RD,
1492	&sc->txdefrags, 0,
1493	"Transmit m_defrag() calls");
1494
1495	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_txdefragfails", CTLFLAG_RD,
1496	&sc->txdefragfails, 0,
1497	"Transmit m_defrag() failures");
1498
1499	tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
1500	NULL, "GEM statistics");
1501	child = SYSCTL_CHILDREN(tree);
1502
1503	SYSCTL_ADD_UQUAD(ctx, child, OID_AUTO, "tx_bytes", CTLFLAG_RD,
1504	&sc->stats.tx_bytes, "Total bytes transmitted");
1505
1506	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames", CTLFLAG_RD,
1507	&sc->stats.tx_frames, 0, "Total frames transmitted");
1508	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_bcast", CTLFLAG_RD,
1509	&sc->stats.tx_frames_bcast, 0,
1510	"Number broadcast frames transmitted");
1511	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_multi", CTLFLAG_RD,
1512	&sc->stats.tx_frames_multi, 0,
1513	"Number multicast frames transmitted");
1514	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_pause",
1515	CTLFLAG_RD, &sc->stats.tx_frames_pause, 0,
1516	"Number pause frames transmitted");
1517	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_64b", CTLFLAG_RD,
1518	&sc->stats.tx_frames_64b, 0,
1519	"Number frames transmitted of size 64 bytes or less");
1520	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_65to127b", CTLFLAG_RD,
1521	&sc->stats.tx_frames_65to127b, 0,
1522	"Number frames transmitted of size 65-127 bytes");
1523	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_128to255b",
1524	CTLFLAG_RD, &sc->stats.tx_frames_128to255b, 0,
1525	"Number frames transmitted of size 128-255 bytes");
1526	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_256to511b",
1527	CTLFLAG_RD, &sc->stats.tx_frames_256to511b, 0,
1528	"Number frames transmitted of size 256-511 bytes");
1529	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_512to1023b",
1530	CTLFLAG_RD, &sc->stats.tx_frames_512to1023b, 0,
1531	"Number frames transmitted of size 512-1023 bytes");
1532	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_1024to1536b",
1533	CTLFLAG_RD, &sc->stats.tx_frames_1024to1536b, 0,
1534	"Number frames transmitted of size 1024-1536 bytes");
1535	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_under_runs",
1536	CTLFLAG_RD, &sc->stats.tx_under_runs, 0,
1537	"Number transmit under-run events");
1538	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_single_collisn",
1539	CTLFLAG_RD, &sc->stats.tx_single_collisn, 0,
1540	"Number single-collision transmit frames");
1541	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_multi_collisn",
1542	CTLFLAG_RD, &sc->stats.tx_multi_collisn, 0,
1543	"Number multi-collision transmit frames");
1544	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_excsv_collisn",
1545	CTLFLAG_RD, &sc->stats.tx_excsv_collisn, 0,
1546	"Number excessive collision transmit frames");
1547	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_late_collisn",
1548	CTLFLAG_RD, &sc->stats.tx_late_collisn, 0,
1549	"Number late-collision transmit frames");
1550	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_deferred_frames",
1551	CTLFLAG_RD, &sc->stats.tx_deferred_frames, 0,
1552	"Number deferred transmit frames");
1553	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_carrier_sense_errs",
1554	CTLFLAG_RD, &sc->stats.tx_carrier_sense_errs, 0,
1555	"Number carrier sense errors on transmit");
1556
1557	SYSCTL_ADD_UQUAD(ctx, child, OID_AUTO, "rx_bytes", CTLFLAG_RD,
1558	&sc->stats.rx_bytes, "Total bytes received");
1559
1560	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames", CTLFLAG_RD,
1561	&sc->stats.rx_frames, 0, "Total frames received");
1562	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_bcast",
1563	CTLFLAG_RD, &sc->stats.rx_frames_bcast, 0,
1564	"Number broadcast frames received");
1565	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_multi",
1566	CTLFLAG_RD, &sc->stats.rx_frames_multi, 0,
1567	"Number multicast frames received");
1568	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_pause",
1569	CTLFLAG_RD, &sc->stats.rx_frames_pause, 0,
1570	"Number pause frames received");
1571	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_64b",
1572	CTLFLAG_RD, &sc->stats.rx_frames_64b, 0,
1573	"Number frames received of size 64 bytes or less");
1574	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_65to127b",
1575	CTLFLAG_RD, &sc->stats.rx_frames_65to127b, 0,
1576	"Number frames received of size 65-127 bytes");
1577	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_128to255b",
1578	CTLFLAG_RD, &sc->stats.rx_frames_128to255b, 0,
1579	"Number frames received of size 128-255 bytes");
1580	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_256to511b",
1581	CTLFLAG_RD, &sc->stats.rx_frames_256to511b, 0,
1582	"Number frames received of size 256-511 bytes");
1583	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_512to1023b",
1584	CTLFLAG_RD, &sc->stats.rx_frames_512to1023b, 0,
1585	"Number frames received of size 512-1023 bytes");
1586	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_1024to1536b",
1587	CTLFLAG_RD, &sc->stats.rx_frames_1024to1536b, 0,
1588	"Number frames received of size 1024-1536 bytes");
1589	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_undersize",
1590	CTLFLAG_RD, &sc->stats.rx_frames_undersize, 0,
1591	"Number undersize frames received");
1592	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_oversize",
1593	CTLFLAG_RD, &sc->stats.rx_frames_oversize, 0,
1594	"Number oversize frames received");
1595	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_jabber",
1596	CTLFLAG_RD, &sc->stats.rx_frames_jabber, 0,
1597	"Number jabber frames received");
1598	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_fcs_errs",
1599	CTLFLAG_RD, &sc->stats.rx_frames_fcs_errs, 0,
1600	"Number frames received with FCS errors");
1601	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_length_errs",
1602	CTLFLAG_RD, &sc->stats.rx_frames_length_errs, 0,
1603	"Number frames received with length errors");
1604	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_symbol_errs",
1605	CTLFLAG_RD, &sc->stats.rx_symbol_errs, 0,
1606	"Number receive symbol errors");
1607	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_align_errs",
1608	CTLFLAG_RD, &sc->stats.rx_align_errs, 0,
1609	"Number receive alignment errors");
1610	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_resource_errs",
1611	CTLFLAG_RD, &sc->stats.rx_resource_errs, 0,
1612	"Number frames received when no rx buffer available");
1613	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_overrun_errs",
1614	CTLFLAG_RD, &sc->stats.rx_overrun_errs, 0,
1615	"Number frames received but not copied due to "
1616	"receive overrun");
1617	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_ip_hdr_csum_errs",
1618	CTLFLAG_RD, &sc->stats.rx_ip_hdr_csum_errs, 0,
1619	"Number frames received with IP header checksum "
1620	"errors");
1621	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_tcp_csum_errs",
1622	CTLFLAG_RD, &sc->stats.rx_tcp_csum_errs, 0,
1623	"Number frames received with TCP checksum errors");
1624	SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_udp_csum_errs",
1625	CTLFLAG_RD, &sc->stats.rx_udp_csum_errs, 0,
1626	"Number frames received with UDP checksum errors");
1627	}
1628
1629
1630	static int
1631	cgem_probe(device_t dev)
1632	{
1633
1634	#ifndef __rtems__
1635	if (!ofw_bus_is_compatible(dev, "cadence,gem"))
1636	return (ENXIO);
1637	#endif /* __rtems__ */
1638
1639	device_set_desc(dev, "Cadence CGEM Gigabit Ethernet Interface");
1640	return (0);
1641	}
1642
1643	static int
1644	cgem_attach(device_t dev)
1645	{
1646	struct cgem_softc *sc = device_get_softc(dev);
1647	struct ifnet *ifp = NULL;
1648	#ifndef __rtems__
1649	phandle_t node;
1650	pcell_t cell;
1651	#endif /* __rtems__ */
1652	int rid, err;
1653	u_char eaddr[ETHER_ADDR_LEN];
1654
1655	sc->dev = dev;
1656	CGEM_LOCK_INIT(sc);
1657
1658	#ifndef __rtems__
1659	/* Get reference clock number and base divider from fdt. */
1660	node = ofw_bus_get_node(dev);
1661	sc->ref_clk_num = 0;
1662	if (OF_getprop(node, "ref-clock-num", &cell, sizeof(cell)) > 0)
1663	sc->ref_clk_num = fdt32_to_cpu(cell);
1664	#endif /* __rtems__ */
1665
1666	/* Get memory resource. */
1667	rid = 0;
1668	sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1669	RF_ACTIVE);
1670	if (sc->mem_res == NULL) {
1671	device_printf(dev, "could not allocate memory resources.\n");
1672	return (ENOMEM);
1673	}
1674
1675	/* Get IRQ resource. */
1676	rid = 0;
1677	sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1678	RF_ACTIVE);
1679	if (sc->irq_res == NULL) {
1680	device_printf(dev, "could not allocate interrupt resource.\n");
1681	cgem_detach(dev);
1682	return (ENOMEM);
1683	}
1684
1685	/* Set up ifnet structure. */
1686	ifp = sc->ifp = if_alloc(IFT_ETHER);
1687	if (ifp == NULL) {
1688	device_printf(dev, "could not allocate ifnet structure\n");
1689	cgem_detach(dev);
1690	return (ENOMEM);
1691	}
1692	ifp->if_softc = sc;
1693	if_initname(ifp, IF_CGEM_NAME, device_get_unit(dev));
1694	ifp->if_flags = IFF_BROADCAST \| IFF_SIMPLEX \| IFF_MULTICAST;
1695	ifp->if_start = cgem_start;
1696	ifp->if_ioctl = cgem_ioctl;
1697	ifp->if_init = cgem_init;
1698	ifp->if_capabilities \|= IFCAP_HWCSUM \| IFCAP_HWCSUM_IPV6 \|
1699	IFCAP_VLAN_MTU \| IFCAP_VLAN_HWCSUM;
1700	/* Disable hardware checksumming by default. */
1701	ifp->if_hwassist = 0;
1702	ifp->if_capenable = ifp->if_capabilities &
1703	~(IFCAP_HWCSUM \| IFCAP_HWCSUM_IPV6 \| IFCAP_VLAN_HWCSUM);
1704	ifp->if_snd.ifq_drv_maxlen = CGEM_NUM_TX_DESCS;
1705	IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
1706	IFQ_SET_READY(&ifp->if_snd);
1707
1708	sc->if_old_flags = ifp->if_flags;
1709	sc->rxbufs = DEFAULT_NUM_RX_BUFS;
1710	sc->rxhangwar = 1;
1711
1712	/* Reset hardware. */
1713	CGEM_LOCK(sc);
1714	cgem_reset(sc);
1715	CGEM_UNLOCK(sc);
1716
1717	/* Attach phy to mii bus. */
1718	err = mii_attach(dev, &sc->miibus, ifp,
1719	cgem_ifmedia_upd, cgem_ifmedia_sts,
1720	BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
1721	if (err) {
1722	device_printf(dev, "attaching PHYs failed\n");
1723	cgem_detach(dev);
1724	return (err);
1725	}
1726
1727	/* Set up TX and RX descriptor area. */
1728	err = cgem_setup_descs(sc);
1729	if (err) {
1730	device_printf(dev, "could not set up dma mem for descs.\n");
1731	cgem_detach(dev);
1732	return (ENOMEM);
1733	}
1734
1735	/* Get a MAC address. */
1736	cgem_get_mac(sc, eaddr);
1737
1738	/* Start ticks. */
1739	callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0);
1740
1741	ether_ifattach(ifp, eaddr);
1742
1743	err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET \| INTR_MPSAFE \|
1744	INTR_EXCL, NULL, cgem_intr, sc, &sc->intrhand);
1745	if (err) {
1746	device_printf(dev, "could not set interrupt handler.\n");
1747	ether_ifdetach(ifp);
1748	cgem_detach(dev);
1749	return (err);
1750	}
1751
1752	cgem_add_sysctls(dev);
1753
1754	return (0);
1755	}
1756
1757	static int
1758	cgem_detach(device_t dev)
1759	{
1760	struct cgem_softc *sc = device_get_softc(dev);
1761	int i;
1762
1763	if (sc == NULL)
1764	return (ENODEV);
1765
1766	if (device_is_attached(dev)) {
1767	CGEM_LOCK(sc);
1768	cgem_stop(sc);
1769	CGEM_UNLOCK(sc);
1770	callout_drain(&sc->tick_ch);
1771	sc->ifp->if_flags &= ~IFF_UP;
1772	ether_ifdetach(sc->ifp);
1773	}
1774
1775	if (sc->miibus != NULL) {
1776	device_delete_child(dev, sc->miibus);
1777	sc->miibus = NULL;
1778	}
1779
1780	/* Release resources. */
1781	if (sc->mem_res != NULL) {
1782	bus_release_resource(dev, SYS_RES_MEMORY,
1783	rman_get_rid(sc->mem_res), sc->mem_res);
1784	sc->mem_res = NULL;
1785	}
1786	if (sc->irq_res != NULL) {
1787	if (sc->intrhand)
1788	bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
1789	bus_release_resource(dev, SYS_RES_IRQ,
1790	rman_get_rid(sc->irq_res), sc->irq_res);
1791	sc->irq_res = NULL;
1792	}
1793
1794	/* Release DMA resources. */
1795	if (sc->rxring != NULL) {
1796	if (sc->rxring_physaddr != 0) {
1797	bus_dmamap_unload(sc->desc_dma_tag, sc->rxring_dma_map);
1798	sc->rxring_physaddr = 0;
1799	}
1800	bus_dmamem_free(sc->desc_dma_tag, sc->rxring,
1801	sc->rxring_dma_map);
1802	sc->rxring = NULL;
1803	for (i = 0; i < CGEM_NUM_RX_DESCS; i++)
1804	if (sc->rxring_m_dmamap[i] != NULL) {
1805	bus_dmamap_destroy(sc->mbuf_dma_tag,
1806	sc->rxring_m_dmamap[i]);
1807	sc->rxring_m_dmamap[i] = NULL;
1808	}
1809	}
1810	if (sc->txring != NULL) {
1811	if (sc->txring_physaddr != 0) {
1812	bus_dmamap_unload(sc->desc_dma_tag, sc->txring_dma_map);
1813	sc->txring_physaddr = 0;
1814	}
1815	bus_dmamem_free(sc->desc_dma_tag, sc->txring,
1816	sc->txring_dma_map);
1817	sc->txring = NULL;
1818	for (i = 0; i < CGEM_NUM_TX_DESCS; i++)
1819	if (sc->txring_m_dmamap[i] != NULL) {
1820	bus_dmamap_destroy(sc->mbuf_dma_tag,
1821	sc->txring_m_dmamap[i]);
1822	sc->txring_m_dmamap[i] = NULL;
1823	}
1824	}
1825	if (sc->desc_dma_tag != NULL) {
1826	bus_dma_tag_destroy(sc->desc_dma_tag);
1827	sc->desc_dma_tag = NULL;
1828	}
1829	if (sc->mbuf_dma_tag != NULL) {
1830	bus_dma_tag_destroy(sc->mbuf_dma_tag);
1831	sc->mbuf_dma_tag = NULL;
1832	}
1833
1834	bus_generic_detach(dev);
1835
1836	CGEM_LOCK_DESTROY(sc);
1837
1838	return (0);
1839	}
1840
1841	static device_method_t cgem_methods[] = {
1842	/* Device interface */
1843	DEVMETHOD(device_probe, cgem_probe),
1844	DEVMETHOD(device_attach, cgem_attach),
1845	DEVMETHOD(device_detach, cgem_detach),
1846
1847	/* Bus interface */
1848	DEVMETHOD(bus_child_detached, cgem_child_detached),
1849
1850	/* MII interface */
1851	DEVMETHOD(miibus_readreg, cgem_miibus_readreg),
1852	DEVMETHOD(miibus_writereg, cgem_miibus_writereg),
1853	DEVMETHOD(miibus_statchg, cgem_miibus_statchg),
1854	DEVMETHOD(miibus_linkchg, cgem_miibus_linkchg),
1855
1856	DEVMETHOD_END
1857	};
1858
1859	static driver_t cgem_driver = {
1860	"cgem",
1861	cgem_methods,
1862	sizeof(struct cgem_softc),
1863	};
1864
1865	DRIVER_MODULE(cgem, simplebus, cgem_driver, cgem_devclass, NULL, NULL);
1866	DRIVER_MODULE(miibus, cgem, miibus_driver, miibus_devclass, NULL, NULL);
1867	MODULE_DEPEND(cgem, miibus, 1, 1, 1);
1868	MODULE_DEPEND(cgem, ether, 1, 1, 1);

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