source: rtems-libbsd/freebsd/sys/arm/xilinx/zy7_slcr.c @ dae9f66

4.115-freebsd-12freebsd-9.3
Last change on this file since dae9f66 was dae9f66, checked in by Sebastian Huber <sebastian.huber@…>, on Nov 25, 2014 at 1:37:22 PM

zy7_slcr: Import from FreeBSD

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File size: 12.1 KB
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1#include <machine/rtems-bsd-kernel-space.h>
2
3/*-
4 * Copyright (c) 2013 Thomas Skibo
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD$
29 */
30
31/*
32 * Zynq-700 SLCR driver.  Provides hooks for cpu_reset and PL control stuff.
33 * In the future, maybe MIO control, clock control, etc. could go here.
34 *
35 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
36 * (v1.4) November 16, 2012.  Xilinx doc UG585.
37 */
38
39#include <sys/cdefs.h>
40__FBSDID("$FreeBSD$");
41
42#include <rtems/bsd/sys/param.h>
43#include <sys/systm.h>
44#ifdef __rtems__
45#include <sys/bus.h>
46#endif /* __rtems__ */
47#include <sys/conf.h>
48#include <sys/kernel.h>
49#include <sys/module.h>
50#include <rtems/bsd/sys/lock.h>
51#include <sys/mutex.h>
52#include <rtems/bsd/sys/resource.h>
53#include <sys/sysctl.h>
54#include <sys/rman.h>
55
56#include <machine/bus.h>
57#include <machine/resource.h>
58#include <machine/stdarg.h>
59
60#ifndef __rtems__
61#include <dev/fdt/fdt_common.h>
62#include <dev/ofw/ofw_bus.h>
63#include <dev/ofw/ofw_bus_subr.h>
64#endif /* __rtems__ */
65
66#include <arm/xilinx/zy7_slcr.h>
67
68struct zy7_slcr_softc {
69        device_t        dev;
70        struct mtx      sc_mtx;
71        struct resource *mem_res;
72};
73
74static struct zy7_slcr_softc *zy7_slcr_softc_p;
75#ifndef __rtems__
76extern void (*zynq7_cpu_reset);
77#endif /* __rtems__ */
78
79#define ZSLCR_LOCK(sc)          mtx_lock(&(sc)->sc_mtx)
80#define ZSLCR_UNLOCK(sc)                mtx_unlock(&(sc)->sc_mtx)
81#define ZSLCR_LOCK_INIT(sc) \
82        mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \
83            "zy7_slcr", MTX_DEF)
84#define ZSLCR_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
85
86#define RD4(sc, off)            (bus_read_4((sc)->mem_res, (off)))
87#define WR4(sc, off, val)       (bus_write_4((sc)->mem_res, (off), (val)))
88
89#define ZYNQ_DEFAULT_PS_CLK_FREQUENCY   33333333        /* 33.3 Mhz */
90
91
92SYSCTL_NODE(_hw, OID_AUTO, zynq, CTLFLAG_RD, 0, "Xilinx Zynq-7000");
93
94static char zynq_bootmode[64];
95SYSCTL_STRING(_hw_zynq, OID_AUTO, bootmode, CTLFLAG_RD, zynq_bootmode, 0,
96              "Zynq boot mode");
97
98static char zynq_pssid[100];
99SYSCTL_STRING(_hw_zynq, OID_AUTO, pssid, CTLFLAG_RD, zynq_pssid, 0,
100           "Zynq PSS IDCODE");
101
102static uint32_t zynq_reboot_status;
103SYSCTL_INT(_hw_zynq, OID_AUTO, reboot_status, CTLFLAG_RD, &zynq_reboot_status,
104           0, "Zynq REBOOT_STATUS register");
105
106static int ps_clk_frequency;
107SYSCTL_INT(_hw_zynq, OID_AUTO, ps_clk_frequency, CTLFLAG_RD, &ps_clk_frequency,
108           0, "Zynq PS_CLK Frequency");
109
110static int io_pll_frequency;
111SYSCTL_INT(_hw_zynq, OID_AUTO, io_pll_frequency, CTLFLAG_RD, &io_pll_frequency,
112           0, "Zynq IO PLL Frequency");
113
114static int arm_pll_frequency;
115SYSCTL_INT(_hw_zynq, OID_AUTO, arm_pll_frequency, CTLFLAG_RD,
116           &arm_pll_frequency, 0, "Zynq ARM PLL Frequency");
117
118static int ddr_pll_frequency;
119SYSCTL_INT(_hw_zynq, OID_AUTO, ddr_pll_frequency, CTLFLAG_RD,
120           &ddr_pll_frequency, 0, "Zynq DDR PLL Frequency");
121
122static void
123zy7_slcr_unlock(struct zy7_slcr_softc *sc)
124{
125
126        /* Unlock SLCR with magic number. */
127        WR4(sc, ZY7_SLCR_UNLOCK, ZY7_SLCR_UNLOCK_MAGIC);
128}
129
130static void
131zy7_slcr_lock(struct zy7_slcr_softc *sc)
132{
133
134        /* Lock SLCR with magic number. */
135        WR4(sc, ZY7_SLCR_LOCK, ZY7_SLCR_LOCK_MAGIC);
136}
137
138
139#ifndef __rtems__
140static void
141zy7_slcr_cpu_reset(void)
142{
143        struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
144
145        /* Unlock SLCR registers. */
146        zy7_slcr_unlock(sc);
147
148        /* This has something to do with a work-around so the fsbl will load
149         * the bitstream after soft-reboot.  It's very important.
150         */
151        WR4(sc, ZY7_SLCR_REBOOT_STAT,
152            RD4(sc, ZY7_SLCR_REBOOT_STAT) & 0xf0ffffff);
153
154        /* Soft reset */
155        WR4(sc, ZY7_SLCR_PSS_RST_CTRL, ZY7_SLCR_PSS_RST_CTRL_SOFT_RESET);
156
157        for (;;)
158                ;
159}
160
161/* Assert PL resets and disable level shifters in preparation of programming
162 * the PL (FPGA) section.  Called from zy7_devcfg.c.
163 */
164void
165zy7_slcr_preload_pl(void)
166{
167        struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
168
169        if (!sc)
170                return;
171
172        ZSLCR_LOCK(sc);
173
174        /* Unlock SLCR registers. */
175        zy7_slcr_unlock(sc);
176
177        /* Assert top level output resets. */
178        WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, ZY7_SLCR_FPGA_RST_CTRL_RST_ALL);
179
180        /* Disable all level shifters. */
181        WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, 0);
182
183        /* Lock SLCR registers. */
184        zy7_slcr_lock(sc);
185
186        ZSLCR_UNLOCK(sc);
187}
188
189/* After PL configuration, enable level shifters and deassert top-level
190 * PL resets.  Called from zy7_devcfg.c.  Optionally, the level shifters
191 * can be left disabled but that's rare of an FPGA application. That option
192 * is controled by a sysctl in the devcfg driver.
193 */
194void
195zy7_slcr_postload_pl(int en_level_shifters)
196{
197        struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
198
199        if (!sc)
200                return;
201
202        ZSLCR_LOCK(sc);
203
204        /* Unlock SLCR registers. */
205        zy7_slcr_unlock(sc);
206
207        if (en_level_shifters)
208                /* Enable level shifters. */
209                WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, ZY7_SLCR_LVL_SHFTR_EN_ALL);
210
211        /* Deassert top level output resets. */
212        WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, 0);
213
214        /* Lock SLCR registers. */
215        zy7_slcr_lock(sc);
216
217        ZSLCR_UNLOCK(sc);
218}
219#endif /* __rtems__ */
220
221/* Override cgem_set_refclk() in gigabit ethernet driver
222 * (sys/dev/cadence/if_cgem.c).  This function is called to
223 * request a change in the gem's reference clock speed.
224 */
225int
226cgem_set_ref_clk(int unit, int frequency)
227{
228        struct zy7_slcr_softc *sc = zy7_slcr_softc_p;
229        int div0, div1;
230
231        if (!sc)
232                return (-1);
233
234        /* Find suitable divisor pairs.  Round result to nearest khz
235         * to test for match.
236         */
237        for (div1 = 1; div1 <= ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX; div1++) {
238                div0 = (io_pll_frequency + div1 * frequency / 2) /
239                        div1 / frequency;
240                if (div0 > 0 && div0 <= ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_MAX &&
241                    ((io_pll_frequency / div0 / div1) + 500) / 1000 ==
242                    (frequency + 500) / 1000)
243                        break;
244        }
245
246        if (div1 > ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX)
247                return (-1);
248
249        ZSLCR_LOCK(sc);
250
251        /* Unlock SLCR registers. */
252        zy7_slcr_unlock(sc);
253
254        /* Modify GEM reference clock. */
255        WR4(sc, unit ? ZY7_SLCR_GEM1_CLK_CTRL : ZY7_SLCR_GEM0_CLK_CTRL,
256            (div1 << ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_SHIFT) |
257            (div0 << ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_SHIFT) |
258            ZY7_SLCR_GEM_CLK_CTRL_SRCSEL_IO_PLL |
259            ZY7_SLCR_GEM_CLK_CTRL_CLKACT);
260
261        /* Lock SLCR registers. */
262        zy7_slcr_lock(sc);
263
264        ZSLCR_UNLOCK(sc);
265
266        return (0);
267}
268
269static int
270zy7_slcr_probe(device_t dev)
271{
272
273#ifndef __rtems__
274        if (!ofw_bus_status_okay(dev))
275                return (ENXIO);
276
277        if (!ofw_bus_is_compatible(dev, "xlnx,zy7_slcr"))
278                return (ENXIO);
279#endif /* __rtems__ */
280
281        device_set_desc(dev, "Zynq-7000 slcr block");
282        return (0);
283}
284
285static int
286zy7_slcr_attach(device_t dev)
287{
288        struct zy7_slcr_softc *sc = device_get_softc(dev);
289        int rid;
290#ifndef __rtems__
291        phandle_t node;
292        pcell_t cell;
293#endif /* __rtems__ */
294        uint32_t bootmode;
295        uint32_t pss_idcode;
296        uint32_t arm_pll_ctrl;
297        uint32_t ddr_pll_ctrl;
298        uint32_t io_pll_ctrl;
299        static char *bootdev_names[] = {
300                "JTAG", "Quad-SPI", "NOR", "(3?)",
301                "NAND", "SD Card", "(6?)", "(7?)"
302        };
303
304        /* Allow only one attach. */
305        if (zy7_slcr_softc_p != NULL)
306                return (ENXIO);
307
308        sc->dev = dev;
309
310        ZSLCR_LOCK_INIT(sc);
311
312        /* Get memory resource. */
313        rid = 0;
314        sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
315                                             RF_ACTIVE);
316        if (sc->mem_res == NULL) {
317                device_printf(dev, "could not allocate memory resources.\n");
318                return (ENOMEM);
319        }
320
321        /* Hook up cpu_reset. */
322        zy7_slcr_softc_p = sc;
323#ifndef __rtems__
324        zynq7_cpu_reset = zy7_slcr_cpu_reset;
325#endif /* __rtems__ */
326
327        /* Read info and set sysctls. */
328        bootmode = RD4(sc, ZY7_SLCR_BOOT_MODE);
329        snprintf(zynq_bootmode, sizeof(zynq_bootmode),
330                 "0x%x: boot device: %s", bootmode,
331                 bootdev_names[bootmode & ZY7_SLCR_BOOT_MODE_BOOTDEV_MASK]);
332
333        pss_idcode = RD4(sc, ZY7_SLCR_PSS_IDCODE);
334        snprintf(zynq_pssid, sizeof(zynq_pssid),
335                 "0x%x: manufacturer: 0x%x device: 0x%x "
336                 "family: 0x%x sub-family: 0x%x rev: 0x%x",
337                 pss_idcode,
338                 (pss_idcode & ZY7_SLCR_PSS_IDCODE_MNFR_ID_MASK) >>
339                 ZY7_SLCR_PSS_IDCODE_MNFR_ID_SHIFT,
340                 (pss_idcode & ZY7_SLCR_PSS_IDCODE_DEVICE_MASK) >>
341                 ZY7_SLCR_PSS_IDCODE_DEVICE_SHIFT,
342                 (pss_idcode & ZY7_SLCR_PSS_IDCODE_FAMILY_MASK) >>
343                 ZY7_SLCR_PSS_IDCODE_FAMILY_SHIFT,
344                 (pss_idcode & ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_MASK) >>
345                 ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_SHIFT,
346                 (pss_idcode & ZY7_SLCR_PSS_IDCODE_REVISION_MASK) >>
347                 ZY7_SLCR_PSS_IDCODE_REVISION_SHIFT);
348
349        zynq_reboot_status = RD4(sc, ZY7_SLCR_REBOOT_STAT);
350
351        /* Derive PLL frequencies from PS_CLK. */
352#ifndef __rtems__
353        node = ofw_bus_get_node(dev);
354        if (OF_getprop(node, "clock-frequency", &cell, sizeof(cell)) > 0)
355                ps_clk_frequency = fdt32_to_cpu(cell);
356        else
357#endif /* __rtems__ */
358                ps_clk_frequency = ZYNQ_DEFAULT_PS_CLK_FREQUENCY;
359
360        arm_pll_ctrl = RD4(sc, ZY7_SLCR_ARM_PLL_CTRL);
361        ddr_pll_ctrl = RD4(sc, ZY7_SLCR_DDR_PLL_CTRL);
362        io_pll_ctrl = RD4(sc, ZY7_SLCR_IO_PLL_CTRL);
363
364        /* Determine ARM PLL frequency. */
365        if (((arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) == 0 &&
366             (arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_FORCE) != 0) ||
367            ((arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) != 0 &&
368             (bootmode & ZY7_SLCR_BOOT_MODE_PLL_BYPASS) != 0))
369                /* PLL is bypassed. */
370                arm_pll_frequency = ps_clk_frequency;
371        else
372                arm_pll_frequency = ps_clk_frequency *
373                        ((arm_pll_ctrl & ZY7_SLCR_PLL_CTRL_FDIV_MASK) >>
374                         ZY7_SLCR_PLL_CTRL_FDIV_SHIFT);
375
376        /* Determine DDR PLL frequency. */
377        if (((ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) == 0 &&
378             (ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_FORCE) != 0) ||
379            ((ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) != 0 &&
380             (bootmode & ZY7_SLCR_BOOT_MODE_PLL_BYPASS) != 0))
381                /* PLL is bypassed. */
382                ddr_pll_frequency = ps_clk_frequency;
383        else
384                ddr_pll_frequency = ps_clk_frequency *
385                        ((ddr_pll_ctrl & ZY7_SLCR_PLL_CTRL_FDIV_MASK) >>
386                         ZY7_SLCR_PLL_CTRL_FDIV_SHIFT);
387
388        /* Determine IO PLL frequency. */
389        if (((io_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) == 0 &&
390             (io_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_FORCE) != 0) ||
391            ((io_pll_ctrl & ZY7_SLCR_PLL_CTRL_BYPASS_QUAL) != 0 &&
392             (bootmode & ZY7_SLCR_BOOT_MODE_PLL_BYPASS) != 0))
393                /* PLL is bypassed. */
394                io_pll_frequency = ps_clk_frequency;
395        else
396                io_pll_frequency = ps_clk_frequency *
397                        ((io_pll_ctrl & ZY7_SLCR_PLL_CTRL_FDIV_MASK) >>
398                         ZY7_SLCR_PLL_CTRL_FDIV_SHIFT);
399
400        /* Lock SLCR registers. */
401        zy7_slcr_lock(sc);
402
403        return (0);
404}
405
406static int
407zy7_slcr_detach(device_t dev)
408{
409        struct zy7_slcr_softc *sc = device_get_softc(dev);
410
411        bus_generic_detach(dev);
412
413        /* Release memory resource. */
414        if (sc->mem_res != NULL)
415                bus_release_resource(dev, SYS_RES_MEMORY,
416                             rman_get_rid(sc->mem_res), sc->mem_res);
417
418        zy7_slcr_softc_p = NULL;
419#ifndef __rtems__
420        zynq7_cpu_reset = NULL;
421#endif /* __rtems__ */
422
423        ZSLCR_LOCK_DESTROY(sc);
424
425        return (0);
426}
427
428static device_method_t zy7_slcr_methods[] = {
429        /* device_if */
430        DEVMETHOD(device_probe,         zy7_slcr_probe),
431        DEVMETHOD(device_attach,        zy7_slcr_attach),
432        DEVMETHOD(device_detach,        zy7_slcr_detach),
433
434        DEVMETHOD_END
435};
436
437static driver_t zy7_slcr_driver = {
438        "zy7_slcr",
439        zy7_slcr_methods,
440        sizeof(struct zy7_slcr_softc),
441};
442static devclass_t zy7_slcr_devclass;
443
444#ifndef __rtems__
445DRIVER_MODULE(zy7_slcr, simplebus, zy7_slcr_driver, zy7_slcr_devclass, 0, 0);
446#else /* __rtems__ */
447DRIVER_MODULE(zy7_slcr, nexus, zy7_slcr_driver, zy7_slcr_devclass, 0, 0);
448#endif /* __rtems__ */
449MODULE_VERSION(zy7_slcr, 1);
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