1 | /*- |
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2 | * Copyright (c) 2005 Olivier Houchard. All rights reserved. |
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3 | * |
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4 | * Redistribution and use in source and binary forms, with or without |
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5 | * modification, are permitted provided that the following conditions |
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6 | * are met: |
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7 | * 1. Redistributions of source code must retain the above copyright |
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8 | * notice, this list of conditions and the following disclaimer. |
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9 | * 2. Redistributions in binary form must reproduce the above copyright |
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10 | * notice, this list of conditions and the following disclaimer in the |
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11 | * documentation and/or other materials provided with the distribution. |
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12 | * |
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13 | * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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14 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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15 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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16 | * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE |
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17 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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18 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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19 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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20 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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21 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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22 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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23 | * SUCH DAMAGE. |
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24 | */ |
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25 | |
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26 | /* $FreeBSD$ */ |
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27 | |
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28 | #ifndef _AT91VAR_H_ |
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29 | #define _AT91VAR_H_ |
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30 | |
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31 | #include <sys/bus.h> |
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32 | #include <sys/rman.h> |
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33 | |
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34 | #include <arm/at91/at91reg.h> |
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35 | |
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36 | struct at91_softc { |
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37 | device_t dev; |
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38 | bus_space_tag_t sc_st; |
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39 | bus_space_handle_t sc_sh; |
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40 | bus_space_handle_t sc_aic_sh; |
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41 | struct rman sc_irq_rman; |
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42 | struct rman sc_mem_rman; |
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43 | }; |
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44 | |
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45 | struct at91_ivar { |
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46 | struct resource_list resources; |
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47 | }; |
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48 | |
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49 | struct cpu_devs |
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50 | { |
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51 | const char *name; |
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52 | int unit; |
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53 | bus_addr_t mem_base; |
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54 | bus_size_t mem_len; |
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55 | int irq0; |
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56 | int irq1; |
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57 | int irq2; |
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58 | const char *parent_clk; |
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59 | }; |
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60 | |
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61 | enum at91_soc_type { |
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62 | AT91_T_NONE = 0, |
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63 | AT91_T_CAP9, |
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64 | AT91_T_RM9200, |
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65 | AT91_T_SAM9260, |
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66 | AT91_T_SAM9261, |
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67 | AT91_T_SAM9263, |
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68 | AT91_T_SAM9G10, |
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69 | AT91_T_SAM9G20, |
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70 | AT91_T_SAM9G45, |
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71 | AT91_T_SAM9N12, |
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72 | AT91_T_SAM9RL, |
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73 | AT91_T_SAM9X5, |
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74 | }; |
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75 | |
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76 | enum at91_soc_subtype { |
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77 | AT91_ST_ANY = -1, /* Match any type */ |
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78 | AT91_ST_NONE = 0, |
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79 | /* AT91RM9200 */ |
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80 | AT91_ST_RM9200_BGA, |
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81 | AT91_ST_RM9200_PQFP, |
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82 | /* AT91SAM9260 */ |
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83 | AT91_ST_SAM9XE, |
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84 | /* AT91SAM9G45 */ |
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85 | AT91_ST_SAM9G45, |
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86 | AT91_ST_SAM9M10, |
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87 | AT91_ST_SAM9G46, |
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88 | AT91_ST_SAM9M11, |
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89 | /* AT91SAM9X5 */ |
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90 | AT91_ST_SAM9G15, |
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91 | AT91_ST_SAM9G25, |
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92 | AT91_ST_SAM9G35, |
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93 | AT91_ST_SAM9X25, |
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94 | AT91_ST_SAM9X35, |
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95 | }; |
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96 | |
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97 | enum at91_soc_family { |
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98 | AT91_FAMILY_SAM9 = 0x19, |
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99 | AT91_FAMILY_SAM9XE = 0x29, |
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100 | AT91_FAMILY_RM92 = 0x92, |
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101 | }; |
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102 | |
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103 | #define AT91_SOC_NAME_MAX 50 |
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104 | |
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105 | typedef void (*DELAY_t)(int); |
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106 | typedef void (*cpu_reset_t)(void); |
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107 | typedef void (*clk_init_t)(void); |
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108 | |
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109 | struct at91_soc_data { |
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110 | DELAY_t soc_delay; /* SoC specific delay function */ |
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111 | cpu_reset_t soc_reset; /* SoC specific reset function */ |
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112 | clk_init_t soc_clock_init; /* SoC specific clock init function */ |
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113 | const int *soc_irq_prio; /* SoC specific IRQ priorities */ |
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114 | const struct cpu_devs *soc_children; /* SoC specific children list */ |
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115 | const uint32_t *soc_pio_base; /* SoC specific PIO base registers */ |
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116 | size_t soc_pio_count; /* Count of PIO units (not pins) in SoC */ |
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117 | }; |
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118 | |
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119 | struct at91_soc_info { |
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120 | enum at91_soc_type type; |
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121 | enum at91_soc_subtype subtype; |
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122 | enum at91_soc_family family; |
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123 | uint32_t cidr; |
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124 | uint32_t exid; |
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125 | char name[AT91_SOC_NAME_MAX]; |
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126 | uint32_t dbgu_base; |
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127 | struct at91_soc_data *soc_data; |
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128 | }; |
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129 | |
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130 | extern struct at91_soc_info soc_info; |
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131 | |
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132 | static inline int at91_is_rm92(void); |
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133 | static inline int at91_is_sam9(void); |
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134 | static inline int at91_is_sam9xe(void); |
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135 | static inline int at91_cpu_is(u_int cpu); |
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136 | |
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137 | static inline int |
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138 | at91_is_rm92(void) |
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139 | { |
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140 | |
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141 | return (soc_info.type == AT91_T_RM9200); |
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142 | } |
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143 | |
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144 | static inline int |
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145 | at91_is_sam9(void) |
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146 | { |
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147 | |
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148 | return (soc_info.family == AT91_FAMILY_SAM9); |
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149 | } |
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150 | |
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151 | static inline int |
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152 | at91_is_sam9xe(void) |
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153 | { |
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154 | |
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155 | return (soc_info.family == AT91_FAMILY_SAM9XE); |
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156 | } |
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157 | |
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158 | static inline int |
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159 | at91_cpu_is(u_int cpu) |
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160 | { |
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161 | |
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162 | return (soc_info.type == cpu); |
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163 | } |
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164 | |
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165 | void at91_add_child(device_t dev, int prio, const char *name, int unit, |
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166 | bus_addr_t addr, bus_size_t size, int irq0, int irq1, int irq2); |
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167 | |
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168 | extern uint32_t at91_irq_system; |
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169 | extern uint32_t at91_master_clock; |
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170 | void at91_pmc_init_clock(void); |
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171 | void at91_soc_id(void); |
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172 | |
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173 | #endif /* _AT91VAR_H_ */ |
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