source: rtems-libbsd/freebsd/sys/arm/at91/at91_mci.c @ ef5d536

5-freebsd-12
Last change on this file since ef5d536 was ef5d536, checked in by Sebastian Huber <sebastian.huber@…>, on Apr 27, 2018 at 8:14:44 AM

at91_mci: Simplify XDMA usage

  • Property mode set to 100644
File size: 50.2 KB
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1#include <machine/rtems-bsd-kernel-space.h>
2
3/*-
4 * Copyright (c) 2006 Bernd Walter.  All rights reserved.
5 * Copyright (c) 2006 M. Warner Losh.  All rights reserved.
6 * Copyright (c) 2010 Greg Ansley.  All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30#include <rtems/bsd/local/opt_platform.h>
31
32#include <sys/cdefs.h>
33__FBSDID("$FreeBSD$");
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/bus.h>
38#include <sys/endian.h>
39#include <sys/kernel.h>
40#include <sys/lock.h>
41#include <sys/malloc.h>
42#include <sys/module.h>
43#include <sys/mutex.h>
44#include <rtems/bsd/sys/resource.h>
45#include <sys/rman.h>
46#include <sys/sysctl.h>
47
48#include <machine/bus.h>
49#include <machine/resource.h>
50#include <machine/intr.h>
51
52#include <arm/at91/at91var.h>
53#include <arm/at91/at91_mcireg.h>
54#include <arm/at91/at91_pdcreg.h>
55
56#include <dev/mmc/bridge.h>
57#include <dev/mmc/mmcbrvar.h>
58
59#ifdef FDT
60#include <dev/ofw/ofw_bus.h>
61#include <dev/ofw/ofw_bus_subr.h>
62#endif
63
64#include <rtems/bsd/local/mmcbr_if.h>
65
66#include <rtems/bsd/local/opt_at91.h>
67
68#ifdef __rtems__
69#include <bsp.h>
70#endif /* __rtems__ */
71#if defined(__rtems__) && defined(LIBBSP_ARM_ATSAM_BSP_H)
72#ifdef __rtems__
73#include <rtems/irq-extension.h>
74#include <libchip/chip.h>
75
76#define AT91_MCI_HAS_4WIRE 1
77
78#define at91_master_clock BOARD_MCK
79
80static sXdmad *pXdmad = &XDMAD_Instance;
81#endif /* __rtems__ */
82/*
83 * About running the MCI bus above 25MHz
84 *
85 * Historically, the MCI bus has been run at 30MHz on systems with a 60MHz
86 * master clock, in part due to a bug in dev/mmc.c making always request
87 * 30MHz, and in part over clocking the bus because 15MHz was too slow.
88 * Fixing that bug causes the mmc driver to request a 25MHz clock (as it
89 * should) and the logic in at91_mci_update_ios() picks the highest speed that
90 * doesn't exceed that limit.  With a 60MHz MCK that would be 15MHz, and
91 * that's a real performance buzzkill when you've been getting away with 30MHz
92 * all along.
93 *
94 * By defining AT91_MCI_ALLOW_OVERCLOCK (or setting the allow_overclock=1
95 * device hint or sysctl) you can enable logic in at91_mci_update_ios() to
96 * overlcock the SD bus a little by running it at MCK / 2 when the requested
97 * speed is 25MHz and the next highest speed is 15MHz or less.  This appears
98 * to work on virtually all SD cards, since it is what this driver has been
99 * doing prior to the introduction of this option, where the overclocking vs
100 * underclocking decision was automatically "overclock".  Modern SD cards can
101 * run at 45mhz/1-bit in standard mode (high speed mode enable commands not
102 * sent) without problems.
103 *
104 * Speaking of high-speed mode, the rm9200 manual says the MCI device supports
105 * the SD v1.0 specification and can run up to 50MHz.  This is interesting in
106 * that the SD v1.0 spec caps the speed at 25MHz; high speed mode was added in
107 * the v1.10 spec.  Furthermore, high speed mode doesn't just crank up the
108 * clock, it alters the signal timing.  The rm9200 MCI device doesn't support
109 * these altered timings.  So while speeds over 25MHz may work, they only work
110 * in what the SD spec calls "default" speed mode, and it amounts to violating
111 * the spec by overclocking the bus.
112 *
113 * If you also enable 4-wire mode it's possible transfers faster than 25MHz
114 * will fail.  On the AT91RM9200, due to bugs in the bus contention logic, if
115 * you have the USB host device and OHCI driver enabled will fail.  Even
116 * underclocking to 15MHz, intermittant overrun and underrun errors occur.
117 * Note that you don't even need to have usb devices attached to the system,
118 * the errors begin to occur as soon as the OHCI driver sets the register bit
119 * to enable periodic transfers.  It appears (based on brief investigation)
120 * that the usb host controller uses so much ASB bandwidth that sometimes the
121 * DMA for MCI transfers doesn't get a bus grant in time and data gets
122 * dropped.  Adding even a modicum of network activity changes the symptom
123 * from intermittant to very frequent.  Members of the AT91SAM9 family have
124 * corrected this problem, or are at least better about their use of the bus.
125 */
126#ifndef AT91_MCI_ALLOW_OVERCLOCK
127#define AT91_MCI_ALLOW_OVERCLOCK 1
128#endif
129
130/*
131 * Allocate 2 bounce buffers we'll use to endian-swap the data due to the rm9200
132 * erratum.  We use a pair of buffers because when reading that lets us begin
133 * endian-swapping the data in the first buffer while the DMA is reading into
134 * the second buffer.  (We can't use the same trick for writing because we might
135 * not get all the data in the 2nd buffer swapped before the hardware needs it;
136 * dealing with that would add complexity to the driver.)
137 *
138 * The buffers are sized at 16K each due to the way the busdma cache sync
139 * operations work on arm.  A dcache_inv_range() operation on a range larger
140 * than 16K gets turned into a dcache_wbinv_all().  That needlessly flushes the
141 * entire data cache, impacting overall system performance.
142 */
143#ifndef __rtems__
144#define BBCOUNT     2
145#define BBSIZE      (32*1024)
146#define MAX_BLOCKS  ((BBSIZE)/512)
147/* FIXME: It would be better to split the DMA up in that case like in the
148 * original driver. But that would need some rework. */
149#else /* __rtems__ */
150#define MAX_BLOCKS 256
151#endif /* __rtems__ */
152
153#ifndef __rtems__
154static int mci_debug;
155#else /* __rtems__ */
156#define mci_debug 0
157#endif /* __rtems__ */
158
159struct at91_mci_softc {
160        void *intrhand;                 /* Interrupt handle */
161        device_t dev;
162        int sc_cap;
163#define CAP_HAS_4WIRE           1       /* Has 4 wire bus */
164#define CAP_NEEDS_BYTESWAP      2       /* broken hardware needing bounce */
165#define CAP_MCI1_REV2XX         4       /* MCI 1 rev 2.x */
166        int flags;
167#define PENDING_CMD     0x01
168#define PENDING_STOP    0x02
169#define CMD_MULTIREAD   0x10
170#define CMD_MULTIWRITE  0x20
171        int has_4wire;
172        int allow_overclock;
173        struct resource *irq_res;       /* IRQ resource */
174        struct resource *mem_res;       /* Memory resource */
175        struct mtx sc_mtx;
176#ifdef __rtems__
177        RTEMS_INTERRUPT_LOCK_MEMBER(sc_lock)
178#endif /* __rtems__ */
179#ifndef __rtems__
180        bus_dma_tag_t dmatag;
181#endif /* __rtems__ */
182        struct mmc_host host;
183        int bus_busy;
184        struct mmc_request *req;
185        struct mmc_command *curcmd;
186#ifndef __rtems__
187        bus_dmamap_t bbuf_map[BBCOUNT];
188        char      *  bbuf_vaddr[BBCOUNT]; /* bounce bufs in KVA space */
189        uint32_t     bbuf_len[BBCOUNT];   /* len currently queued for bounce buf */
190        uint32_t     bbuf_curidx;         /* which bbuf is the active DMA buffer */
191        uint32_t     xfer_offset;         /* offset so far into caller's buf */
192#else /* __rtems__ */
193        LinkedListDescriporView1 xdma_desc;
194        uint32_t xdma_tx_channel;
195        uint32_t xdma_rx_channel;
196        uint8_t xdma_tx_perid;
197        uint8_t xdma_rx_perid;
198        sXdmadCfg xdma_tx_cfg;
199        sXdmadCfg xdma_rx_cfg;
200#endif /* __rtems__ */
201};
202
203/* bus entry points */
204static int at91_mci_probe(device_t dev);
205static int at91_mci_attach(device_t dev);
206static int at91_mci_detach(device_t dev);
207static void at91_mci_intr(void *);
208
209/* helper routines */
210static int at91_mci_activate(device_t dev);
211static void at91_mci_deactivate(device_t dev);
212static int at91_mci_is_mci1rev2xx(void);
213#ifndef __rtems__
214static void at91_mci_read_done(struct at91_mci_softc *sc, uint32_t sr);
215#endif /* __rtems__ */
216static void at91_mci_write_done(struct at91_mci_softc *sc, uint32_t sr);
217
218#ifndef __rtems__
219#define AT91_MCI_LOCK(_sc)              mtx_lock(&(_sc)->sc_mtx)
220#define AT91_MCI_UNLOCK(_sc)            mtx_unlock(&(_sc)->sc_mtx)
221#define AT91_MCI_LOCK_INIT(_sc) \
222        mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \
223            "mci", MTX_DEF)
224#define AT91_MCI_LOCK_DESTROY(_sc)      mtx_destroy(&_sc->sc_mtx);
225#define AT91_MCI_ASSERT_LOCKED(_sc)     mtx_assert(&_sc->sc_mtx, MA_OWNED);
226#define AT91_MCI_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
227#else /* __rtems__ */
228#define AT91_MCI_LOCK(_sc) \
229        rtems_interrupt_lock_context at91_mci_lock_context; \
230        rtems_interrupt_lock_acquire(&(_sc)->sc_lock, &at91_mci_lock_context)
231#define AT91_MCI_UNLOCK(_sc) \
232        rtems_interrupt_lock_release(&(_sc)->sc_lock, &at91_mci_lock_context)
233#define AT91_MCI_LOCK_INIT(_sc) \
234        rtems_interrupt_lock_initialize(&(_sc)->sc_lock, \
235            device_get_nameunit((_sc)->dev))
236#define AT91_MCI_LOCK_DESTROY(_sc) \
237        rtems_interrupt_lock_destroy(&(_sc)->sc_mtx)
238#define AT91_MCI_BUS_LOCK(_sc)          mtx_lock(&(_sc)->sc_mtx)
239#define AT91_MCI_BUS_UNLOCK(_sc)                mtx_unlock(&(_sc)->sc_mtx)
240#define AT91_MCI_BUS_LOCK_INIT(_sc) \
241        mtx_init(&_sc->sc_mtx, device_get_nameunit((_sc)->dev), \
242            "mci", MTX_DEF)
243#endif /* __rtems__ */
244
245static inline uint32_t
246RD4(struct at91_mci_softc *sc, bus_size_t off)
247{
248        return (bus_read_4(sc->mem_res, off));
249}
250
251static inline void
252WR4(struct at91_mci_softc *sc, bus_size_t off, uint32_t val)
253{
254        bus_write_4(sc->mem_res, off, val);
255}
256
257#ifndef __rtems__
258static void
259at91_bswap_buf(struct at91_mci_softc *sc, void * dptr, void * sptr, uint32_t memsize)
260{
261        uint32_t * dst = (uint32_t *)dptr;
262        uint32_t * src = (uint32_t *)sptr;
263        uint32_t   i;
264
265        /*
266         * If the hardware doesn't need byte-swapping, let bcopy() do the
267         * work.  Use bounce buffer even if we don't need byteswap, since
268         * buffer may straddle a page boundary, and we don't handle
269         * multi-segment transfers in hardware.  Seen from 'bsdlabel -w' which
270         * uses raw geom access to the volume.  Greg Ansley (gja (at)
271         * ansley.com)
272         */
273        if (!(sc->sc_cap & CAP_NEEDS_BYTESWAP)) {
274                memcpy(dptr, sptr, memsize);
275                return;
276        }
277
278        /*
279         * Nice performance boost for slightly unrolling this loop.
280         * (But very little extra boost for further unrolling it.)
281         */
282        for (i = 0; i < memsize; i += 16) {
283                *dst++ = bswap32(*src++);
284                *dst++ = bswap32(*src++);
285                *dst++ = bswap32(*src++);
286                *dst++ = bswap32(*src++);
287        }
288
289        /* Mop up the last 1-3 words, if any. */
290        for (i = 0; i < (memsize & 0x0F); i += 4) {
291                *dst++ = bswap32(*src++);
292        }
293}
294
295static void
296at91_mci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
297{
298        if (error != 0)
299                return;
300        *(bus_addr_t *)arg = segs[0].ds_addr;
301}
302#endif /* __rtems__ */
303
304static void
305at91_mci_pdc_disable(struct at91_mci_softc *sc)
306{
307#ifndef __rtems__
308        WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS);
309        WR4(sc, PDC_RPR, 0);
310        WR4(sc, PDC_RCR, 0);
311        WR4(sc, PDC_RNPR, 0);
312        WR4(sc, PDC_RNCR, 0);
313        WR4(sc, PDC_TPR, 0);
314        WR4(sc, PDC_TCR, 0);
315        WR4(sc, PDC_TNPR, 0);
316        WR4(sc, PDC_TNCR, 0);
317#else /* __rtems__ */
318        /* On SAMV71 there is no PDC but a DMAC */
319        XDMAD_StopTransfer(pXdmad, sc->xdma_rx_channel);
320        XDMAD_StopTransfer(pXdmad, sc->xdma_tx_channel);
321        WR4(sc, MCI_DMA, 0);
322#endif /* __rtems__ */
323}
324
325/*
326 * Reset the controller, then restore most of the current state.
327 *
328 * This is called after detecting an error.  It's also called after stopping a
329 * multi-block write, to un-wedge the device so that it will handle the NOTBUSY
330 * signal correctly.  See comments in at91_mci_stop_done() for more details.
331 */
332static void at91_mci_reset(struct at91_mci_softc *sc)
333{
334        uint32_t mr;
335        uint32_t sdcr;
336        uint32_t dtor;
337        uint32_t imr;
338
339        at91_mci_pdc_disable(sc);
340
341        /* save current state */
342
343        imr  = RD4(sc, MCI_IMR);
344#ifndef __rtems__
345        mr   = RD4(sc, MCI_MR) & 0x7fff;
346#else /* __rtems__ */
347        mr   = RD4(sc, MCI_MR);
348#endif /* __rtems__ */
349        sdcr = RD4(sc, MCI_SDCR);
350        dtor = RD4(sc, MCI_DTOR);
351
352        /* reset the controller */
353
354        WR4(sc, MCI_IDR, 0xffffffff);
355        WR4(sc, MCI_CR, MCI_CR_MCIDIS | MCI_CR_SWRST);
356
357        /* restore state */
358
359        WR4(sc, MCI_CR, MCI_CR_MCIEN|MCI_CR_PWSEN);
360        WR4(sc, MCI_MR, mr);
361        WR4(sc, MCI_SDCR, sdcr);
362        WR4(sc, MCI_DTOR, dtor);
363        WR4(sc, MCI_IER, imr);
364
365        /*
366         * Make sure sdio interrupts will fire.  Not sure why reading
367         * SR ensures that, but this is in the linux driver.
368         */
369
370        RD4(sc, MCI_SR);
371}
372
373static void
374at91_mci_init(device_t dev)
375{
376        struct at91_mci_softc *sc = device_get_softc(dev);
377        uint32_t val;
378
379        WR4(sc, MCI_CR, MCI_CR_MCIDIS | MCI_CR_SWRST); /* device into reset */
380        WR4(sc, MCI_IDR, 0xffffffff);           /* Turn off interrupts */
381        WR4(sc, MCI_DTOR, MCI_DTOR_DTOMUL_1M | 1);
382#ifndef __rtems__
383        val = MCI_MR_PDCMODE;
384#else /* __rtems__ */
385        val = 0;
386        val |= MCI_MR_RDPROOF | MCI_MR_WRPROOF;
387#endif /* __rtems__ */
388        val |= 0x34a;                           /* PWSDIV = 3; CLKDIV = 74 */
389//      if (sc->sc_cap & CAP_MCI1_REV2XX)
390//              val |= MCI_MR_RDPROOF | MCI_MR_WRPROOF;
391        WR4(sc, MCI_MR, val);
392#ifndef  AT91_MCI_SLOT_B
393        WR4(sc, MCI_SDCR, 0);                   /* SLOT A, 1 bit bus */
394#else
395        /*
396         * XXX Really should add second "unit" but nobody using using
397         * a two slot card that we know of. XXX
398         */
399        WR4(sc, MCI_SDCR, 1);                   /* SLOT B, 1 bit bus */
400#endif
401        /*
402         * Enable controller, including power-save.  The slower clock
403         * of the power-save mode is only in effect when there is no
404         * transfer in progress, so it can be left in this mode all
405         * the time.
406         */
407        WR4(sc, MCI_CR, MCI_CR_MCIEN|MCI_CR_PWSEN);
408}
409
410static void
411at91_mci_fini(device_t dev)
412{
413        struct at91_mci_softc *sc = device_get_softc(dev);
414
415        WR4(sc, MCI_IDR, 0xffffffff);           /* Turn off interrupts */
416        at91_mci_pdc_disable(sc);
417        WR4(sc, MCI_CR, MCI_CR_MCIDIS | MCI_CR_SWRST); /* device into reset */
418}
419
420static int
421at91_mci_probe(device_t dev)
422{
423#ifdef FDT
424        if (!ofw_bus_is_compatible(dev, "atmel,hsmci"))
425                return (ENXIO);
426#endif
427        device_set_desc(dev, "MCI mmc/sd host bridge");
428        return (0);
429}
430
431static int
432at91_mci_attach(device_t dev)
433{
434        struct at91_mci_softc *sc = device_get_softc(dev);
435        struct sysctl_ctx_list *sctx;
436        struct sysctl_oid *soid;
437        device_t child;
438#ifndef __rtems__
439        int err, i;
440#else /* __rtems__ */
441        int err;
442#endif /* __rtems__ */
443
444#ifdef __rtems__
445#ifdef LIBBSP_ARM_ATSAM_BSP_H
446        PMC_EnablePeripheral(ID_HSMCI);
447        sc->xdma_tx_channel = XDMAD_ALLOC_FAILED;
448        sc->xdma_rx_channel = XDMAD_ALLOC_FAILED;
449#endif /* LIBBSP_ARM_ATSAM_BSP_H */
450#endif /* __rtems__ */
451        sctx = device_get_sysctl_ctx(dev);
452        soid = device_get_sysctl_tree(dev);
453
454        sc->dev = dev;
455        sc->sc_cap = 0;
456#ifndef __rtems__
457        if (at91_is_rm92())
458                sc->sc_cap |= CAP_NEEDS_BYTESWAP;
459#endif /* __rtems__ */
460        /*
461         * MCI1 Rev 2 controllers need some workarounds, flag if so.
462         */
463        if (at91_mci_is_mci1rev2xx())
464                sc->sc_cap |= CAP_MCI1_REV2XX;
465
466        err = at91_mci_activate(dev);
467        if (err)
468                goto out;
469
470#ifdef __rtems__
471        eXdmadRC rc;
472
473        /* Prepare some configurations so they don't have to be fetched on every
474         * setup */
475        sc->xdma_rx_perid = XDMAIF_Get_ChannelNumber(ID_HSMCI,
476            XDMAD_TRANSFER_RX);
477        sc->xdma_tx_perid = XDMAIF_Get_ChannelNumber(ID_HSMCI,
478            XDMAD_TRANSFER_TX);
479        memset(&sc->xdma_rx_cfg, 0, sizeof(sc->xdma_rx_cfg));
480        sc->xdma_rx_cfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN |
481            XDMAC_CC_MBSIZE_SINGLE | XDMAC_CC_DSYNC_PER2MEM |
482            XDMAC_CC_SWREQ_HWR_CONNECTED | XDMAC_CC_MEMSET_NORMAL_MODE |
483            XDMAC_CC_CSIZE_CHK_1 | XDMAC_CC_DWIDTH_WORD |
484            XDMAC_CC_SIF_AHB_IF1 | XDMAC_CC_DIF_AHB_IF1 |
485            XDMAC_CC_SAM_FIXED_AM | XDMAC_CC_DAM_INCREMENTED_AM |
486            XDMAC_CC_PERID(
487                XDMAIF_Get_ChannelNumber(ID_HSMCI,XDMAD_TRANSFER_RX));
488        memset(&sc->xdma_tx_cfg, 0, sizeof(sc->xdma_tx_cfg));
489        sc->xdma_tx_cfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN |
490            XDMAC_CC_MBSIZE_SINGLE | XDMAC_CC_DSYNC_MEM2PER |
491            XDMAC_CC_SWREQ_HWR_CONNECTED | XDMAC_CC_MEMSET_NORMAL_MODE |
492            XDMAC_CC_CSIZE_CHK_1 | XDMAC_CC_DWIDTH_WORD |
493            XDMAC_CC_SIF_AHB_IF1 | XDMAC_CC_DIF_AHB_IF1 |
494            XDMAC_CC_SAM_INCREMENTED_AM | XDMAC_CC_DAM_FIXED_AM |
495            XDMAC_CC_PERID(
496                XDMAIF_Get_ChannelNumber(ID_HSMCI,XDMAD_TRANSFER_TX));
497
498        sc->xdma_tx_channel = XDMAD_AllocateChannel(pXdmad,
499            XDMAD_TRANSFER_MEMORY, ID_HSMCI);
500        if (sc->xdma_tx_channel == XDMAD_ALLOC_FAILED)
501                goto out;
502
503        /* FIXME: The two DMA channels are not really necessary for the driver.
504         * But the XDMAD interface does not allow to allocate one and use it
505         * into two directions. The current (2017-07-11) implementation of
506         * the XDMAD interface should work with it. So we might could try it. */
507        sc->xdma_rx_channel = XDMAD_AllocateChannel(pXdmad, ID_HSMCI,
508            XDMAD_TRANSFER_MEMORY);
509        if (sc->xdma_rx_channel == XDMAD_ALLOC_FAILED)
510                goto out;
511
512        rc = XDMAD_PrepareChannel(pXdmad, sc->xdma_rx_channel);
513        if (rc != XDMAD_OK)
514                goto out;
515
516        rc = XDMAD_PrepareChannel(pXdmad, sc->xdma_tx_channel);
517        if (rc != XDMAD_OK)
518                goto out;
519
520        AT91_MCI_BUS_LOCK_INIT(sc);
521#endif /* __rtems__ */
522        AT91_MCI_LOCK_INIT(sc);
523
524        at91_mci_fini(dev);
525        at91_mci_init(dev);
526
527#ifndef __rtems__
528        /*
529         * Allocate DMA tags and maps and bounce buffers.
530         *
531         * The parms in the tag_create call cause the dmamem_alloc call to
532         * create each bounce buffer as a single contiguous buffer of BBSIZE
533         * bytes aligned to a 4096 byte boundary.
534         *
535         * Do not use DMA_COHERENT for these buffers because that maps the
536         * memory as non-cachable, which prevents cache line burst fills/writes,
537         * which is something we need since we're trying to overlap the
538         * byte-swapping with the DMA operations.
539         */
540        err = bus_dma_tag_create(bus_get_dma_tag(dev), 4096, 0,
541            BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
542            BBSIZE, 1, BBSIZE, 0, NULL, NULL, &sc->dmatag);
543        if (err != 0)
544                goto out;
545
546        for (i = 0; i < BBCOUNT; ++i) {
547                err = bus_dmamem_alloc(sc->dmatag, (void **)&sc->bbuf_vaddr[i],
548                    BUS_DMA_NOWAIT, &sc->bbuf_map[i]);
549                if (err != 0)
550                        goto out;
551        }
552
553        /*
554         * Activate the interrupt
555         */
556        err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
557            NULL, at91_mci_intr, sc, &sc->intrhand);
558#else /* __rtems__ */
559        err = rtems_interrupt_handler_install(rman_get_start(sc->irq_res),
560            device_get_nameunit(dev), RTEMS_INTERRUPT_SHARED, at91_mci_intr,
561            sc);
562#endif /* __rtems__ */
563        if (err) {
564                AT91_MCI_LOCK_DESTROY(sc);
565                goto out;
566        }
567
568        /*
569         * Allow 4-wire to be initially set via #define.
570         * Allow a device hint to override that.
571         * Allow a sysctl to override that.
572         */
573#if defined(AT91_MCI_HAS_4WIRE) && AT91_MCI_HAS_4WIRE != 0
574        sc->has_4wire = 1;
575#endif
576        resource_int_value(device_get_name(dev), device_get_unit(dev),
577                           "4wire", &sc->has_4wire);
578        SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "4wire",
579            CTLFLAG_RW, &sc->has_4wire, 0, "has 4 wire SD Card bus");
580        if (sc->has_4wire)
581                sc->sc_cap |= CAP_HAS_4WIRE;
582
583        sc->allow_overclock = AT91_MCI_ALLOW_OVERCLOCK;
584        resource_int_value(device_get_name(dev), device_get_unit(dev),
585                           "allow_overclock", &sc->allow_overclock);
586        SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "allow_overclock",
587            CTLFLAG_RW, &sc->allow_overclock, 0,
588            "Allow up to 30MHz clock for 25MHz request when next highest speed 15MHz or less.");
589
590#ifndef __rtems__
591        SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "debug",
592            CTLFLAG_RWTUN, &mci_debug, 0, "enable debug output");
593#endif /* __rtems__ */
594
595        /*
596         * Our real min freq is master_clock/512, but upper driver layers are
597         * going to set the min speed during card discovery, and the right speed
598         * for that is 400kHz, so advertise a safe value just under that.
599         *
600         * For max speed, while the rm9200 manual says the max is 50mhz, it also
601         * says it supports only the SD v1.0 spec, which means the real limit is
602         * 25mhz. On the other hand, historical use has been to slightly violate
603         * the standard by running the bus at 30MHz.  For more information on
604         * that, see the comments at the top of this file.
605         */
606        sc->host.f_min = 375000;
607        sc->host.f_max = at91_master_clock / 2;
608        if (sc->host.f_max > 25000000)
609                sc->host.f_max = 25000000;
610        sc->host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340;
611        sc->host.caps = 0;
612        if (sc->sc_cap & CAP_HAS_4WIRE)
613                sc->host.caps |= MMC_CAP_4_BIT_DATA;
614
615        child = device_add_child(dev, "mmc", 0);
616#ifdef __rtems__
617        (void)child;
618#endif /* __rtems__ */
619        device_set_ivars(dev, &sc->host);
620        err = bus_generic_attach(dev);
621out:
622        if (err)
623                at91_mci_deactivate(dev);
624        return (err);
625}
626
627static int
628at91_mci_detach(device_t dev)
629{
630#ifndef __rtems__
631        struct at91_mci_softc *sc = device_get_softc(dev);
632#endif /* __rtems__ */
633
634        at91_mci_fini(dev);
635        at91_mci_deactivate(dev);
636
637#ifndef __rtems__
638        bus_dmamem_free(sc->dmatag, sc->bbuf_vaddr[0], sc->bbuf_map[0]);
639        bus_dmamem_free(sc->dmatag, sc->bbuf_vaddr[1], sc->bbuf_map[1]);
640        bus_dma_tag_destroy(sc->dmatag);
641#endif /* __rtems__ */
642
643        return (EBUSY); /* XXX */
644}
645
646static int
647at91_mci_activate(device_t dev)
648{
649        struct at91_mci_softc *sc;
650        int rid;
651
652        sc = device_get_softc(dev);
653        rid = 0;
654        sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
655            RF_ACTIVE);
656        if (sc->mem_res == NULL)
657                goto errout;
658
659        rid = 0;
660        sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
661            RF_ACTIVE);
662        if (sc->irq_res == NULL)
663                goto errout;
664
665        return (0);
666errout:
667        at91_mci_deactivate(dev);
668        return (ENOMEM);
669}
670
671static void
672at91_mci_deactivate(device_t dev)
673{
674        struct at91_mci_softc *sc;
675
676        sc = device_get_softc(dev);
677        if (sc->intrhand)
678                bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
679        sc->intrhand = NULL;
680        bus_generic_detach(sc->dev);
681        if (sc->mem_res)
682                bus_release_resource(dev, SYS_RES_MEMORY,
683                    rman_get_rid(sc->mem_res), sc->mem_res);
684        sc->mem_res = NULL;
685        if (sc->irq_res)
686                bus_release_resource(dev, SYS_RES_IRQ,
687                    rman_get_rid(sc->irq_res), sc->irq_res);
688        sc->irq_res = NULL;
689#ifdef __rtems__
690        if (sc->xdma_rx_channel != XDMAD_ALLOC_FAILED) {
691                XDMAD_FreeChannel(pXdmad, sc->xdma_rx_channel);
692        }
693        if (sc->xdma_tx_channel != XDMAD_ALLOC_FAILED) {
694                XDMAD_FreeChannel(pXdmad, sc->xdma_tx_channel);
695        }
696#endif /* __rtems__ */
697        return;
698}
699
700static int
701at91_mci_is_mci1rev2xx(void)
702{
703
704#ifndef __rtems__
705        switch (soc_info.type) {
706        case AT91_T_SAM9260:
707        case AT91_T_SAM9263:
708        case AT91_T_CAP9:
709        case AT91_T_SAM9G10:
710        case AT91_T_SAM9G20:
711        case AT91_T_SAM9RL:
712                return(1);
713        default:
714                return (0);
715        }
716#else /* __rtems__ */
717        /* Currently only supports the SAM V71 */
718        return (1);
719#endif /* __rtems__ */
720}
721
722static int
723at91_mci_update_ios(device_t brdev, device_t reqdev)
724{
725        struct at91_mci_softc *sc;
726        struct mmc_ios *ios;
727        uint32_t clkdiv;
728        uint32_t freq;
729
730        sc = device_get_softc(brdev);
731        ios = &sc->host.ios;
732
733        /*
734         * Calculate our closest available clock speed that doesn't exceed the
735         * requested speed.
736         *
737         * When overclocking is allowed, the requested clock is 25MHz, the
738         * computed frequency is 15MHz or smaller and clockdiv is 1, use
739         * clockdiv of 0 to double that.  If less than 12.5MHz, double
740         * regardless of the overclocking setting.
741         *
742         * Whatever we come up with, store it back into ios->clock so that the
743         * upper layer drivers can report the actual speed of the bus.
744         */
745        if (ios->clock == 0) {
746                WR4(sc, MCI_CR, MCI_CR_MCIDIS);
747                clkdiv = 0;
748        } else {
749                WR4(sc, MCI_CR, MCI_CR_MCIEN|MCI_CR_PWSEN);
750                if ((at91_master_clock % (ios->clock * 2)) == 0)
751                        clkdiv = ((at91_master_clock / ios->clock) / 2) - 1;
752                else
753                        clkdiv = (at91_master_clock / ios->clock) / 2;
754                freq = at91_master_clock / ((clkdiv+1) * 2);
755                if (clkdiv == 1 && ios->clock == 25000000 && freq <= 15000000) {
756                        if (sc->allow_overclock || freq <= 12500000) {
757                                clkdiv = 0;
758                                freq = at91_master_clock / ((clkdiv+1) * 2);
759                        }
760                }
761                ios->clock = freq;
762        }
763        if (ios->bus_width == bus_width_4)
764                WR4(sc, MCI_SDCR, RD4(sc, MCI_SDCR) | MCI_SDCR_SDCBUS);
765        else
766                WR4(sc, MCI_SDCR, RD4(sc, MCI_SDCR) & ~MCI_SDCR_SDCBUS);
767        WR4(sc, MCI_MR, (RD4(sc, MCI_MR) & ~MCI_MR_CLKDIV) | clkdiv);
768        /* Do we need a settle time here? */
769        /* XXX We need to turn the device on/off here with a GPIO pin */
770        return (0);
771}
772
773#ifdef __rtems__
774static void
775at91_mci_setup_xdma(struct at91_mci_softc *sc, bool read, void *data,
776    uint32_t len)
777{
778        const uint32_t xdma_cndc = XDMAC_CNDC_NDVIEW_NDV1 |
779            XDMAC_CNDC_NDE_DSCR_FETCH_EN |
780            XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED |
781            XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED;
782        const uint32_t xdma_interrupt = XDMAC_CIE_BIE | XDMAC_CIE_DIE |
783            XDMAC_CIE_FIE | XDMAC_CIE_RBIE | XDMAC_CIE_WBIE | XDMAC_CIE_ROIE;
784        sXdmadCfg *xdma_cfg;
785        uint32_t xdma_channel;
786        eXdmadRC rc;
787
788        if (len % 4 != 0)
789                panic("invalid XDMA transfer length");
790
791        if (read) {
792                xdma_cfg = &sc->xdma_rx_cfg;
793                xdma_channel = sc->xdma_rx_channel;
794                sc->xdma_desc.mbr_sa = (uint32_t)(sc->mem_res->r_bushandle +
795                    MCI_RDR);
796                sc->xdma_desc.mbr_da = (uint32_t)data;
797                rtems_cache_invalidate_multiple_data_lines(data, len);
798        } else {
799                xdma_cfg = &sc->xdma_tx_cfg;
800                xdma_channel = sc->xdma_tx_channel;
801                sc->xdma_desc.mbr_sa = (uint32_t)data;
802                sc->xdma_desc.mbr_da = (uint32_t)(sc->mem_res->r_bushandle +
803                    MCI_TDR);
804                rtems_cache_flush_multiple_data_lines(data, len);
805        }
806
807        sc->xdma_desc.mbr_ubc = XDMA_UBC_NVIEW_NDV1 |
808            XDMA_UBC_NDEN_UPDATED | (len / 4);
809        sc->xdma_desc.mbr_ubc |= XDMA_UBC_NDE_FETCH_DIS;
810        sc->xdma_desc.mbr_nda = 0;
811
812        rc = XDMAD_ConfigureTransfer(pXdmad, xdma_channel, xdma_cfg, xdma_cndc,
813            (uint32_t)&sc->xdma_desc, xdma_interrupt);
814        if (rc != XDMAD_OK)
815                panic("configure XDMA failed: %d", rc);
816
817        rtems_cache_flush_multiple_data_lines(&sc->xdma_desc, sizeof(sc->xdma_desc));
818
819        rc = XDMAD_StartTransfer(pXdmad, xdma_channel);
820        if (rc != XDMAD_OK)
821                panic("start XDMA failed: %d", rc);
822}
823#endif /* __rtems__ */
824static void
825at91_mci_start_cmd(struct at91_mci_softc *sc, struct mmc_command *cmd)
826{
827        uint32_t cmdr, mr;
828        struct mmc_data *data;
829#ifdef __rtems__
830        uint32_t block_count;
831        uint32_t block_size;
832#endif /* __rtems__ */
833
834        sc->curcmd = cmd;
835        data = cmd->data;
836
837        /* XXX Upper layers don't always set this */
838        cmd->mrq = sc->req;
839
840        /* Begin setting up command register. */
841
842        cmdr = cmd->opcode;
843
844        if (sc->host.ios.bus_mode == opendrain)
845                cmdr |= MCI_CMDR_OPDCMD;
846
847        /* Set up response handling.  Allow max timeout for responses. */
848
849        if (MMC_RSP(cmd->flags) == MMC_RSP_NONE)
850                cmdr |= MCI_CMDR_RSPTYP_NO;
851        else {
852                cmdr |= MCI_CMDR_MAXLAT;
853                if (cmd->flags & MMC_RSP_136)
854                        cmdr |= MCI_CMDR_RSPTYP_136;
855                else
856                        cmdr |= MCI_CMDR_RSPTYP_48;
857        }
858
859        /*
860         * If there is no data transfer, just set up the right interrupt mask
861         * and start the command.
862         *
863         * The interrupt mask needs to be CMDRDY plus all non-data-transfer
864         * errors. It's important to leave the transfer-related errors out, to
865         * avoid spurious timeout or crc errors on a STOP command following a
866         * multiblock read.  When a multiblock read is in progress, sending a
867         * STOP in the middle of a block occasionally triggers such errors, but
868         * we're totally disinterested in them because we've already gotten all
869         * the data we wanted without error before sending the STOP command.
870         */
871
872        if (data == NULL) {
873                uint32_t ier = MCI_SR_CMDRDY |
874                    MCI_SR_RTOE | MCI_SR_RENDE |
875                    MCI_SR_RCRCE | MCI_SR_RDIRE | MCI_SR_RINDE;
876
877                at91_mci_pdc_disable(sc);
878
879                if (cmd->opcode == MMC_STOP_TRANSMISSION)
880                        cmdr |= MCI_CMDR_TRCMD_STOP;
881
882                /* Ignore response CRC on CMD2 and ACMD41, per standard. */
883
884                if (cmd->opcode == MMC_SEND_OP_COND ||
885                    cmd->opcode == ACMD_SD_SEND_OP_COND)
886                        ier &= ~MCI_SR_RCRCE;
887
888                if (mci_debug)
889                        printf("CMDR %x (opcode %d) ARGR %x no data\n",
890                            cmdr, cmd->opcode, cmd->arg);
891
892                WR4(sc, MCI_ARGR, cmd->arg);
893                WR4(sc, MCI_CMDR, cmdr);
894                WR4(sc, MCI_IDR, 0xffffffff);
895                WR4(sc, MCI_IER, ier);
896                return;
897        }
898
899        /* There is data, set up the transfer-related parts of the command. */
900
901        if (data->flags & MMC_DATA_READ)
902                cmdr |= MCI_CMDR_TRDIR;
903
904        if (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE))
905                cmdr |= MCI_CMDR_TRCMD_START;
906
907        if (data->flags & MMC_DATA_STREAM)
908                cmdr |= MCI_CMDR_TRTYP_STREAM;
909        else if (data->flags & MMC_DATA_MULTI) {
910                cmdr |= MCI_CMDR_TRTYP_MULTIPLE;
911                sc->flags |= (data->flags & MMC_DATA_READ) ?
912                    CMD_MULTIREAD : CMD_MULTIWRITE;
913        }
914
915        /*
916         * Disable PDC until we're ready.
917         *
918         * Set block size and turn on PDC mode for dma xfer.
919         * Note that the block size is the smaller of the amount of data to be
920         * transferred, or 512 bytes.  The 512 size is fixed by the standard;
921         * smaller blocks are possible, but never larger.
922         */
923
924#ifndef __rtems__
925        WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS);
926
927        mr = RD4(sc,MCI_MR) & ~MCI_MR_BLKLEN;
928        mr |=  min(data->len, 512) << 16;
929        WR4(sc, MCI_MR, mr | MCI_MR_PDCMODE|MCI_MR_PDCPADV);
930
931        /*
932         * Set up DMA.
933         *
934         * Use bounce buffers even if we don't need to byteswap, because doing
935         * multi-block IO with large DMA buffers is way fast (compared to
936         * single-block IO), even after incurring the overhead of also copying
937         * from/to the caller's buffers (which may be in non-contiguous physical
938         * pages).
939         *
940         * In an ideal non-byteswap world we could create a dma tag that allows
941         * for discontiguous segments and do the IO directly from/to the
942         * caller's buffer(s), using ENDRX/ENDTX interrupts to chain the
943         * discontiguous buffers through the PDC. Someday.
944         *
945         * If a read is bigger than 2k, split it in half so that we can start
946         * byte-swapping the first half while the second half is on the wire.
947         * It would be best if we could split it into 8k chunks, but we can't
948         * always keep up with the byte-swapping due to other system activity,
949         * and if an RXBUFF interrupt happens while we're still handling the
950         * byte-swap from the prior buffer (IE, we haven't returned from
951         * handling the prior interrupt yet), then data will get dropped on the
952         * floor and we can't easily recover from that.  The right fix for that
953         * would be to have the interrupt handling only keep the DMA flowing and
954         * enqueue filled buffers to be byte-swapped in a non-interrupt context.
955         * Even that won't work on the write side of things though; in that
956         * context we have to have all the data ready to go before starting the
957         * dma.
958         *
959         * XXX what about stream transfers?
960         */
961        sc->xfer_offset = 0;
962        sc->bbuf_curidx = 0;
963#else /* __rtems__ */
964        mr = RD4(sc,MCI_MR);
965        WR4(sc, MCI_MR, mr | MCI_MR_PDCPADV);
966
967        WR4(sc, MCI_DMA, MCI_DMA_DMAEN | MCI_DMA_CHKSIZE_1);
968
969        block_size = min(data->len, 512);
970        block_count = data->len / block_size;
971        WR4(sc, MCI_BLKR, (block_size << 16) | block_count);
972#endif /* __rtems__ */
973
974        if (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE)) {
975#ifndef __rtems__
976                uint32_t len;
977                uint32_t remaining = data->len;
978                bus_addr_t paddr;
979                int err;
980
981                if (remaining > (BBCOUNT*BBSIZE))
982                        panic("IO read size exceeds MAXDATA\n");
983#endif /* __rtems__ */
984
985                if (data->flags & MMC_DATA_READ) {
986#ifndef __rtems__
987                        if (remaining > 2048) // XXX
988                                len = remaining / 2;
989                        else
990                                len = remaining;
991                        err = bus_dmamap_load(sc->dmatag, sc->bbuf_map[0],
992                            sc->bbuf_vaddr[0], len, at91_mci_getaddr,
993                            &paddr, BUS_DMA_NOWAIT);
994                        if (err != 0)
995                                panic("IO read dmamap_load failed\n");
996                        bus_dmamap_sync(sc->dmatag, sc->bbuf_map[0],
997                            BUS_DMASYNC_PREREAD);
998                        WR4(sc, PDC_RPR, paddr);
999                        WR4(sc, PDC_RCR, len / 4);
1000                        sc->bbuf_len[0] = len;
1001                        remaining -= len;
1002                        if (remaining == 0) {
1003                                sc->bbuf_len[1] = 0;
1004                        } else {
1005                                len = remaining;
1006                                err = bus_dmamap_load(sc->dmatag, sc->bbuf_map[1],
1007                                    sc->bbuf_vaddr[1], len, at91_mci_getaddr,
1008                                    &paddr, BUS_DMA_NOWAIT);
1009                                if (err != 0)
1010                                        panic("IO read dmamap_load failed\n");
1011                                bus_dmamap_sync(sc->dmatag, sc->bbuf_map[1],
1012                                    BUS_DMASYNC_PREREAD);
1013                                WR4(sc, PDC_RNPR, paddr);
1014                                WR4(sc, PDC_RNCR, len / 4);
1015                                sc->bbuf_len[1] = len;
1016                                remaining -= len;
1017                        }
1018                        WR4(sc, PDC_PTCR, PDC_PTCR_RXTEN);
1019#else /* __rtems__ */
1020                        at91_mci_setup_xdma(sc, true, data->data, data->len);
1021#endif /* __rtems__ */
1022                } else {
1023#ifndef __rtems__
1024                        len = min(BBSIZE, remaining);
1025                        at91_bswap_buf(sc, sc->bbuf_vaddr[0], data->data, len);
1026                        err = bus_dmamap_load(sc->dmatag, sc->bbuf_map[0],
1027                            sc->bbuf_vaddr[0], len, at91_mci_getaddr,
1028                            &paddr, BUS_DMA_NOWAIT);
1029                        if (err != 0)
1030                                panic("IO write dmamap_load failed\n");
1031                        bus_dmamap_sync(sc->dmatag, sc->bbuf_map[0],
1032                            BUS_DMASYNC_PREWRITE);
1033                        /*
1034                         * Erratum workaround:  PDC transfer length on a write
1035                         * must not be smaller than 12 bytes (3 words); only
1036                         * blklen bytes (set above) are actually transferred.
1037                         */
1038                        WR4(sc, PDC_TPR,paddr);
1039                        WR4(sc, PDC_TCR, (len < 12) ? 3 : len / 4);
1040                        sc->bbuf_len[0] = len;
1041                        remaining -= len;
1042                        if (remaining == 0) {
1043                                sc->bbuf_len[1] = 0;
1044                        } else {
1045                                len = remaining;
1046                                at91_bswap_buf(sc, sc->bbuf_vaddr[1],
1047                                    ((char *)data->data)+BBSIZE, len);
1048                                err = bus_dmamap_load(sc->dmatag, sc->bbuf_map[1],
1049                                    sc->bbuf_vaddr[1], len, at91_mci_getaddr,
1050                                    &paddr, BUS_DMA_NOWAIT);
1051                                if (err != 0)
1052                                        panic("IO write dmamap_load failed\n");
1053                                bus_dmamap_sync(sc->dmatag, sc->bbuf_map[1],
1054                                    BUS_DMASYNC_PREWRITE);
1055                                WR4(sc, PDC_TNPR, paddr);
1056                                WR4(sc, PDC_TNCR, (len < 12) ? 3 : len / 4);
1057                                sc->bbuf_len[1] = len;
1058                                remaining -= len;
1059                        }
1060                        /* do not enable PDC xfer until CMDRDY asserted */
1061#else /* __rtems__ */
1062                        at91_mci_setup_xdma(sc, false, data->data, data->len);
1063#endif /* __rtems__ */
1064                }
1065                data->xfer_len = 0; /* XXX what's this? appears to be unused. */
1066        }
1067
1068        if (mci_debug)
1069                printf("CMDR %x (opcode %d) ARGR %x with data len %d\n",
1070                       cmdr, cmd->opcode, cmd->arg, cmd->data->len);
1071
1072        WR4(sc, MCI_ARGR, cmd->arg);
1073        WR4(sc, MCI_CMDR, cmdr);
1074        WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_CMDRDY);
1075}
1076
1077static void
1078at91_mci_next_operation(struct at91_mci_softc *sc)
1079{
1080        struct mmc_request *req;
1081
1082        req = sc->req;
1083        if (req == NULL)
1084                return;
1085
1086        if (sc->flags & PENDING_CMD) {
1087                sc->flags &= ~PENDING_CMD;
1088                at91_mci_start_cmd(sc, req->cmd);
1089                return;
1090        } else if (sc->flags & PENDING_STOP) {
1091                sc->flags &= ~PENDING_STOP;
1092                at91_mci_start_cmd(sc, req->stop);
1093                return;
1094        }
1095
1096        WR4(sc, MCI_IDR, 0xffffffff);
1097        sc->req = NULL;
1098        sc->curcmd = NULL;
1099        //printf("req done\n");
1100        req->done(req);
1101}
1102
1103static int
1104at91_mci_request(device_t brdev, device_t reqdev, struct mmc_request *req)
1105{
1106        struct at91_mci_softc *sc = device_get_softc(brdev);
1107
1108        AT91_MCI_LOCK(sc);
1109        if (sc->req != NULL) {
1110                AT91_MCI_UNLOCK(sc);
1111                return (EBUSY);
1112        }
1113        //printf("new req\n");
1114        sc->req = req;
1115        sc->flags = PENDING_CMD;
1116        if (sc->req->stop)
1117                sc->flags |= PENDING_STOP;
1118        at91_mci_next_operation(sc);
1119        AT91_MCI_UNLOCK(sc);
1120        return (0);
1121}
1122
1123static int
1124at91_mci_get_ro(device_t brdev, device_t reqdev)
1125{
1126        return (0);
1127}
1128
1129static int
1130at91_mci_acquire_host(device_t brdev, device_t reqdev)
1131{
1132        struct at91_mci_softc *sc = device_get_softc(brdev);
1133        int err = 0;
1134
1135#ifndef __rtems__
1136        AT91_MCI_LOCK(sc);
1137#else /* __rtems__ */
1138        AT91_MCI_BUS_LOCK(sc);
1139#endif /* __rtems__ */
1140        while (sc->bus_busy)
1141                msleep(sc, &sc->sc_mtx, PZERO, "mciah", hz / 5);
1142        sc->bus_busy++;
1143#ifndef __rtems__
1144        AT91_MCI_UNLOCK(sc);
1145#else /* __rtems__ */
1146        AT91_MCI_BUS_UNLOCK(sc);
1147#endif /* __rtems__ */
1148        return (err);
1149}
1150
1151static int
1152at91_mci_release_host(device_t brdev, device_t reqdev)
1153{
1154        struct at91_mci_softc *sc = device_get_softc(brdev);
1155
1156#ifndef __rtems__
1157        AT91_MCI_LOCK(sc);
1158#else /* __rtems__ */
1159        AT91_MCI_BUS_LOCK(sc);
1160#endif /* __rtems__ */
1161        sc->bus_busy--;
1162        wakeup(sc);
1163#ifndef __rtems__
1164        AT91_MCI_UNLOCK(sc);
1165#else /* __rtems__ */
1166        AT91_MCI_BUS_UNLOCK(sc);
1167#endif /* __rtems__ */
1168        return (0);
1169}
1170
1171#ifndef __rtems__
1172static void
1173at91_mci_read_done(struct at91_mci_softc *sc, uint32_t sr)
1174{
1175        struct mmc_command *cmd = sc->curcmd;
1176        char * dataptr = (char *)cmd->data->data;
1177        uint32_t curidx = sc->bbuf_curidx;
1178        uint32_t len = sc->bbuf_len[curidx];
1179
1180        /*
1181         * We arrive here when a DMA transfer for a read is done, whether it's
1182         * a single or multi-block read.
1183         *
1184         * We byte-swap the buffer that just completed, and if that is the
1185         * last buffer that's part of this read then we move on to the next
1186         * operation, otherwise we wait for another ENDRX for the next bufer.
1187         */
1188
1189        bus_dmamap_sync(sc->dmatag, sc->bbuf_map[curidx], BUS_DMASYNC_POSTREAD);
1190        bus_dmamap_unload(sc->dmatag, sc->bbuf_map[curidx]);
1191
1192        at91_bswap_buf(sc, dataptr + sc->xfer_offset, sc->bbuf_vaddr[curidx], len);
1193
1194        if (mci_debug) {
1195                printf("read done sr %x curidx %d len %d xfer_offset %d\n",
1196                       sr, curidx, len, sc->xfer_offset);
1197        }
1198
1199        sc->xfer_offset += len;
1200        sc->bbuf_curidx = !curidx; /* swap buffers */
1201
1202        /*
1203         * If we've transferred all the data, move on to the next operation.
1204         *
1205         * If we're still transferring the last buffer, RNCR is already zero but
1206         * we have to write a zero anyway to clear the ENDRX status so we don't
1207         * re-interrupt until the last buffer is done.
1208         */
1209        if (sc->xfer_offset == cmd->data->len) {
1210                WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS);
1211                cmd->error = MMC_ERR_NONE;
1212                at91_mci_next_operation(sc);
1213        } else {
1214                WR4(sc, PDC_RNCR, 0);
1215                WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_ENDRX);
1216        }
1217}
1218#endif /* __rtems__ */
1219
1220static void
1221at91_mci_write_done(struct at91_mci_softc *sc, uint32_t sr)
1222{
1223        struct mmc_command *cmd = sc->curcmd;
1224
1225        /*
1226         * We arrive here when the entire DMA transfer for a write is done,
1227         * whether it's a single or multi-block write.  If it's multi-block we
1228         * have to immediately move on to the next operation which is to send
1229         * the stop command.  If it's a single-block transfer we need to wait
1230         * for NOTBUSY, but if that's already asserted we can avoid another
1231         * interrupt and just move on to completing the request right away.
1232         */
1233
1234        WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS);
1235
1236#ifndef __rtems__
1237        bus_dmamap_sync(sc->dmatag, sc->bbuf_map[sc->bbuf_curidx],
1238            BUS_DMASYNC_POSTWRITE);
1239        bus_dmamap_unload(sc->dmatag, sc->bbuf_map[sc->bbuf_curidx]);
1240#endif /* __rtems__ */
1241
1242        if ((cmd->data->flags & MMC_DATA_MULTI) || (sr & MCI_SR_NOTBUSY)) {
1243                cmd->error = MMC_ERR_NONE;
1244                at91_mci_next_operation(sc);
1245        } else {
1246                WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_NOTBUSY);
1247        }
1248}
1249
1250static void
1251at91_mci_notbusy(struct at91_mci_softc *sc)
1252{
1253        struct mmc_command *cmd = sc->curcmd;
1254
1255        /*
1256         * We arrive here by either completion of a single-block write, or
1257         * completion of the stop command that ended a multi-block write (and,
1258         * I suppose, after a card-select or erase, but I haven't tested
1259         * those).  Anyway, we're done and it's time to move on to the next
1260         * command.
1261         */
1262
1263        cmd->error = MMC_ERR_NONE;
1264        at91_mci_next_operation(sc);
1265}
1266
1267static void
1268at91_mci_stop_done(struct at91_mci_softc *sc, uint32_t sr)
1269{
1270        struct mmc_command *cmd = sc->curcmd;
1271
1272        /*
1273         * We arrive here after receiving CMDRDY for a MMC_STOP_TRANSMISSION
1274         * command.  Depending on the operation being stopped, we may have to
1275         * do some unusual things to work around hardware bugs.
1276         */
1277
1278        /*
1279         * This is known to be true of at91rm9200 hardware; it may or may not
1280         * apply to more recent chips:
1281         *
1282         * After stopping a multi-block write, the NOTBUSY bit in MCI_SR does
1283         * not properly reflect the actual busy state of the card as signaled
1284         * on the DAT0 line; it always claims the card is not-busy.  If we
1285         * believe that and let operations continue, following commands will
1286         * fail with response timeouts (except of course MMC_SEND_STATUS -- it
1287         * indicates the card is busy in the PRG state, which was the smoking
1288         * gun that showed MCI_SR NOTBUSY was not tracking DAT0 correctly).
1289         *
1290         * The atmel docs are emphatic: "This flag [NOTBUSY] must be used only
1291         * for Write Operations."  I guess technically since we sent a stop
1292         * it's not a write operation anymore.  But then just what did they
1293         * think it meant for the stop command to have "...an optional busy
1294         * signal transmitted on the data line" according to the SD spec?
1295         *
1296         * I tried a variety of things to un-wedge the MCI and get the status
1297         * register to reflect NOTBUSY correctly again, but the only thing
1298         * that worked was a full device reset.  It feels like an awfully big
1299         * hammer, but doing a full reset after every multiblock write is
1300         * still faster than doing single-block IO (by almost two orders of
1301         * magnitude: 20KB/sec improves to about 1.8MB/sec best case).
1302         *
1303         * After doing the reset, wait for a NOTBUSY interrupt before
1304         * continuing with the next operation.
1305         *
1306         * This workaround breaks multiwrite on the rev2xx parts, but some other
1307         * workaround is needed.
1308         */
1309        if ((sc->flags & CMD_MULTIWRITE) && (sc->sc_cap & CAP_NEEDS_BYTESWAP)) {
1310                at91_mci_reset(sc);
1311                WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_NOTBUSY);
1312                return;
1313        }
1314
1315        /*
1316         * This is known to be true of at91rm9200 hardware; it may or may not
1317         * apply to more recent chips:
1318         *
1319         * After stopping a multi-block read, loop to read and discard any
1320         * data that coasts in after we sent the stop command.  The docs don't
1321         * say anything about it, but empirical testing shows that 1-3
1322         * additional words of data get buffered up in some unmentioned
1323         * internal fifo and if we don't read and discard them here they end
1324         * up on the front of the next read DMA transfer we do.
1325         *
1326         * This appears to be unnecessary for rev2xx parts.
1327         */
1328        if ((sc->flags & CMD_MULTIREAD) && (sc->sc_cap & CAP_NEEDS_BYTESWAP)) {
1329                uint32_t sr;
1330                int count = 0;
1331
1332                do {
1333                        sr = RD4(sc, MCI_SR);
1334                        if (sr & MCI_SR_RXRDY) {
1335                                RD4(sc,  MCI_RDR);
1336                                ++count;
1337                        }
1338                } while (sr & MCI_SR_RXRDY);
1339                at91_mci_reset(sc);
1340        }
1341
1342        cmd->error = MMC_ERR_NONE;
1343        at91_mci_next_operation(sc);
1344
1345}
1346
1347static void
1348at91_mci_cmdrdy(struct at91_mci_softc *sc, uint32_t sr)
1349{
1350        struct mmc_command *cmd = sc->curcmd;
1351        int i;
1352
1353        if (cmd == NULL)
1354                return;
1355
1356        /*
1357         * We get here at the end of EVERY command.  We retrieve the command
1358         * response (if any) then decide what to do next based on the command.
1359         */
1360
1361        if (cmd->flags & MMC_RSP_PRESENT) {
1362                for (i = 0; i < ((cmd->flags & MMC_RSP_136) ? 4 : 1); i++) {
1363                        cmd->resp[i] = RD4(sc, MCI_RSPR + i * 4);
1364                        if (mci_debug)
1365                                printf("RSPR[%d] = %x sr=%x\n", i, cmd->resp[i],  sr);
1366                }
1367        }
1368
1369        /*
1370         * If this was a stop command, go handle the various special
1371         * conditions (read: bugs) that have to be dealt with following a stop.
1372         */
1373        if (cmd->opcode == MMC_STOP_TRANSMISSION) {
1374                at91_mci_stop_done(sc, sr);
1375                return;
1376        }
1377
1378        /*
1379         * If this command can continue to assert BUSY beyond the response then
1380         * we need to wait for NOTBUSY before the command is really done.
1381         *
1382         * Note that this may not work properly on the at91rm9200.  It certainly
1383         * doesn't work for the STOP command that follows a multi-block write,
1384         * so post-stop CMDRDY is handled separately; see the special handling
1385         * in at91_mci_stop_done().
1386         *
1387         * Beside STOP, there are other R1B-type commands that use the busy
1388         * signal after CMDRDY: CMD7 (card select), CMD28-29 (write protect),
1389         * CMD38 (erase). I haven't tested any of them, but I rather expect
1390         * them all to have the same sort of problem with MCI_SR not actually
1391         * reflecting the state of the DAT0-line busy indicator.  So this code
1392         * may need to grow some sort of special handling for them too. (This
1393         * just in: CMD7 isn't a problem right now because dev/mmc.c incorrectly
1394         * sets the response flags to R1 rather than R1B.) XXX
1395         */
1396        if ((cmd->flags & MMC_RSP_BUSY)) {
1397                WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_NOTBUSY);
1398                return;
1399        }
1400
1401        /*
1402         * If there is a data transfer with this command, then...
1403         * - If it's a read, we need to wait for ENDRX.
1404         * - If it's a write, now is the time to enable the PDC, and we need
1405         *   to wait for a BLKE that follows a TXBUFE, because if we're doing
1406         *   a split transfer we get a BLKE after the first half (when TPR/TCR
1407         *   get loaded from TNPR/TNCR).  So first we wait for the TXBUFE, and
1408         *   the handling for that interrupt will then invoke the wait for the
1409         *   subsequent BLKE which indicates actual completion.
1410         */
1411        if (cmd->data) {
1412                uint32_t ier;
1413#ifndef __rtems__
1414                if (cmd->data->flags & MMC_DATA_READ) {
1415                        ier = MCI_SR_ENDRX;
1416                } else {
1417                        ier = MCI_SR_TXBUFE;
1418                        WR4(sc, PDC_PTCR, PDC_PTCR_TXTEN);
1419                }
1420#else /* __rtems__ */
1421                ier = MCI_SR_XFRDONE;
1422#endif /* __rtems__ */
1423                WR4(sc, MCI_IER, MCI_SR_ERROR | ier);
1424                return;
1425        }
1426
1427        /*
1428         * If we made it to here, we don't need to wait for anything more for
1429         * the current command, move on to the next command (will complete the
1430         * request if there is no next command).
1431         */
1432        cmd->error = MMC_ERR_NONE;
1433        at91_mci_next_operation(sc);
1434}
1435
1436static void
1437at91_mci_intr(void *arg)
1438{
1439        struct at91_mci_softc *sc = (struct at91_mci_softc*)arg;
1440        struct mmc_command *cmd = sc->curcmd;
1441        uint32_t sr, isr;
1442
1443        AT91_MCI_LOCK(sc);
1444
1445        sr = RD4(sc, MCI_SR);
1446        isr = sr & RD4(sc, MCI_IMR);
1447
1448        if (mci_debug)
1449                printf("i 0x%x sr 0x%x\n", isr, sr);
1450
1451        /*
1452         * All interrupts are one-shot; disable it now.
1453         * The next operation will re-enable whatever interrupts it wants.
1454         */
1455        WR4(sc, MCI_IDR, isr);
1456        if (isr & MCI_SR_ERROR) {
1457                if (isr & (MCI_SR_RTOE | MCI_SR_DTOE))
1458                        cmd->error = MMC_ERR_TIMEOUT;
1459                else if (isr & (MCI_SR_RCRCE | MCI_SR_DCRCE))
1460                        cmd->error = MMC_ERR_BADCRC;
1461                else if (isr & (MCI_SR_OVRE | MCI_SR_UNRE))
1462                        cmd->error = MMC_ERR_FIFO;
1463                else
1464                        cmd->error = MMC_ERR_FAILED;
1465                /*
1466                 * CMD8 is used to probe for SDHC cards, a standard SD card
1467                 * will get a response timeout; don't report it because it's a
1468                 * normal and expected condition.  One might argue that all
1469                 * error reporting should be left to higher levels, but when
1470                 * they report at all it's always EIO, which isn't very
1471                 * helpful. XXX bootverbose?
1472                 */
1473                if (cmd->opcode != 8) {
1474                        device_printf(sc->dev,
1475                            "IO error; status MCI_SR = 0x%b cmd opcode = %d%s\n",
1476                            sr, MCI_SR_BITSTRING, cmd->opcode,
1477                            (cmd->opcode != 12) ? "" :
1478                            (sc->flags & CMD_MULTIREAD) ? " after read" : " after write");
1479                        /* XXX not sure RTOE needs a full reset, just a retry */
1480                        at91_mci_reset(sc);
1481                }
1482                at91_mci_next_operation(sc);
1483        } else {
1484#ifndef __rtems__
1485                if (isr & MCI_SR_TXBUFE) {
1486//                      printf("TXBUFE\n");
1487                        /*
1488                         * We need to wait for a BLKE that follows TXBUFE
1489                         * (intermediate BLKEs might happen after ENDTXes if
1490                         * we're chaining multiple buffers).  If BLKE is also
1491                         * asserted at the time we get TXBUFE, we can avoid
1492                         * another interrupt and process it right away, below.
1493                         */
1494                        if (sr & MCI_SR_BLKE)
1495                                isr |= MCI_SR_BLKE;
1496                        else
1497                                WR4(sc, MCI_IER, MCI_SR_BLKE);
1498                }
1499                if (isr & MCI_SR_RXBUFF) {
1500//                      printf("RXBUFF\n");
1501                }
1502                if (isr & MCI_SR_ENDTX) {
1503//                      printf("ENDTX\n");
1504                }
1505                if (isr & MCI_SR_ENDRX) {
1506//                      printf("ENDRX\n");
1507                        at91_mci_read_done(sc, sr);
1508                }
1509#else /* __rtems__ */
1510                if (isr & MCI_SR_XFRDONE) {
1511                        if (cmd->data->flags & MMC_DATA_READ) {
1512                                WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS |
1513                                    PDC_PTCR_TXTDIS);
1514                                cmd->error = MMC_ERR_NONE;
1515                                at91_mci_next_operation(sc);
1516                        } else {
1517                                if (sr & MCI_SR_BLKE)
1518                                        isr |= MCI_SR_BLKE;
1519                                else
1520                                        WR4(sc, MCI_IER, MCI_SR_BLKE);
1521                        }
1522                }
1523#endif /* __rtems__ */
1524                if (isr & MCI_SR_NOTBUSY) {
1525//                      printf("NOTBUSY\n");
1526                        at91_mci_notbusy(sc);
1527                }
1528                if (isr & MCI_SR_DTIP) {
1529//                      printf("Data transfer in progress\n");
1530                }
1531                if (isr & MCI_SR_BLKE) {
1532//                      printf("Block transfer end\n");
1533                        at91_mci_write_done(sc, sr);
1534                }
1535                if (isr & MCI_SR_TXRDY) {
1536//                      printf("Ready to transmit\n");
1537                }
1538                if (isr & MCI_SR_RXRDY) {
1539//                      printf("Ready to receive\n");
1540                }
1541                if (isr & MCI_SR_CMDRDY) {
1542//                      printf("Command ready\n");
1543                        at91_mci_cmdrdy(sc, sr);
1544                }
1545        }
1546        AT91_MCI_UNLOCK(sc);
1547}
1548
1549static int
1550at91_mci_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
1551{
1552        struct at91_mci_softc *sc = device_get_softc(bus);
1553
1554        switch (which) {
1555        default:
1556                return (EINVAL);
1557        case MMCBR_IVAR_BUS_MODE:
1558                *(int *)result = sc->host.ios.bus_mode;
1559                break;
1560        case MMCBR_IVAR_BUS_WIDTH:
1561                *(int *)result = sc->host.ios.bus_width;
1562                break;
1563        case MMCBR_IVAR_CHIP_SELECT:
1564                *(int *)result = sc->host.ios.chip_select;
1565                break;
1566        case MMCBR_IVAR_CLOCK:
1567                *(int *)result = sc->host.ios.clock;
1568                break;
1569        case MMCBR_IVAR_F_MIN:
1570                *(int *)result = sc->host.f_min;
1571                break;
1572        case MMCBR_IVAR_F_MAX:
1573                *(int *)result = sc->host.f_max;
1574                break;
1575        case MMCBR_IVAR_HOST_OCR:
1576                *(int *)result = sc->host.host_ocr;
1577                break;
1578        case MMCBR_IVAR_MODE:
1579                *(int *)result = sc->host.mode;
1580                break;
1581        case MMCBR_IVAR_OCR:
1582                *(int *)result = sc->host.ocr;
1583                break;
1584        case MMCBR_IVAR_POWER_MODE:
1585                *(int *)result = sc->host.ios.power_mode;
1586                break;
1587        case MMCBR_IVAR_VDD:
1588                *(int *)result = sc->host.ios.vdd;
1589                break;
1590        case MMCBR_IVAR_CAPS:
1591                if (sc->has_4wire) {
1592                        sc->sc_cap |= CAP_HAS_4WIRE;
1593                        sc->host.caps |= MMC_CAP_4_BIT_DATA;
1594                } else {
1595                        sc->sc_cap &= ~CAP_HAS_4WIRE;
1596                        sc->host.caps &= ~MMC_CAP_4_BIT_DATA;
1597                }
1598                *(int *)result = sc->host.caps;
1599                break;
1600#ifdef __rtems__
1601        case MMCBR_IVAR_TIMING:
1602                *result = sc->host.ios.timing;
1603                break;
1604#endif /* __rtems__ */
1605        case MMCBR_IVAR_MAX_DATA:
1606                /*
1607                 * Something is wrong with the 2x parts and multiblock, so
1608                 * just do 1 block at a time for now, which really kills
1609                 * performance.
1610                 */
1611                if (sc->sc_cap & CAP_MCI1_REV2XX)
1612                        *(int *)result = 1;
1613                else
1614                        *(int *)result = MAX_BLOCKS;
1615                break;
1616        }
1617        return (0);
1618}
1619
1620static int
1621at91_mci_write_ivar(device_t bus, device_t child, int which, uintptr_t value)
1622{
1623        struct at91_mci_softc *sc = device_get_softc(bus);
1624
1625        switch (which) {
1626        default:
1627                return (EINVAL);
1628        case MMCBR_IVAR_BUS_MODE:
1629                sc->host.ios.bus_mode = value;
1630                break;
1631        case MMCBR_IVAR_BUS_WIDTH:
1632                sc->host.ios.bus_width = value;
1633                break;
1634        case MMCBR_IVAR_CHIP_SELECT:
1635                sc->host.ios.chip_select = value;
1636                break;
1637        case MMCBR_IVAR_CLOCK:
1638                sc->host.ios.clock = value;
1639                break;
1640        case MMCBR_IVAR_MODE:
1641                sc->host.mode = value;
1642                break;
1643        case MMCBR_IVAR_OCR:
1644                sc->host.ocr = value;
1645                break;
1646        case MMCBR_IVAR_POWER_MODE:
1647                sc->host.ios.power_mode = value;
1648                break;
1649        case MMCBR_IVAR_VDD:
1650                sc->host.ios.vdd = value;
1651                break;
1652#ifdef __rtems__
1653        case MMCBR_IVAR_TIMING:
1654                sc->host.ios.timing = value;
1655                break;
1656#endif /* __rtems__ */
1657        /* These are read-only */
1658        case MMCBR_IVAR_CAPS:
1659        case MMCBR_IVAR_HOST_OCR:
1660        case MMCBR_IVAR_F_MIN:
1661        case MMCBR_IVAR_F_MAX:
1662        case MMCBR_IVAR_MAX_DATA:
1663                return (EINVAL);
1664        }
1665        return (0);
1666}
1667
1668static device_method_t at91_mci_methods[] = {
1669        /* device_if */
1670        DEVMETHOD(device_probe, at91_mci_probe),
1671        DEVMETHOD(device_attach, at91_mci_attach),
1672        DEVMETHOD(device_detach, at91_mci_detach),
1673
1674        /* Bus interface */
1675        DEVMETHOD(bus_read_ivar,        at91_mci_read_ivar),
1676        DEVMETHOD(bus_write_ivar,       at91_mci_write_ivar),
1677
1678        /* mmcbr_if */
1679        DEVMETHOD(mmcbr_update_ios, at91_mci_update_ios),
1680        DEVMETHOD(mmcbr_request, at91_mci_request),
1681        DEVMETHOD(mmcbr_get_ro, at91_mci_get_ro),
1682        DEVMETHOD(mmcbr_acquire_host, at91_mci_acquire_host),
1683        DEVMETHOD(mmcbr_release_host, at91_mci_release_host),
1684
1685        DEVMETHOD_END
1686};
1687
1688static driver_t at91_mci_driver = {
1689        "at91_mci",
1690        at91_mci_methods,
1691        sizeof(struct at91_mci_softc),
1692};
1693
1694static devclass_t at91_mci_devclass;
1695
1696#ifndef __rtems__
1697#ifdef FDT
1698DRIVER_MODULE(at91_mci, simplebus, at91_mci_driver, at91_mci_devclass, NULL,
1699    NULL);
1700#else
1701DRIVER_MODULE(at91_mci, atmelarm, at91_mci_driver, at91_mci_devclass, NULL,
1702    NULL);
1703#endif
1704
1705MMC_DECLARE_BRIDGE(at91_mci);
1706#else /* __rtems__ */
1707DRIVER_MODULE(at91_mci, nexus, at91_mci_driver, at91_mci_devclass, NULL, NULL);
1708#endif /* __rtems__ */
1709DRIVER_MODULE(mmc, at91_mci, mmc_driver, mmc_devclass, NULL, NULL);
1710MODULE_DEPEND(at91_mci, mmc, 1, 1, 1);
1711#endif /* __rtems__ && LIBBSP_ARM_ATSAM_BSP_H */
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