1 | #include <machine/rtems-bsd-kernel-space.h> |
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2 | |
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3 | /*- |
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4 | * Copyright (c) 2006 Bernd Walter. All rights reserved. |
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5 | * Copyright (c) 2006 M. Warner Losh. All rights reserved. |
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6 | * Copyright (c) 2010 Greg Ansley. All rights reserved. |
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7 | * |
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8 | * Redistribution and use in source and binary forms, with or without |
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9 | * modification, are permitted provided that the following conditions |
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10 | * are met: |
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11 | * 1. Redistributions of source code must retain the above copyright |
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12 | * notice, this list of conditions and the following disclaimer. |
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13 | * 2. Redistributions in binary form must reproduce the above copyright |
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14 | * notice, this list of conditions and the following disclaimer in the |
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15 | * documentation and/or other materials provided with the distribution. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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18 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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19 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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20 | * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE |
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21 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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22 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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23 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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24 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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25 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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26 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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27 | * SUCH DAMAGE. |
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28 | */ |
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29 | |
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30 | #include <rtems/bsd/local/opt_platform.h> |
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31 | |
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32 | #include <sys/cdefs.h> |
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33 | __FBSDID("$FreeBSD$"); |
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34 | |
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35 | #include <rtems/bsd/sys/param.h> |
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36 | #include <sys/systm.h> |
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37 | #include <sys/bus.h> |
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38 | #include <sys/endian.h> |
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39 | #include <sys/kernel.h> |
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40 | #include <sys/lock.h> |
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41 | #include <sys/malloc.h> |
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42 | #include <sys/module.h> |
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43 | #include <sys/mutex.h> |
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44 | #include <rtems/bsd/sys/resource.h> |
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45 | #include <sys/rman.h> |
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46 | #include <sys/sysctl.h> |
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47 | |
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48 | #include <machine/bus.h> |
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49 | #include <machine/resource.h> |
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50 | #include <machine/intr.h> |
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51 | |
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52 | #include <arm/at91/at91var.h> |
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53 | #include <arm/at91/at91_mcireg.h> |
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54 | #include <arm/at91/at91_pdcreg.h> |
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55 | |
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56 | #include <dev/mmc/bridge.h> |
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57 | #include <dev/mmc/mmcbrvar.h> |
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58 | |
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59 | #ifdef FDT |
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60 | #include <dev/ofw/ofw_bus.h> |
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61 | #include <dev/ofw/ofw_bus_subr.h> |
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62 | #endif |
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63 | |
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64 | #include <rtems/bsd/local/mmcbr_if.h> |
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65 | |
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66 | #include <rtems/bsd/local/opt_at91.h> |
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67 | |
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68 | /* |
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69 | * About running the MCI bus above 25MHz |
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70 | * |
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71 | * Historically, the MCI bus has been run at 30MHz on systems with a 60MHz |
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72 | * master clock, in part due to a bug in dev/mmc.c making always request |
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73 | * 30MHz, and in part over clocking the bus because 15MHz was too slow. |
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74 | * Fixing that bug causes the mmc driver to request a 25MHz clock (as it |
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75 | * should) and the logic in at91_mci_update_ios() picks the highest speed that |
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76 | * doesn't exceed that limit. With a 60MHz MCK that would be 15MHz, and |
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77 | * that's a real performance buzzkill when you've been getting away with 30MHz |
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78 | * all along. |
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79 | * |
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80 | * By defining AT91_MCI_ALLOW_OVERCLOCK (or setting the allow_overclock=1 |
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81 | * device hint or sysctl) you can enable logic in at91_mci_update_ios() to |
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82 | * overlcock the SD bus a little by running it at MCK / 2 when the requested |
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83 | * speed is 25MHz and the next highest speed is 15MHz or less. This appears |
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84 | * to work on virtually all SD cards, since it is what this driver has been |
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85 | * doing prior to the introduction of this option, where the overclocking vs |
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86 | * underclocking decision was automatically "overclock". Modern SD cards can |
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87 | * run at 45mhz/1-bit in standard mode (high speed mode enable commands not |
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88 | * sent) without problems. |
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89 | * |
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90 | * Speaking of high-speed mode, the rm9200 manual says the MCI device supports |
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91 | * the SD v1.0 specification and can run up to 50MHz. This is interesting in |
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92 | * that the SD v1.0 spec caps the speed at 25MHz; high speed mode was added in |
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93 | * the v1.10 spec. Furthermore, high speed mode doesn't just crank up the |
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94 | * clock, it alters the signal timing. The rm9200 MCI device doesn't support |
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95 | * these altered timings. So while speeds over 25MHz may work, they only work |
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96 | * in what the SD spec calls "default" speed mode, and it amounts to violating |
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97 | * the spec by overclocking the bus. |
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98 | * |
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99 | * If you also enable 4-wire mode it's possible transfers faster than 25MHz |
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100 | * will fail. On the AT91RM9200, due to bugs in the bus contention logic, if |
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101 | * you have the USB host device and OHCI driver enabled will fail. Even |
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102 | * underclocking to 15MHz, intermittant overrun and underrun errors occur. |
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103 | * Note that you don't even need to have usb devices attached to the system, |
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104 | * the errors begin to occur as soon as the OHCI driver sets the register bit |
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105 | * to enable periodic transfers. It appears (based on brief investigation) |
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106 | * that the usb host controller uses so much ASB bandwidth that sometimes the |
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107 | * DMA for MCI transfers doesn't get a bus grant in time and data gets |
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108 | * dropped. Adding even a modicum of network activity changes the symptom |
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109 | * from intermittant to very frequent. Members of the AT91SAM9 family have |
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110 | * corrected this problem, or are at least better about their use of the bus. |
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111 | */ |
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112 | #ifndef AT91_MCI_ALLOW_OVERCLOCK |
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113 | #define AT91_MCI_ALLOW_OVERCLOCK 1 |
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114 | #endif |
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115 | |
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116 | /* |
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117 | * Allocate 2 bounce buffers we'll use to endian-swap the data due to the rm9200 |
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118 | * erratum. We use a pair of buffers because when reading that lets us begin |
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119 | * endian-swapping the data in the first buffer while the DMA is reading into |
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120 | * the second buffer. (We can't use the same trick for writing because we might |
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121 | * not get all the data in the 2nd buffer swapped before the hardware needs it; |
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122 | * dealing with that would add complexity to the driver.) |
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123 | * |
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124 | * The buffers are sized at 16K each due to the way the busdma cache sync |
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125 | * operations work on arm. A dcache_inv_range() operation on a range larger |
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126 | * than 16K gets turned into a dcache_wbinv_all(). That needlessly flushes the |
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127 | * entire data cache, impacting overall system performance. |
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128 | */ |
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129 | #define BBCOUNT 2 |
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130 | #define BBSIZE (16*1024) |
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131 | #define MAX_BLOCKS ((BBSIZE*BBCOUNT)/512) |
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132 | |
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133 | static int mci_debug; |
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134 | |
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135 | struct at91_mci_softc { |
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136 | void *intrhand; /* Interrupt handle */ |
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137 | device_t dev; |
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138 | int sc_cap; |
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139 | #define CAP_HAS_4WIRE 1 /* Has 4 wire bus */ |
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140 | #define CAP_NEEDS_BYTESWAP 2 /* broken hardware needing bounce */ |
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141 | #define CAP_MCI1_REV2XX 4 /* MCI 1 rev 2.x */ |
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142 | int flags; |
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143 | #define PENDING_CMD 0x01 |
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144 | #define PENDING_STOP 0x02 |
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145 | #define CMD_MULTIREAD 0x10 |
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146 | #define CMD_MULTIWRITE 0x20 |
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147 | int has_4wire; |
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148 | int allow_overclock; |
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149 | struct resource *irq_res; /* IRQ resource */ |
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150 | struct resource *mem_res; /* Memory resource */ |
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151 | struct mtx sc_mtx; |
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152 | bus_dma_tag_t dmatag; |
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153 | struct mmc_host host; |
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154 | int bus_busy; |
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155 | struct mmc_request *req; |
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156 | struct mmc_command *curcmd; |
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157 | bus_dmamap_t bbuf_map[BBCOUNT]; |
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158 | char * bbuf_vaddr[BBCOUNT]; /* bounce bufs in KVA space */ |
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159 | uint32_t bbuf_len[BBCOUNT]; /* len currently queued for bounce buf */ |
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160 | uint32_t bbuf_curidx; /* which bbuf is the active DMA buffer */ |
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161 | uint32_t xfer_offset; /* offset so far into caller's buf */ |
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162 | }; |
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163 | |
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164 | /* bus entry points */ |
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165 | static int at91_mci_probe(device_t dev); |
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166 | static int at91_mci_attach(device_t dev); |
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167 | static int at91_mci_detach(device_t dev); |
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168 | static void at91_mci_intr(void *); |
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169 | |
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170 | /* helper routines */ |
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171 | static int at91_mci_activate(device_t dev); |
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172 | static void at91_mci_deactivate(device_t dev); |
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173 | static int at91_mci_is_mci1rev2xx(void); |
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174 | |
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175 | #define AT91_MCI_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) |
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176 | #define AT91_MCI_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) |
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177 | #define AT91_MCI_LOCK_INIT(_sc) \ |
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178 | mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ |
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179 | "mci", MTX_DEF) |
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180 | #define AT91_MCI_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); |
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181 | #define AT91_MCI_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); |
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182 | #define AT91_MCI_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); |
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183 | |
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184 | static inline uint32_t |
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185 | RD4(struct at91_mci_softc *sc, bus_size_t off) |
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186 | { |
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187 | return (bus_read_4(sc->mem_res, off)); |
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188 | } |
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189 | |
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190 | static inline void |
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191 | WR4(struct at91_mci_softc *sc, bus_size_t off, uint32_t val) |
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192 | { |
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193 | bus_write_4(sc->mem_res, off, val); |
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194 | } |
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195 | |
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196 | static void |
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197 | at91_bswap_buf(struct at91_mci_softc *sc, void * dptr, void * sptr, uint32_t memsize) |
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198 | { |
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199 | uint32_t * dst = (uint32_t *)dptr; |
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200 | uint32_t * src = (uint32_t *)sptr; |
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201 | uint32_t i; |
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202 | |
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203 | /* |
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204 | * If the hardware doesn't need byte-swapping, let bcopy() do the |
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205 | * work. Use bounce buffer even if we don't need byteswap, since |
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206 | * buffer may straddle a page boundary, and we don't handle |
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207 | * multi-segment transfers in hardware. Seen from 'bsdlabel -w' which |
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208 | * uses raw geom access to the volume. Greg Ansley (gja (at) |
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209 | * ansley.com) |
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210 | */ |
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211 | if (!(sc->sc_cap & CAP_NEEDS_BYTESWAP)) { |
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212 | memcpy(dptr, sptr, memsize); |
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213 | return; |
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214 | } |
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215 | |
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216 | /* |
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217 | * Nice performance boost for slightly unrolling this loop. |
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218 | * (But very little extra boost for further unrolling it.) |
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219 | */ |
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220 | for (i = 0; i < memsize; i += 16) { |
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221 | *dst++ = bswap32(*src++); |
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222 | *dst++ = bswap32(*src++); |
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223 | *dst++ = bswap32(*src++); |
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224 | *dst++ = bswap32(*src++); |
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225 | } |
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226 | |
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227 | /* Mop up the last 1-3 words, if any. */ |
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228 | for (i = 0; i < (memsize & 0x0F); i += 4) { |
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229 | *dst++ = bswap32(*src++); |
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230 | } |
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231 | } |
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232 | |
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233 | static void |
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234 | at91_mci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) |
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235 | { |
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236 | if (error != 0) |
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237 | return; |
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238 | *(bus_addr_t *)arg = segs[0].ds_addr; |
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239 | } |
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240 | |
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241 | static void |
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242 | at91_mci_pdc_disable(struct at91_mci_softc *sc) |
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243 | { |
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244 | WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS); |
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245 | WR4(sc, PDC_RPR, 0); |
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246 | WR4(sc, PDC_RCR, 0); |
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247 | WR4(sc, PDC_RNPR, 0); |
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248 | WR4(sc, PDC_RNCR, 0); |
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249 | WR4(sc, PDC_TPR, 0); |
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250 | WR4(sc, PDC_TCR, 0); |
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251 | WR4(sc, PDC_TNPR, 0); |
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252 | WR4(sc, PDC_TNCR, 0); |
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253 | } |
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254 | |
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255 | /* |
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256 | * Reset the controller, then restore most of the current state. |
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257 | * |
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258 | * This is called after detecting an error. It's also called after stopping a |
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259 | * multi-block write, to un-wedge the device so that it will handle the NOTBUSY |
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260 | * signal correctly. See comments in at91_mci_stop_done() for more details. |
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261 | */ |
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262 | static void at91_mci_reset(struct at91_mci_softc *sc) |
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263 | { |
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264 | uint32_t mr; |
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265 | uint32_t sdcr; |
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266 | uint32_t dtor; |
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267 | uint32_t imr; |
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268 | |
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269 | at91_mci_pdc_disable(sc); |
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270 | |
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271 | /* save current state */ |
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272 | |
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273 | imr = RD4(sc, MCI_IMR); |
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274 | mr = RD4(sc, MCI_MR) & 0x7fff; |
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275 | sdcr = RD4(sc, MCI_SDCR); |
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276 | dtor = RD4(sc, MCI_DTOR); |
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277 | |
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278 | /* reset the controller */ |
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279 | |
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280 | WR4(sc, MCI_IDR, 0xffffffff); |
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281 | WR4(sc, MCI_CR, MCI_CR_MCIDIS | MCI_CR_SWRST); |
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282 | |
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283 | /* restore state */ |
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284 | |
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285 | WR4(sc, MCI_CR, MCI_CR_MCIEN|MCI_CR_PWSEN); |
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286 | WR4(sc, MCI_MR, mr); |
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287 | WR4(sc, MCI_SDCR, sdcr); |
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288 | WR4(sc, MCI_DTOR, dtor); |
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289 | WR4(sc, MCI_IER, imr); |
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290 | |
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291 | /* |
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292 | * Make sure sdio interrupts will fire. Not sure why reading |
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293 | * SR ensures that, but this is in the linux driver. |
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294 | */ |
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295 | |
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296 | RD4(sc, MCI_SR); |
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297 | } |
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298 | |
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299 | static void |
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300 | at91_mci_init(device_t dev) |
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301 | { |
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302 | struct at91_mci_softc *sc = device_get_softc(dev); |
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303 | uint32_t val; |
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304 | |
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305 | WR4(sc, MCI_CR, MCI_CR_MCIDIS | MCI_CR_SWRST); /* device into reset */ |
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306 | WR4(sc, MCI_IDR, 0xffffffff); /* Turn off interrupts */ |
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307 | WR4(sc, MCI_DTOR, MCI_DTOR_DTOMUL_1M | 1); |
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308 | val = MCI_MR_PDCMODE; |
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309 | val |= 0x34a; /* PWSDIV = 3; CLKDIV = 74 */ |
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310 | // if (sc->sc_cap & CAP_MCI1_REV2XX) |
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311 | // val |= MCI_MR_RDPROOF | MCI_MR_WRPROOF; |
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312 | WR4(sc, MCI_MR, val); |
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313 | #ifndef AT91_MCI_SLOT_B |
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314 | WR4(sc, MCI_SDCR, 0); /* SLOT A, 1 bit bus */ |
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315 | #else |
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316 | /* |
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317 | * XXX Really should add second "unit" but nobody using using |
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318 | * a two slot card that we know of. XXX |
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319 | */ |
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320 | WR4(sc, MCI_SDCR, 1); /* SLOT B, 1 bit bus */ |
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321 | #endif |
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322 | /* |
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323 | * Enable controller, including power-save. The slower clock |
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324 | * of the power-save mode is only in effect when there is no |
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325 | * transfer in progress, so it can be left in this mode all |
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326 | * the time. |
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327 | */ |
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328 | WR4(sc, MCI_CR, MCI_CR_MCIEN|MCI_CR_PWSEN); |
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329 | } |
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330 | |
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331 | static void |
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332 | at91_mci_fini(device_t dev) |
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333 | { |
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334 | struct at91_mci_softc *sc = device_get_softc(dev); |
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335 | |
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336 | WR4(sc, MCI_IDR, 0xffffffff); /* Turn off interrupts */ |
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337 | at91_mci_pdc_disable(sc); |
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338 | WR4(sc, MCI_CR, MCI_CR_MCIDIS | MCI_CR_SWRST); /* device into reset */ |
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339 | } |
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340 | |
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341 | static int |
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342 | at91_mci_probe(device_t dev) |
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343 | { |
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344 | #ifdef FDT |
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345 | if (!ofw_bus_is_compatible(dev, "atmel,hsmci")) |
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346 | return (ENXIO); |
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347 | #endif |
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348 | device_set_desc(dev, "MCI mmc/sd host bridge"); |
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349 | return (0); |
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350 | } |
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351 | |
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352 | static int |
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353 | at91_mci_attach(device_t dev) |
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354 | { |
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355 | struct at91_mci_softc *sc = device_get_softc(dev); |
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356 | struct sysctl_ctx_list *sctx; |
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357 | struct sysctl_oid *soid; |
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358 | device_t child; |
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359 | int err, i; |
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360 | |
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361 | sctx = device_get_sysctl_ctx(dev); |
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362 | soid = device_get_sysctl_tree(dev); |
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363 | |
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364 | sc->dev = dev; |
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365 | sc->sc_cap = 0; |
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366 | if (at91_is_rm92()) |
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367 | sc->sc_cap |= CAP_NEEDS_BYTESWAP; |
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368 | /* |
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369 | * MCI1 Rev 2 controllers need some workarounds, flag if so. |
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370 | */ |
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371 | if (at91_mci_is_mci1rev2xx()) |
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372 | sc->sc_cap |= CAP_MCI1_REV2XX; |
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373 | |
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374 | err = at91_mci_activate(dev); |
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375 | if (err) |
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376 | goto out; |
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377 | |
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378 | AT91_MCI_LOCK_INIT(sc); |
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379 | |
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380 | at91_mci_fini(dev); |
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381 | at91_mci_init(dev); |
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382 | |
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383 | /* |
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384 | * Allocate DMA tags and maps and bounce buffers. |
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385 | * |
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386 | * The parms in the tag_create call cause the dmamem_alloc call to |
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387 | * create each bounce buffer as a single contiguous buffer of BBSIZE |
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388 | * bytes aligned to a 4096 byte boundary. |
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389 | * |
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390 | * Do not use DMA_COHERENT for these buffers because that maps the |
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391 | * memory as non-cachable, which prevents cache line burst fills/writes, |
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392 | * which is something we need since we're trying to overlap the |
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393 | * byte-swapping with the DMA operations. |
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394 | */ |
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395 | err = bus_dma_tag_create(bus_get_dma_tag(dev), 4096, 0, |
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396 | BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, |
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397 | BBSIZE, 1, BBSIZE, 0, NULL, NULL, &sc->dmatag); |
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398 | if (err != 0) |
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399 | goto out; |
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400 | |
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401 | for (i = 0; i < BBCOUNT; ++i) { |
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402 | err = bus_dmamem_alloc(sc->dmatag, (void **)&sc->bbuf_vaddr[i], |
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403 | BUS_DMA_NOWAIT, &sc->bbuf_map[i]); |
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404 | if (err != 0) |
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405 | goto out; |
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406 | } |
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407 | |
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408 | /* |
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409 | * Activate the interrupt |
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410 | */ |
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411 | err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, |
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412 | NULL, at91_mci_intr, sc, &sc->intrhand); |
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413 | if (err) { |
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414 | AT91_MCI_LOCK_DESTROY(sc); |
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415 | goto out; |
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416 | } |
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417 | |
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418 | /* |
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419 | * Allow 4-wire to be initially set via #define. |
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420 | * Allow a device hint to override that. |
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421 | * Allow a sysctl to override that. |
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422 | */ |
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423 | #if defined(AT91_MCI_HAS_4WIRE) && AT91_MCI_HAS_4WIRE != 0 |
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424 | sc->has_4wire = 1; |
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425 | #endif |
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426 | resource_int_value(device_get_name(dev), device_get_unit(dev), |
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427 | "4wire", &sc->has_4wire); |
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428 | SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "4wire", |
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429 | CTLFLAG_RW, &sc->has_4wire, 0, "has 4 wire SD Card bus"); |
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430 | if (sc->has_4wire) |
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431 | sc->sc_cap |= CAP_HAS_4WIRE; |
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432 | |
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433 | sc->allow_overclock = AT91_MCI_ALLOW_OVERCLOCK; |
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434 | resource_int_value(device_get_name(dev), device_get_unit(dev), |
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435 | "allow_overclock", &sc->allow_overclock); |
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436 | SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "allow_overclock", |
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437 | CTLFLAG_RW, &sc->allow_overclock, 0, |
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438 | "Allow up to 30MHz clock for 25MHz request when next highest speed 15MHz or less."); |
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439 | |
---|
440 | SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "debug", |
---|
441 | CTLFLAG_RWTUN, &mci_debug, 0, "enable debug output"); |
---|
442 | |
---|
443 | /* |
---|
444 | * Our real min freq is master_clock/512, but upper driver layers are |
---|
445 | * going to set the min speed during card discovery, and the right speed |
---|
446 | * for that is 400kHz, so advertise a safe value just under that. |
---|
447 | * |
---|
448 | * For max speed, while the rm9200 manual says the max is 50mhz, it also |
---|
449 | * says it supports only the SD v1.0 spec, which means the real limit is |
---|
450 | * 25mhz. On the other hand, historical use has been to slightly violate |
---|
451 | * the standard by running the bus at 30MHz. For more information on |
---|
452 | * that, see the comments at the top of this file. |
---|
453 | */ |
---|
454 | sc->host.f_min = 375000; |
---|
455 | sc->host.f_max = at91_master_clock / 2; |
---|
456 | if (sc->host.f_max > 25000000) |
---|
457 | sc->host.f_max = 25000000; |
---|
458 | sc->host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340; |
---|
459 | sc->host.caps = 0; |
---|
460 | if (sc->sc_cap & CAP_HAS_4WIRE) |
---|
461 | sc->host.caps |= MMC_CAP_4_BIT_DATA; |
---|
462 | |
---|
463 | child = device_add_child(dev, "mmc", 0); |
---|
464 | device_set_ivars(dev, &sc->host); |
---|
465 | err = bus_generic_attach(dev); |
---|
466 | out: |
---|
467 | if (err) |
---|
468 | at91_mci_deactivate(dev); |
---|
469 | return (err); |
---|
470 | } |
---|
471 | |
---|
472 | static int |
---|
473 | at91_mci_detach(device_t dev) |
---|
474 | { |
---|
475 | struct at91_mci_softc *sc = device_get_softc(dev); |
---|
476 | |
---|
477 | at91_mci_fini(dev); |
---|
478 | at91_mci_deactivate(dev); |
---|
479 | |
---|
480 | bus_dmamem_free(sc->dmatag, sc->bbuf_vaddr[0], sc->bbuf_map[0]); |
---|
481 | bus_dmamem_free(sc->dmatag, sc->bbuf_vaddr[1], sc->bbuf_map[1]); |
---|
482 | bus_dma_tag_destroy(sc->dmatag); |
---|
483 | |
---|
484 | return (EBUSY); /* XXX */ |
---|
485 | } |
---|
486 | |
---|
487 | static int |
---|
488 | at91_mci_activate(device_t dev) |
---|
489 | { |
---|
490 | struct at91_mci_softc *sc; |
---|
491 | int rid; |
---|
492 | |
---|
493 | sc = device_get_softc(dev); |
---|
494 | rid = 0; |
---|
495 | sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, |
---|
496 | RF_ACTIVE); |
---|
497 | if (sc->mem_res == NULL) |
---|
498 | goto errout; |
---|
499 | |
---|
500 | rid = 0; |
---|
501 | sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, |
---|
502 | RF_ACTIVE); |
---|
503 | if (sc->irq_res == NULL) |
---|
504 | goto errout; |
---|
505 | |
---|
506 | return (0); |
---|
507 | errout: |
---|
508 | at91_mci_deactivate(dev); |
---|
509 | return (ENOMEM); |
---|
510 | } |
---|
511 | |
---|
512 | static void |
---|
513 | at91_mci_deactivate(device_t dev) |
---|
514 | { |
---|
515 | struct at91_mci_softc *sc; |
---|
516 | |
---|
517 | sc = device_get_softc(dev); |
---|
518 | if (sc->intrhand) |
---|
519 | bus_teardown_intr(dev, sc->irq_res, sc->intrhand); |
---|
520 | sc->intrhand = NULL; |
---|
521 | bus_generic_detach(sc->dev); |
---|
522 | if (sc->mem_res) |
---|
523 | bus_release_resource(dev, SYS_RES_MEMORY, |
---|
524 | rman_get_rid(sc->mem_res), sc->mem_res); |
---|
525 | sc->mem_res = NULL; |
---|
526 | if (sc->irq_res) |
---|
527 | bus_release_resource(dev, SYS_RES_IRQ, |
---|
528 | rman_get_rid(sc->irq_res), sc->irq_res); |
---|
529 | sc->irq_res = NULL; |
---|
530 | return; |
---|
531 | } |
---|
532 | |
---|
533 | static int |
---|
534 | at91_mci_is_mci1rev2xx(void) |
---|
535 | { |
---|
536 | |
---|
537 | switch (soc_info.type) { |
---|
538 | case AT91_T_SAM9260: |
---|
539 | case AT91_T_SAM9263: |
---|
540 | case AT91_T_CAP9: |
---|
541 | case AT91_T_SAM9G10: |
---|
542 | case AT91_T_SAM9G20: |
---|
543 | case AT91_T_SAM9RL: |
---|
544 | return(1); |
---|
545 | default: |
---|
546 | return (0); |
---|
547 | } |
---|
548 | } |
---|
549 | |
---|
550 | static int |
---|
551 | at91_mci_update_ios(device_t brdev, device_t reqdev) |
---|
552 | { |
---|
553 | struct at91_mci_softc *sc; |
---|
554 | struct mmc_ios *ios; |
---|
555 | uint32_t clkdiv; |
---|
556 | uint32_t freq; |
---|
557 | |
---|
558 | sc = device_get_softc(brdev); |
---|
559 | ios = &sc->host.ios; |
---|
560 | |
---|
561 | /* |
---|
562 | * Calculate our closest available clock speed that doesn't exceed the |
---|
563 | * requested speed. |
---|
564 | * |
---|
565 | * When overclocking is allowed, the requested clock is 25MHz, the |
---|
566 | * computed frequency is 15MHz or smaller and clockdiv is 1, use |
---|
567 | * clockdiv of 0 to double that. If less than 12.5MHz, double |
---|
568 | * regardless of the overclocking setting. |
---|
569 | * |
---|
570 | * Whatever we come up with, store it back into ios->clock so that the |
---|
571 | * upper layer drivers can report the actual speed of the bus. |
---|
572 | */ |
---|
573 | if (ios->clock == 0) { |
---|
574 | WR4(sc, MCI_CR, MCI_CR_MCIDIS); |
---|
575 | clkdiv = 0; |
---|
576 | } else { |
---|
577 | WR4(sc, MCI_CR, MCI_CR_MCIEN|MCI_CR_PWSEN); |
---|
578 | if ((at91_master_clock % (ios->clock * 2)) == 0) |
---|
579 | clkdiv = ((at91_master_clock / ios->clock) / 2) - 1; |
---|
580 | else |
---|
581 | clkdiv = (at91_master_clock / ios->clock) / 2; |
---|
582 | freq = at91_master_clock / ((clkdiv+1) * 2); |
---|
583 | if (clkdiv == 1 && ios->clock == 25000000 && freq <= 15000000) { |
---|
584 | if (sc->allow_overclock || freq <= 12500000) { |
---|
585 | clkdiv = 0; |
---|
586 | freq = at91_master_clock / ((clkdiv+1) * 2); |
---|
587 | } |
---|
588 | } |
---|
589 | ios->clock = freq; |
---|
590 | } |
---|
591 | if (ios->bus_width == bus_width_4) |
---|
592 | WR4(sc, MCI_SDCR, RD4(sc, MCI_SDCR) | MCI_SDCR_SDCBUS); |
---|
593 | else |
---|
594 | WR4(sc, MCI_SDCR, RD4(sc, MCI_SDCR) & ~MCI_SDCR_SDCBUS); |
---|
595 | WR4(sc, MCI_MR, (RD4(sc, MCI_MR) & ~MCI_MR_CLKDIV) | clkdiv); |
---|
596 | /* Do we need a settle time here? */ |
---|
597 | /* XXX We need to turn the device on/off here with a GPIO pin */ |
---|
598 | return (0); |
---|
599 | } |
---|
600 | |
---|
601 | static void |
---|
602 | at91_mci_start_cmd(struct at91_mci_softc *sc, struct mmc_command *cmd) |
---|
603 | { |
---|
604 | uint32_t cmdr, mr; |
---|
605 | struct mmc_data *data; |
---|
606 | |
---|
607 | sc->curcmd = cmd; |
---|
608 | data = cmd->data; |
---|
609 | |
---|
610 | /* XXX Upper layers don't always set this */ |
---|
611 | cmd->mrq = sc->req; |
---|
612 | |
---|
613 | /* Begin setting up command register. */ |
---|
614 | |
---|
615 | cmdr = cmd->opcode; |
---|
616 | |
---|
617 | if (sc->host.ios.bus_mode == opendrain) |
---|
618 | cmdr |= MCI_CMDR_OPDCMD; |
---|
619 | |
---|
620 | /* Set up response handling. Allow max timeout for responses. */ |
---|
621 | |
---|
622 | if (MMC_RSP(cmd->flags) == MMC_RSP_NONE) |
---|
623 | cmdr |= MCI_CMDR_RSPTYP_NO; |
---|
624 | else { |
---|
625 | cmdr |= MCI_CMDR_MAXLAT; |
---|
626 | if (cmd->flags & MMC_RSP_136) |
---|
627 | cmdr |= MCI_CMDR_RSPTYP_136; |
---|
628 | else |
---|
629 | cmdr |= MCI_CMDR_RSPTYP_48; |
---|
630 | } |
---|
631 | |
---|
632 | /* |
---|
633 | * If there is no data transfer, just set up the right interrupt mask |
---|
634 | * and start the command. |
---|
635 | * |
---|
636 | * The interrupt mask needs to be CMDRDY plus all non-data-transfer |
---|
637 | * errors. It's important to leave the transfer-related errors out, to |
---|
638 | * avoid spurious timeout or crc errors on a STOP command following a |
---|
639 | * multiblock read. When a multiblock read is in progress, sending a |
---|
640 | * STOP in the middle of a block occasionally triggers such errors, but |
---|
641 | * we're totally disinterested in them because we've already gotten all |
---|
642 | * the data we wanted without error before sending the STOP command. |
---|
643 | */ |
---|
644 | |
---|
645 | if (data == NULL) { |
---|
646 | uint32_t ier = MCI_SR_CMDRDY | |
---|
647 | MCI_SR_RTOE | MCI_SR_RENDE | |
---|
648 | MCI_SR_RCRCE | MCI_SR_RDIRE | MCI_SR_RINDE; |
---|
649 | |
---|
650 | at91_mci_pdc_disable(sc); |
---|
651 | |
---|
652 | if (cmd->opcode == MMC_STOP_TRANSMISSION) |
---|
653 | cmdr |= MCI_CMDR_TRCMD_STOP; |
---|
654 | |
---|
655 | /* Ignore response CRC on CMD2 and ACMD41, per standard. */ |
---|
656 | |
---|
657 | if (cmd->opcode == MMC_SEND_OP_COND || |
---|
658 | cmd->opcode == ACMD_SD_SEND_OP_COND) |
---|
659 | ier &= ~MCI_SR_RCRCE; |
---|
660 | |
---|
661 | if (mci_debug) |
---|
662 | printf("CMDR %x (opcode %d) ARGR %x no data\n", |
---|
663 | cmdr, cmd->opcode, cmd->arg); |
---|
664 | |
---|
665 | WR4(sc, MCI_ARGR, cmd->arg); |
---|
666 | WR4(sc, MCI_CMDR, cmdr); |
---|
667 | WR4(sc, MCI_IDR, 0xffffffff); |
---|
668 | WR4(sc, MCI_IER, ier); |
---|
669 | return; |
---|
670 | } |
---|
671 | |
---|
672 | /* There is data, set up the transfer-related parts of the command. */ |
---|
673 | |
---|
674 | if (data->flags & MMC_DATA_READ) |
---|
675 | cmdr |= MCI_CMDR_TRDIR; |
---|
676 | |
---|
677 | if (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE)) |
---|
678 | cmdr |= MCI_CMDR_TRCMD_START; |
---|
679 | |
---|
680 | if (data->flags & MMC_DATA_STREAM) |
---|
681 | cmdr |= MCI_CMDR_TRTYP_STREAM; |
---|
682 | else if (data->flags & MMC_DATA_MULTI) { |
---|
683 | cmdr |= MCI_CMDR_TRTYP_MULTIPLE; |
---|
684 | sc->flags |= (data->flags & MMC_DATA_READ) ? |
---|
685 | CMD_MULTIREAD : CMD_MULTIWRITE; |
---|
686 | } |
---|
687 | |
---|
688 | /* |
---|
689 | * Disable PDC until we're ready. |
---|
690 | * |
---|
691 | * Set block size and turn on PDC mode for dma xfer. |
---|
692 | * Note that the block size is the smaller of the amount of data to be |
---|
693 | * transferred, or 512 bytes. The 512 size is fixed by the standard; |
---|
694 | * smaller blocks are possible, but never larger. |
---|
695 | */ |
---|
696 | |
---|
697 | WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS); |
---|
698 | |
---|
699 | mr = RD4(sc,MCI_MR) & ~MCI_MR_BLKLEN; |
---|
700 | mr |= min(data->len, 512) << 16; |
---|
701 | WR4(sc, MCI_MR, mr | MCI_MR_PDCMODE|MCI_MR_PDCPADV); |
---|
702 | |
---|
703 | /* |
---|
704 | * Set up DMA. |
---|
705 | * |
---|
706 | * Use bounce buffers even if we don't need to byteswap, because doing |
---|
707 | * multi-block IO with large DMA buffers is way fast (compared to |
---|
708 | * single-block IO), even after incurring the overhead of also copying |
---|
709 | * from/to the caller's buffers (which may be in non-contiguous physical |
---|
710 | * pages). |
---|
711 | * |
---|
712 | * In an ideal non-byteswap world we could create a dma tag that allows |
---|
713 | * for discontiguous segments and do the IO directly from/to the |
---|
714 | * caller's buffer(s), using ENDRX/ENDTX interrupts to chain the |
---|
715 | * discontiguous buffers through the PDC. Someday. |
---|
716 | * |
---|
717 | * If a read is bigger than 2k, split it in half so that we can start |
---|
718 | * byte-swapping the first half while the second half is on the wire. |
---|
719 | * It would be best if we could split it into 8k chunks, but we can't |
---|
720 | * always keep up with the byte-swapping due to other system activity, |
---|
721 | * and if an RXBUFF interrupt happens while we're still handling the |
---|
722 | * byte-swap from the prior buffer (IE, we haven't returned from |
---|
723 | * handling the prior interrupt yet), then data will get dropped on the |
---|
724 | * floor and we can't easily recover from that. The right fix for that |
---|
725 | * would be to have the interrupt handling only keep the DMA flowing and |
---|
726 | * enqueue filled buffers to be byte-swapped in a non-interrupt context. |
---|
727 | * Even that won't work on the write side of things though; in that |
---|
728 | * context we have to have all the data ready to go before starting the |
---|
729 | * dma. |
---|
730 | * |
---|
731 | * XXX what about stream transfers? |
---|
732 | */ |
---|
733 | sc->xfer_offset = 0; |
---|
734 | sc->bbuf_curidx = 0; |
---|
735 | |
---|
736 | if (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE)) { |
---|
737 | uint32_t len; |
---|
738 | uint32_t remaining = data->len; |
---|
739 | bus_addr_t paddr; |
---|
740 | int err; |
---|
741 | |
---|
742 | if (remaining > (BBCOUNT*BBSIZE)) |
---|
743 | panic("IO read size exceeds MAXDATA\n"); |
---|
744 | |
---|
745 | if (data->flags & MMC_DATA_READ) { |
---|
746 | if (remaining > 2048) // XXX |
---|
747 | len = remaining / 2; |
---|
748 | else |
---|
749 | len = remaining; |
---|
750 | err = bus_dmamap_load(sc->dmatag, sc->bbuf_map[0], |
---|
751 | sc->bbuf_vaddr[0], len, at91_mci_getaddr, |
---|
752 | &paddr, BUS_DMA_NOWAIT); |
---|
753 | if (err != 0) |
---|
754 | panic("IO read dmamap_load failed\n"); |
---|
755 | bus_dmamap_sync(sc->dmatag, sc->bbuf_map[0], |
---|
756 | BUS_DMASYNC_PREREAD); |
---|
757 | WR4(sc, PDC_RPR, paddr); |
---|
758 | WR4(sc, PDC_RCR, len / 4); |
---|
759 | sc->bbuf_len[0] = len; |
---|
760 | remaining -= len; |
---|
761 | if (remaining == 0) { |
---|
762 | sc->bbuf_len[1] = 0; |
---|
763 | } else { |
---|
764 | len = remaining; |
---|
765 | err = bus_dmamap_load(sc->dmatag, sc->bbuf_map[1], |
---|
766 | sc->bbuf_vaddr[1], len, at91_mci_getaddr, |
---|
767 | &paddr, BUS_DMA_NOWAIT); |
---|
768 | if (err != 0) |
---|
769 | panic("IO read dmamap_load failed\n"); |
---|
770 | bus_dmamap_sync(sc->dmatag, sc->bbuf_map[1], |
---|
771 | BUS_DMASYNC_PREREAD); |
---|
772 | WR4(sc, PDC_RNPR, paddr); |
---|
773 | WR4(sc, PDC_RNCR, len / 4); |
---|
774 | sc->bbuf_len[1] = len; |
---|
775 | remaining -= len; |
---|
776 | } |
---|
777 | WR4(sc, PDC_PTCR, PDC_PTCR_RXTEN); |
---|
778 | } else { |
---|
779 | len = min(BBSIZE, remaining); |
---|
780 | at91_bswap_buf(sc, sc->bbuf_vaddr[0], data->data, len); |
---|
781 | err = bus_dmamap_load(sc->dmatag, sc->bbuf_map[0], |
---|
782 | sc->bbuf_vaddr[0], len, at91_mci_getaddr, |
---|
783 | &paddr, BUS_DMA_NOWAIT); |
---|
784 | if (err != 0) |
---|
785 | panic("IO write dmamap_load failed\n"); |
---|
786 | bus_dmamap_sync(sc->dmatag, sc->bbuf_map[0], |
---|
787 | BUS_DMASYNC_PREWRITE); |
---|
788 | /* |
---|
789 | * Erratum workaround: PDC transfer length on a write |
---|
790 | * must not be smaller than 12 bytes (3 words); only |
---|
791 | * blklen bytes (set above) are actually transferred. |
---|
792 | */ |
---|
793 | WR4(sc, PDC_TPR,paddr); |
---|
794 | WR4(sc, PDC_TCR, (len < 12) ? 3 : len / 4); |
---|
795 | sc->bbuf_len[0] = len; |
---|
796 | remaining -= len; |
---|
797 | if (remaining == 0) { |
---|
798 | sc->bbuf_len[1] = 0; |
---|
799 | } else { |
---|
800 | len = remaining; |
---|
801 | at91_bswap_buf(sc, sc->bbuf_vaddr[1], |
---|
802 | ((char *)data->data)+BBSIZE, len); |
---|
803 | err = bus_dmamap_load(sc->dmatag, sc->bbuf_map[1], |
---|
804 | sc->bbuf_vaddr[1], len, at91_mci_getaddr, |
---|
805 | &paddr, BUS_DMA_NOWAIT); |
---|
806 | if (err != 0) |
---|
807 | panic("IO write dmamap_load failed\n"); |
---|
808 | bus_dmamap_sync(sc->dmatag, sc->bbuf_map[1], |
---|
809 | BUS_DMASYNC_PREWRITE); |
---|
810 | WR4(sc, PDC_TNPR, paddr); |
---|
811 | WR4(sc, PDC_TNCR, (len < 12) ? 3 : len / 4); |
---|
812 | sc->bbuf_len[1] = len; |
---|
813 | remaining -= len; |
---|
814 | } |
---|
815 | /* do not enable PDC xfer until CMDRDY asserted */ |
---|
816 | } |
---|
817 | data->xfer_len = 0; /* XXX what's this? appears to be unused. */ |
---|
818 | } |
---|
819 | |
---|
820 | if (mci_debug) |
---|
821 | printf("CMDR %x (opcode %d) ARGR %x with data len %d\n", |
---|
822 | cmdr, cmd->opcode, cmd->arg, cmd->data->len); |
---|
823 | |
---|
824 | WR4(sc, MCI_ARGR, cmd->arg); |
---|
825 | WR4(sc, MCI_CMDR, cmdr); |
---|
826 | WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_CMDRDY); |
---|
827 | } |
---|
828 | |
---|
829 | static void |
---|
830 | at91_mci_next_operation(struct at91_mci_softc *sc) |
---|
831 | { |
---|
832 | struct mmc_request *req; |
---|
833 | |
---|
834 | req = sc->req; |
---|
835 | if (req == NULL) |
---|
836 | return; |
---|
837 | |
---|
838 | if (sc->flags & PENDING_CMD) { |
---|
839 | sc->flags &= ~PENDING_CMD; |
---|
840 | at91_mci_start_cmd(sc, req->cmd); |
---|
841 | return; |
---|
842 | } else if (sc->flags & PENDING_STOP) { |
---|
843 | sc->flags &= ~PENDING_STOP; |
---|
844 | at91_mci_start_cmd(sc, req->stop); |
---|
845 | return; |
---|
846 | } |
---|
847 | |
---|
848 | WR4(sc, MCI_IDR, 0xffffffff); |
---|
849 | sc->req = NULL; |
---|
850 | sc->curcmd = NULL; |
---|
851 | //printf("req done\n"); |
---|
852 | req->done(req); |
---|
853 | } |
---|
854 | |
---|
855 | static int |
---|
856 | at91_mci_request(device_t brdev, device_t reqdev, struct mmc_request *req) |
---|
857 | { |
---|
858 | struct at91_mci_softc *sc = device_get_softc(brdev); |
---|
859 | |
---|
860 | AT91_MCI_LOCK(sc); |
---|
861 | if (sc->req != NULL) { |
---|
862 | AT91_MCI_UNLOCK(sc); |
---|
863 | return (EBUSY); |
---|
864 | } |
---|
865 | //printf("new req\n"); |
---|
866 | sc->req = req; |
---|
867 | sc->flags = PENDING_CMD; |
---|
868 | if (sc->req->stop) |
---|
869 | sc->flags |= PENDING_STOP; |
---|
870 | at91_mci_next_operation(sc); |
---|
871 | AT91_MCI_UNLOCK(sc); |
---|
872 | return (0); |
---|
873 | } |
---|
874 | |
---|
875 | static int |
---|
876 | at91_mci_get_ro(device_t brdev, device_t reqdev) |
---|
877 | { |
---|
878 | return (0); |
---|
879 | } |
---|
880 | |
---|
881 | static int |
---|
882 | at91_mci_acquire_host(device_t brdev, device_t reqdev) |
---|
883 | { |
---|
884 | struct at91_mci_softc *sc = device_get_softc(brdev); |
---|
885 | int err = 0; |
---|
886 | |
---|
887 | AT91_MCI_LOCK(sc); |
---|
888 | while (sc->bus_busy) |
---|
889 | msleep(sc, &sc->sc_mtx, PZERO, "mciah", hz / 5); |
---|
890 | sc->bus_busy++; |
---|
891 | AT91_MCI_UNLOCK(sc); |
---|
892 | return (err); |
---|
893 | } |
---|
894 | |
---|
895 | static int |
---|
896 | at91_mci_release_host(device_t brdev, device_t reqdev) |
---|
897 | { |
---|
898 | struct at91_mci_softc *sc = device_get_softc(brdev); |
---|
899 | |
---|
900 | AT91_MCI_LOCK(sc); |
---|
901 | sc->bus_busy--; |
---|
902 | wakeup(sc); |
---|
903 | AT91_MCI_UNLOCK(sc); |
---|
904 | return (0); |
---|
905 | } |
---|
906 | |
---|
907 | static void |
---|
908 | at91_mci_read_done(struct at91_mci_softc *sc, uint32_t sr) |
---|
909 | { |
---|
910 | struct mmc_command *cmd = sc->curcmd; |
---|
911 | char * dataptr = (char *)cmd->data->data; |
---|
912 | uint32_t curidx = sc->bbuf_curidx; |
---|
913 | uint32_t len = sc->bbuf_len[curidx]; |
---|
914 | |
---|
915 | /* |
---|
916 | * We arrive here when a DMA transfer for a read is done, whether it's |
---|
917 | * a single or multi-block read. |
---|
918 | * |
---|
919 | * We byte-swap the buffer that just completed, and if that is the |
---|
920 | * last buffer that's part of this read then we move on to the next |
---|
921 | * operation, otherwise we wait for another ENDRX for the next bufer. |
---|
922 | */ |
---|
923 | |
---|
924 | bus_dmamap_sync(sc->dmatag, sc->bbuf_map[curidx], BUS_DMASYNC_POSTREAD); |
---|
925 | bus_dmamap_unload(sc->dmatag, sc->bbuf_map[curidx]); |
---|
926 | |
---|
927 | at91_bswap_buf(sc, dataptr + sc->xfer_offset, sc->bbuf_vaddr[curidx], len); |
---|
928 | |
---|
929 | if (mci_debug) { |
---|
930 | printf("read done sr %x curidx %d len %d xfer_offset %d\n", |
---|
931 | sr, curidx, len, sc->xfer_offset); |
---|
932 | } |
---|
933 | |
---|
934 | sc->xfer_offset += len; |
---|
935 | sc->bbuf_curidx = !curidx; /* swap buffers */ |
---|
936 | |
---|
937 | /* |
---|
938 | * If we've transferred all the data, move on to the next operation. |
---|
939 | * |
---|
940 | * If we're still transferring the last buffer, RNCR is already zero but |
---|
941 | * we have to write a zero anyway to clear the ENDRX status so we don't |
---|
942 | * re-interrupt until the last buffer is done. |
---|
943 | */ |
---|
944 | if (sc->xfer_offset == cmd->data->len) { |
---|
945 | WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS); |
---|
946 | cmd->error = MMC_ERR_NONE; |
---|
947 | at91_mci_next_operation(sc); |
---|
948 | } else { |
---|
949 | WR4(sc, PDC_RNCR, 0); |
---|
950 | WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_ENDRX); |
---|
951 | } |
---|
952 | } |
---|
953 | |
---|
954 | static void |
---|
955 | at91_mci_write_done(struct at91_mci_softc *sc, uint32_t sr) |
---|
956 | { |
---|
957 | struct mmc_command *cmd = sc->curcmd; |
---|
958 | |
---|
959 | /* |
---|
960 | * We arrive here when the entire DMA transfer for a write is done, |
---|
961 | * whether it's a single or multi-block write. If it's multi-block we |
---|
962 | * have to immediately move on to the next operation which is to send |
---|
963 | * the stop command. If it's a single-block transfer we need to wait |
---|
964 | * for NOTBUSY, but if that's already asserted we can avoid another |
---|
965 | * interrupt and just move on to completing the request right away. |
---|
966 | */ |
---|
967 | |
---|
968 | WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS); |
---|
969 | |
---|
970 | bus_dmamap_sync(sc->dmatag, sc->bbuf_map[sc->bbuf_curidx], |
---|
971 | BUS_DMASYNC_POSTWRITE); |
---|
972 | bus_dmamap_unload(sc->dmatag, sc->bbuf_map[sc->bbuf_curidx]); |
---|
973 | |
---|
974 | if ((cmd->data->flags & MMC_DATA_MULTI) || (sr & MCI_SR_NOTBUSY)) { |
---|
975 | cmd->error = MMC_ERR_NONE; |
---|
976 | at91_mci_next_operation(sc); |
---|
977 | } else { |
---|
978 | WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_NOTBUSY); |
---|
979 | } |
---|
980 | } |
---|
981 | |
---|
982 | static void |
---|
983 | at91_mci_notbusy(struct at91_mci_softc *sc) |
---|
984 | { |
---|
985 | struct mmc_command *cmd = sc->curcmd; |
---|
986 | |
---|
987 | /* |
---|
988 | * We arrive here by either completion of a single-block write, or |
---|
989 | * completion of the stop command that ended a multi-block write (and, |
---|
990 | * I suppose, after a card-select or erase, but I haven't tested |
---|
991 | * those). Anyway, we're done and it's time to move on to the next |
---|
992 | * command. |
---|
993 | */ |
---|
994 | |
---|
995 | cmd->error = MMC_ERR_NONE; |
---|
996 | at91_mci_next_operation(sc); |
---|
997 | } |
---|
998 | |
---|
999 | static void |
---|
1000 | at91_mci_stop_done(struct at91_mci_softc *sc, uint32_t sr) |
---|
1001 | { |
---|
1002 | struct mmc_command *cmd = sc->curcmd; |
---|
1003 | |
---|
1004 | /* |
---|
1005 | * We arrive here after receiving CMDRDY for a MMC_STOP_TRANSMISSION |
---|
1006 | * command. Depending on the operation being stopped, we may have to |
---|
1007 | * do some unusual things to work around hardware bugs. |
---|
1008 | */ |
---|
1009 | |
---|
1010 | /* |
---|
1011 | * This is known to be true of at91rm9200 hardware; it may or may not |
---|
1012 | * apply to more recent chips: |
---|
1013 | * |
---|
1014 | * After stopping a multi-block write, the NOTBUSY bit in MCI_SR does |
---|
1015 | * not properly reflect the actual busy state of the card as signaled |
---|
1016 | * on the DAT0 line; it always claims the card is not-busy. If we |
---|
1017 | * believe that and let operations continue, following commands will |
---|
1018 | * fail with response timeouts (except of course MMC_SEND_STATUS -- it |
---|
1019 | * indicates the card is busy in the PRG state, which was the smoking |
---|
1020 | * gun that showed MCI_SR NOTBUSY was not tracking DAT0 correctly). |
---|
1021 | * |
---|
1022 | * The atmel docs are emphatic: "This flag [NOTBUSY] must be used only |
---|
1023 | * for Write Operations." I guess technically since we sent a stop |
---|
1024 | * it's not a write operation anymore. But then just what did they |
---|
1025 | * think it meant for the stop command to have "...an optional busy |
---|
1026 | * signal transmitted on the data line" according to the SD spec? |
---|
1027 | * |
---|
1028 | * I tried a variety of things to un-wedge the MCI and get the status |
---|
1029 | * register to reflect NOTBUSY correctly again, but the only thing |
---|
1030 | * that worked was a full device reset. It feels like an awfully big |
---|
1031 | * hammer, but doing a full reset after every multiblock write is |
---|
1032 | * still faster than doing single-block IO (by almost two orders of |
---|
1033 | * magnitude: 20KB/sec improves to about 1.8MB/sec best case). |
---|
1034 | * |
---|
1035 | * After doing the reset, wait for a NOTBUSY interrupt before |
---|
1036 | * continuing with the next operation. |
---|
1037 | * |
---|
1038 | * This workaround breaks multiwrite on the rev2xx parts, but some other |
---|
1039 | * workaround is needed. |
---|
1040 | */ |
---|
1041 | if ((sc->flags & CMD_MULTIWRITE) && (sc->sc_cap & CAP_NEEDS_BYTESWAP)) { |
---|
1042 | at91_mci_reset(sc); |
---|
1043 | WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_NOTBUSY); |
---|
1044 | return; |
---|
1045 | } |
---|
1046 | |
---|
1047 | /* |
---|
1048 | * This is known to be true of at91rm9200 hardware; it may or may not |
---|
1049 | * apply to more recent chips: |
---|
1050 | * |
---|
1051 | * After stopping a multi-block read, loop to read and discard any |
---|
1052 | * data that coasts in after we sent the stop command. The docs don't |
---|
1053 | * say anything about it, but empirical testing shows that 1-3 |
---|
1054 | * additional words of data get buffered up in some unmentioned |
---|
1055 | * internal fifo and if we don't read and discard them here they end |
---|
1056 | * up on the front of the next read DMA transfer we do. |
---|
1057 | * |
---|
1058 | * This appears to be unnecessary for rev2xx parts. |
---|
1059 | */ |
---|
1060 | if ((sc->flags & CMD_MULTIREAD) && (sc->sc_cap & CAP_NEEDS_BYTESWAP)) { |
---|
1061 | uint32_t sr; |
---|
1062 | int count = 0; |
---|
1063 | |
---|
1064 | do { |
---|
1065 | sr = RD4(sc, MCI_SR); |
---|
1066 | if (sr & MCI_SR_RXRDY) { |
---|
1067 | RD4(sc, MCI_RDR); |
---|
1068 | ++count; |
---|
1069 | } |
---|
1070 | } while (sr & MCI_SR_RXRDY); |
---|
1071 | at91_mci_reset(sc); |
---|
1072 | } |
---|
1073 | |
---|
1074 | cmd->error = MMC_ERR_NONE; |
---|
1075 | at91_mci_next_operation(sc); |
---|
1076 | |
---|
1077 | } |
---|
1078 | |
---|
1079 | static void |
---|
1080 | at91_mci_cmdrdy(struct at91_mci_softc *sc, uint32_t sr) |
---|
1081 | { |
---|
1082 | struct mmc_command *cmd = sc->curcmd; |
---|
1083 | int i; |
---|
1084 | |
---|
1085 | if (cmd == NULL) |
---|
1086 | return; |
---|
1087 | |
---|
1088 | /* |
---|
1089 | * We get here at the end of EVERY command. We retrieve the command |
---|
1090 | * response (if any) then decide what to do next based on the command. |
---|
1091 | */ |
---|
1092 | |
---|
1093 | if (cmd->flags & MMC_RSP_PRESENT) { |
---|
1094 | for (i = 0; i < ((cmd->flags & MMC_RSP_136) ? 4 : 1); i++) { |
---|
1095 | cmd->resp[i] = RD4(sc, MCI_RSPR + i * 4); |
---|
1096 | if (mci_debug) |
---|
1097 | printf("RSPR[%d] = %x sr=%x\n", i, cmd->resp[i], sr); |
---|
1098 | } |
---|
1099 | } |
---|
1100 | |
---|
1101 | /* |
---|
1102 | * If this was a stop command, go handle the various special |
---|
1103 | * conditions (read: bugs) that have to be dealt with following a stop. |
---|
1104 | */ |
---|
1105 | if (cmd->opcode == MMC_STOP_TRANSMISSION) { |
---|
1106 | at91_mci_stop_done(sc, sr); |
---|
1107 | return; |
---|
1108 | } |
---|
1109 | |
---|
1110 | /* |
---|
1111 | * If this command can continue to assert BUSY beyond the response then |
---|
1112 | * we need to wait for NOTBUSY before the command is really done. |
---|
1113 | * |
---|
1114 | * Note that this may not work properly on the at91rm9200. It certainly |
---|
1115 | * doesn't work for the STOP command that follows a multi-block write, |
---|
1116 | * so post-stop CMDRDY is handled separately; see the special handling |
---|
1117 | * in at91_mci_stop_done(). |
---|
1118 | * |
---|
1119 | * Beside STOP, there are other R1B-type commands that use the busy |
---|
1120 | * signal after CMDRDY: CMD7 (card select), CMD28-29 (write protect), |
---|
1121 | * CMD38 (erase). I haven't tested any of them, but I rather expect |
---|
1122 | * them all to have the same sort of problem with MCI_SR not actually |
---|
1123 | * reflecting the state of the DAT0-line busy indicator. So this code |
---|
1124 | * may need to grow some sort of special handling for them too. (This |
---|
1125 | * just in: CMD7 isn't a problem right now because dev/mmc.c incorrectly |
---|
1126 | * sets the response flags to R1 rather than R1B.) XXX |
---|
1127 | */ |
---|
1128 | if ((cmd->flags & MMC_RSP_BUSY)) { |
---|
1129 | WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_NOTBUSY); |
---|
1130 | return; |
---|
1131 | } |
---|
1132 | |
---|
1133 | /* |
---|
1134 | * If there is a data transfer with this command, then... |
---|
1135 | * - If it's a read, we need to wait for ENDRX. |
---|
1136 | * - If it's a write, now is the time to enable the PDC, and we need |
---|
1137 | * to wait for a BLKE that follows a TXBUFE, because if we're doing |
---|
1138 | * a split transfer we get a BLKE after the first half (when TPR/TCR |
---|
1139 | * get loaded from TNPR/TNCR). So first we wait for the TXBUFE, and |
---|
1140 | * the handling for that interrupt will then invoke the wait for the |
---|
1141 | * subsequent BLKE which indicates actual completion. |
---|
1142 | */ |
---|
1143 | if (cmd->data) { |
---|
1144 | uint32_t ier; |
---|
1145 | if (cmd->data->flags & MMC_DATA_READ) { |
---|
1146 | ier = MCI_SR_ENDRX; |
---|
1147 | } else { |
---|
1148 | ier = MCI_SR_TXBUFE; |
---|
1149 | WR4(sc, PDC_PTCR, PDC_PTCR_TXTEN); |
---|
1150 | } |
---|
1151 | WR4(sc, MCI_IER, MCI_SR_ERROR | ier); |
---|
1152 | return; |
---|
1153 | } |
---|
1154 | |
---|
1155 | /* |
---|
1156 | * If we made it to here, we don't need to wait for anything more for |
---|
1157 | * the current command, move on to the next command (will complete the |
---|
1158 | * request if there is no next command). |
---|
1159 | */ |
---|
1160 | cmd->error = MMC_ERR_NONE; |
---|
1161 | at91_mci_next_operation(sc); |
---|
1162 | } |
---|
1163 | |
---|
1164 | static void |
---|
1165 | at91_mci_intr(void *arg) |
---|
1166 | { |
---|
1167 | struct at91_mci_softc *sc = (struct at91_mci_softc*)arg; |
---|
1168 | struct mmc_command *cmd = sc->curcmd; |
---|
1169 | uint32_t sr, isr; |
---|
1170 | |
---|
1171 | AT91_MCI_LOCK(sc); |
---|
1172 | |
---|
1173 | sr = RD4(sc, MCI_SR); |
---|
1174 | isr = sr & RD4(sc, MCI_IMR); |
---|
1175 | |
---|
1176 | if (mci_debug) |
---|
1177 | printf("i 0x%x sr 0x%x\n", isr, sr); |
---|
1178 | |
---|
1179 | /* |
---|
1180 | * All interrupts are one-shot; disable it now. |
---|
1181 | * The next operation will re-enable whatever interrupts it wants. |
---|
1182 | */ |
---|
1183 | WR4(sc, MCI_IDR, isr); |
---|
1184 | if (isr & MCI_SR_ERROR) { |
---|
1185 | if (isr & (MCI_SR_RTOE | MCI_SR_DTOE)) |
---|
1186 | cmd->error = MMC_ERR_TIMEOUT; |
---|
1187 | else if (isr & (MCI_SR_RCRCE | MCI_SR_DCRCE)) |
---|
1188 | cmd->error = MMC_ERR_BADCRC; |
---|
1189 | else if (isr & (MCI_SR_OVRE | MCI_SR_UNRE)) |
---|
1190 | cmd->error = MMC_ERR_FIFO; |
---|
1191 | else |
---|
1192 | cmd->error = MMC_ERR_FAILED; |
---|
1193 | /* |
---|
1194 | * CMD8 is used to probe for SDHC cards, a standard SD card |
---|
1195 | * will get a response timeout; don't report it because it's a |
---|
1196 | * normal and expected condition. One might argue that all |
---|
1197 | * error reporting should be left to higher levels, but when |
---|
1198 | * they report at all it's always EIO, which isn't very |
---|
1199 | * helpful. XXX bootverbose? |
---|
1200 | */ |
---|
1201 | if (cmd->opcode != 8) { |
---|
1202 | device_printf(sc->dev, |
---|
1203 | "IO error; status MCI_SR = 0x%b cmd opcode = %d%s\n", |
---|
1204 | sr, MCI_SR_BITSTRING, cmd->opcode, |
---|
1205 | (cmd->opcode != 12) ? "" : |
---|
1206 | (sc->flags & CMD_MULTIREAD) ? " after read" : " after write"); |
---|
1207 | /* XXX not sure RTOE needs a full reset, just a retry */ |
---|
1208 | at91_mci_reset(sc); |
---|
1209 | } |
---|
1210 | at91_mci_next_operation(sc); |
---|
1211 | } else { |
---|
1212 | if (isr & MCI_SR_TXBUFE) { |
---|
1213 | // printf("TXBUFE\n"); |
---|
1214 | /* |
---|
1215 | * We need to wait for a BLKE that follows TXBUFE |
---|
1216 | * (intermediate BLKEs might happen after ENDTXes if |
---|
1217 | * we're chaining multiple buffers). If BLKE is also |
---|
1218 | * asserted at the time we get TXBUFE, we can avoid |
---|
1219 | * another interrupt and process it right away, below. |
---|
1220 | */ |
---|
1221 | if (sr & MCI_SR_BLKE) |
---|
1222 | isr |= MCI_SR_BLKE; |
---|
1223 | else |
---|
1224 | WR4(sc, MCI_IER, MCI_SR_BLKE); |
---|
1225 | } |
---|
1226 | if (isr & MCI_SR_RXBUFF) { |
---|
1227 | // printf("RXBUFF\n"); |
---|
1228 | } |
---|
1229 | if (isr & MCI_SR_ENDTX) { |
---|
1230 | // printf("ENDTX\n"); |
---|
1231 | } |
---|
1232 | if (isr & MCI_SR_ENDRX) { |
---|
1233 | // printf("ENDRX\n"); |
---|
1234 | at91_mci_read_done(sc, sr); |
---|
1235 | } |
---|
1236 | if (isr & MCI_SR_NOTBUSY) { |
---|
1237 | // printf("NOTBUSY\n"); |
---|
1238 | at91_mci_notbusy(sc); |
---|
1239 | } |
---|
1240 | if (isr & MCI_SR_DTIP) { |
---|
1241 | // printf("Data transfer in progress\n"); |
---|
1242 | } |
---|
1243 | if (isr & MCI_SR_BLKE) { |
---|
1244 | // printf("Block transfer end\n"); |
---|
1245 | at91_mci_write_done(sc, sr); |
---|
1246 | } |
---|
1247 | if (isr & MCI_SR_TXRDY) { |
---|
1248 | // printf("Ready to transmit\n"); |
---|
1249 | } |
---|
1250 | if (isr & MCI_SR_RXRDY) { |
---|
1251 | // printf("Ready to receive\n"); |
---|
1252 | } |
---|
1253 | if (isr & MCI_SR_CMDRDY) { |
---|
1254 | // printf("Command ready\n"); |
---|
1255 | at91_mci_cmdrdy(sc, sr); |
---|
1256 | } |
---|
1257 | } |
---|
1258 | AT91_MCI_UNLOCK(sc); |
---|
1259 | } |
---|
1260 | |
---|
1261 | static int |
---|
1262 | at91_mci_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) |
---|
1263 | { |
---|
1264 | struct at91_mci_softc *sc = device_get_softc(bus); |
---|
1265 | |
---|
1266 | switch (which) { |
---|
1267 | default: |
---|
1268 | return (EINVAL); |
---|
1269 | case MMCBR_IVAR_BUS_MODE: |
---|
1270 | *(int *)result = sc->host.ios.bus_mode; |
---|
1271 | break; |
---|
1272 | case MMCBR_IVAR_BUS_WIDTH: |
---|
1273 | *(int *)result = sc->host.ios.bus_width; |
---|
1274 | break; |
---|
1275 | case MMCBR_IVAR_CHIP_SELECT: |
---|
1276 | *(int *)result = sc->host.ios.chip_select; |
---|
1277 | break; |
---|
1278 | case MMCBR_IVAR_CLOCK: |
---|
1279 | *(int *)result = sc->host.ios.clock; |
---|
1280 | break; |
---|
1281 | case MMCBR_IVAR_F_MIN: |
---|
1282 | *(int *)result = sc->host.f_min; |
---|
1283 | break; |
---|
1284 | case MMCBR_IVAR_F_MAX: |
---|
1285 | *(int *)result = sc->host.f_max; |
---|
1286 | break; |
---|
1287 | case MMCBR_IVAR_HOST_OCR: |
---|
1288 | *(int *)result = sc->host.host_ocr; |
---|
1289 | break; |
---|
1290 | case MMCBR_IVAR_MODE: |
---|
1291 | *(int *)result = sc->host.mode; |
---|
1292 | break; |
---|
1293 | case MMCBR_IVAR_OCR: |
---|
1294 | *(int *)result = sc->host.ocr; |
---|
1295 | break; |
---|
1296 | case MMCBR_IVAR_POWER_MODE: |
---|
1297 | *(int *)result = sc->host.ios.power_mode; |
---|
1298 | break; |
---|
1299 | case MMCBR_IVAR_VDD: |
---|
1300 | *(int *)result = sc->host.ios.vdd; |
---|
1301 | break; |
---|
1302 | case MMCBR_IVAR_CAPS: |
---|
1303 | if (sc->has_4wire) { |
---|
1304 | sc->sc_cap |= CAP_HAS_4WIRE; |
---|
1305 | sc->host.caps |= MMC_CAP_4_BIT_DATA; |
---|
1306 | } else { |
---|
1307 | sc->sc_cap &= ~CAP_HAS_4WIRE; |
---|
1308 | sc->host.caps &= ~MMC_CAP_4_BIT_DATA; |
---|
1309 | } |
---|
1310 | *(int *)result = sc->host.caps; |
---|
1311 | break; |
---|
1312 | case MMCBR_IVAR_MAX_DATA: |
---|
1313 | /* |
---|
1314 | * Something is wrong with the 2x parts and multiblock, so |
---|
1315 | * just do 1 block at a time for now, which really kills |
---|
1316 | * performance. |
---|
1317 | */ |
---|
1318 | if (sc->sc_cap & CAP_MCI1_REV2XX) |
---|
1319 | *(int *)result = 1; |
---|
1320 | else |
---|
1321 | *(int *)result = MAX_BLOCKS; |
---|
1322 | break; |
---|
1323 | } |
---|
1324 | return (0); |
---|
1325 | } |
---|
1326 | |
---|
1327 | static int |
---|
1328 | at91_mci_write_ivar(device_t bus, device_t child, int which, uintptr_t value) |
---|
1329 | { |
---|
1330 | struct at91_mci_softc *sc = device_get_softc(bus); |
---|
1331 | |
---|
1332 | switch (which) { |
---|
1333 | default: |
---|
1334 | return (EINVAL); |
---|
1335 | case MMCBR_IVAR_BUS_MODE: |
---|
1336 | sc->host.ios.bus_mode = value; |
---|
1337 | break; |
---|
1338 | case MMCBR_IVAR_BUS_WIDTH: |
---|
1339 | sc->host.ios.bus_width = value; |
---|
1340 | break; |
---|
1341 | case MMCBR_IVAR_CHIP_SELECT: |
---|
1342 | sc->host.ios.chip_select = value; |
---|
1343 | break; |
---|
1344 | case MMCBR_IVAR_CLOCK: |
---|
1345 | sc->host.ios.clock = value; |
---|
1346 | break; |
---|
1347 | case MMCBR_IVAR_MODE: |
---|
1348 | sc->host.mode = value; |
---|
1349 | break; |
---|
1350 | case MMCBR_IVAR_OCR: |
---|
1351 | sc->host.ocr = value; |
---|
1352 | break; |
---|
1353 | case MMCBR_IVAR_POWER_MODE: |
---|
1354 | sc->host.ios.power_mode = value; |
---|
1355 | break; |
---|
1356 | case MMCBR_IVAR_VDD: |
---|
1357 | sc->host.ios.vdd = value; |
---|
1358 | break; |
---|
1359 | /* These are read-only */ |
---|
1360 | case MMCBR_IVAR_CAPS: |
---|
1361 | case MMCBR_IVAR_HOST_OCR: |
---|
1362 | case MMCBR_IVAR_F_MIN: |
---|
1363 | case MMCBR_IVAR_F_MAX: |
---|
1364 | case MMCBR_IVAR_MAX_DATA: |
---|
1365 | return (EINVAL); |
---|
1366 | } |
---|
1367 | return (0); |
---|
1368 | } |
---|
1369 | |
---|
1370 | static device_method_t at91_mci_methods[] = { |
---|
1371 | /* device_if */ |
---|
1372 | DEVMETHOD(device_probe, at91_mci_probe), |
---|
1373 | DEVMETHOD(device_attach, at91_mci_attach), |
---|
1374 | DEVMETHOD(device_detach, at91_mci_detach), |
---|
1375 | |
---|
1376 | /* Bus interface */ |
---|
1377 | DEVMETHOD(bus_read_ivar, at91_mci_read_ivar), |
---|
1378 | DEVMETHOD(bus_write_ivar, at91_mci_write_ivar), |
---|
1379 | |
---|
1380 | /* mmcbr_if */ |
---|
1381 | DEVMETHOD(mmcbr_update_ios, at91_mci_update_ios), |
---|
1382 | DEVMETHOD(mmcbr_request, at91_mci_request), |
---|
1383 | DEVMETHOD(mmcbr_get_ro, at91_mci_get_ro), |
---|
1384 | DEVMETHOD(mmcbr_acquire_host, at91_mci_acquire_host), |
---|
1385 | DEVMETHOD(mmcbr_release_host, at91_mci_release_host), |
---|
1386 | |
---|
1387 | DEVMETHOD_END |
---|
1388 | }; |
---|
1389 | |
---|
1390 | static driver_t at91_mci_driver = { |
---|
1391 | "at91_mci", |
---|
1392 | at91_mci_methods, |
---|
1393 | sizeof(struct at91_mci_softc), |
---|
1394 | }; |
---|
1395 | |
---|
1396 | static devclass_t at91_mci_devclass; |
---|
1397 | |
---|
1398 | #ifdef FDT |
---|
1399 | DRIVER_MODULE(at91_mci, simplebus, at91_mci_driver, at91_mci_devclass, NULL, |
---|
1400 | NULL); |
---|
1401 | #else |
---|
1402 | DRIVER_MODULE(at91_mci, atmelarm, at91_mci_driver, at91_mci_devclass, NULL, |
---|
1403 | NULL); |
---|
1404 | #endif |
---|
1405 | |
---|
1406 | MMC_DECLARE_BRIDGE(at91_mci); |
---|
1407 | DRIVER_MODULE(mmc, at91_mci, mmc_driver, mmc_devclass, NULL, NULL); |
---|
1408 | MODULE_DEPEND(at91_mci, mmc, 1, 1, 1); |
---|