source: rtems-libbsd/freebsd/sys/arm/at91/at91_mci.c @ d45899b

5-freebsd-12
Last change on this file since d45899b was d45899b, checked in by Sebastian Huber <sebastian.huber@…>, on Apr 27, 2018 at 6:39:22 AM

at91_mci: Get rid of bounce buffer

  • Property mode set to 100644
File size: 50.6 KB
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1#include <machine/rtems-bsd-kernel-space.h>
2
3/*-
4 * Copyright (c) 2006 Bernd Walter.  All rights reserved.
5 * Copyright (c) 2006 M. Warner Losh.  All rights reserved.
6 * Copyright (c) 2010 Greg Ansley.  All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30#include <rtems/bsd/local/opt_platform.h>
31
32#include <sys/cdefs.h>
33__FBSDID("$FreeBSD$");
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/bus.h>
38#include <sys/endian.h>
39#include <sys/kernel.h>
40#include <sys/lock.h>
41#include <sys/malloc.h>
42#include <sys/module.h>
43#include <sys/mutex.h>
44#include <rtems/bsd/sys/resource.h>
45#include <sys/rman.h>
46#include <sys/sysctl.h>
47
48#include <machine/bus.h>
49#include <machine/resource.h>
50#include <machine/intr.h>
51
52#include <arm/at91/at91var.h>
53#include <arm/at91/at91_mcireg.h>
54#include <arm/at91/at91_pdcreg.h>
55
56#include <dev/mmc/bridge.h>
57#include <dev/mmc/mmcbrvar.h>
58
59#ifdef FDT
60#include <dev/ofw/ofw_bus.h>
61#include <dev/ofw/ofw_bus_subr.h>
62#endif
63
64#include <rtems/bsd/local/mmcbr_if.h>
65
66#include <rtems/bsd/local/opt_at91.h>
67
68#ifdef __rtems__
69#include <bsp.h>
70#endif /* __rtems__ */
71#if defined(__rtems__) && defined(LIBBSP_ARM_ATSAM_BSP_H)
72#ifdef __rtems__
73#include <rtems/irq-extension.h>
74#include <libchip/chip.h>
75
76#define AT91_MCI_HAS_4WIRE 1
77
78#define at91_master_clock BOARD_MCK
79
80static sXdmad *pXdmad = &XDMAD_Instance;
81#endif /* __rtems__ */
82/*
83 * About running the MCI bus above 25MHz
84 *
85 * Historically, the MCI bus has been run at 30MHz on systems with a 60MHz
86 * master clock, in part due to a bug in dev/mmc.c making always request
87 * 30MHz, and in part over clocking the bus because 15MHz was too slow.
88 * Fixing that bug causes the mmc driver to request a 25MHz clock (as it
89 * should) and the logic in at91_mci_update_ios() picks the highest speed that
90 * doesn't exceed that limit.  With a 60MHz MCK that would be 15MHz, and
91 * that's a real performance buzzkill when you've been getting away with 30MHz
92 * all along.
93 *
94 * By defining AT91_MCI_ALLOW_OVERCLOCK (or setting the allow_overclock=1
95 * device hint or sysctl) you can enable logic in at91_mci_update_ios() to
96 * overlcock the SD bus a little by running it at MCK / 2 when the requested
97 * speed is 25MHz and the next highest speed is 15MHz or less.  This appears
98 * to work on virtually all SD cards, since it is what this driver has been
99 * doing prior to the introduction of this option, where the overclocking vs
100 * underclocking decision was automatically "overclock".  Modern SD cards can
101 * run at 45mhz/1-bit in standard mode (high speed mode enable commands not
102 * sent) without problems.
103 *
104 * Speaking of high-speed mode, the rm9200 manual says the MCI device supports
105 * the SD v1.0 specification and can run up to 50MHz.  This is interesting in
106 * that the SD v1.0 spec caps the speed at 25MHz; high speed mode was added in
107 * the v1.10 spec.  Furthermore, high speed mode doesn't just crank up the
108 * clock, it alters the signal timing.  The rm9200 MCI device doesn't support
109 * these altered timings.  So while speeds over 25MHz may work, they only work
110 * in what the SD spec calls "default" speed mode, and it amounts to violating
111 * the spec by overclocking the bus.
112 *
113 * If you also enable 4-wire mode it's possible transfers faster than 25MHz
114 * will fail.  On the AT91RM9200, due to bugs in the bus contention logic, if
115 * you have the USB host device and OHCI driver enabled will fail.  Even
116 * underclocking to 15MHz, intermittant overrun and underrun errors occur.
117 * Note that you don't even need to have usb devices attached to the system,
118 * the errors begin to occur as soon as the OHCI driver sets the register bit
119 * to enable periodic transfers.  It appears (based on brief investigation)
120 * that the usb host controller uses so much ASB bandwidth that sometimes the
121 * DMA for MCI transfers doesn't get a bus grant in time and data gets
122 * dropped.  Adding even a modicum of network activity changes the symptom
123 * from intermittant to very frequent.  Members of the AT91SAM9 family have
124 * corrected this problem, or are at least better about their use of the bus.
125 */
126#ifndef AT91_MCI_ALLOW_OVERCLOCK
127#define AT91_MCI_ALLOW_OVERCLOCK 1
128#endif
129
130/*
131 * Allocate 2 bounce buffers we'll use to endian-swap the data due to the rm9200
132 * erratum.  We use a pair of buffers because when reading that lets us begin
133 * endian-swapping the data in the first buffer while the DMA is reading into
134 * the second buffer.  (We can't use the same trick for writing because we might
135 * not get all the data in the 2nd buffer swapped before the hardware needs it;
136 * dealing with that would add complexity to the driver.)
137 *
138 * The buffers are sized at 16K each due to the way the busdma cache sync
139 * operations work on arm.  A dcache_inv_range() operation on a range larger
140 * than 16K gets turned into a dcache_wbinv_all().  That needlessly flushes the
141 * entire data cache, impacting overall system performance.
142 */
143#ifndef __rtems__
144#define BBCOUNT     2
145#define BBSIZE      (32*1024)
146#define MAX_BLOCKS  ((BBSIZE)/512)
147/* FIXME: It would be better to split the DMA up in that case like in the
148 * original driver. But that would need some rework. */
149#else /* __rtems__ */
150#define MAX_BLOCKS 32
151#endif /* __rtems__ */
152
153#ifndef __rtems__
154static int mci_debug;
155#else /* __rtems__ */
156#define mci_debug 0
157#endif /* __rtems__ */
158
159struct at91_mci_softc {
160        void *intrhand;                 /* Interrupt handle */
161        device_t dev;
162        int sc_cap;
163#define CAP_HAS_4WIRE           1       /* Has 4 wire bus */
164#define CAP_NEEDS_BYTESWAP      2       /* broken hardware needing bounce */
165#define CAP_MCI1_REV2XX         4       /* MCI 1 rev 2.x */
166        int flags;
167#define PENDING_CMD     0x01
168#define PENDING_STOP    0x02
169#define CMD_MULTIREAD   0x10
170#define CMD_MULTIWRITE  0x20
171        int has_4wire;
172        int allow_overclock;
173        struct resource *irq_res;       /* IRQ resource */
174        struct resource *mem_res;       /* Memory resource */
175        struct mtx sc_mtx;
176#ifdef __rtems__
177        RTEMS_INTERRUPT_LOCK_MEMBER(sc_lock)
178#endif /* __rtems__ */
179#ifndef __rtems__
180        bus_dma_tag_t dmatag;
181#endif /* __rtems__ */
182        struct mmc_host host;
183        int bus_busy;
184        struct mmc_request *req;
185        struct mmc_command *curcmd;
186#ifndef __rtems__
187        bus_dmamap_t bbuf_map[BBCOUNT];
188        char      *  bbuf_vaddr[BBCOUNT]; /* bounce bufs in KVA space */
189        uint32_t     bbuf_len[BBCOUNT];   /* len currently queued for bounce buf */
190        uint32_t     bbuf_curidx;         /* which bbuf is the active DMA buffer */
191        uint32_t     xfer_offset;         /* offset so far into caller's buf */
192#else /* __rtems__ */
193        uint32_t xdma_tx_channel;
194        uint32_t xdma_rx_channel;
195        uint8_t xdma_tx_perid;
196        uint8_t xdma_rx_perid;
197        sXdmadCfg xdma_tx_cfg;
198        sXdmadCfg xdma_rx_cfg;
199#endif /* __rtems__ */
200};
201
202/* bus entry points */
203static int at91_mci_probe(device_t dev);
204static int at91_mci_attach(device_t dev);
205static int at91_mci_detach(device_t dev);
206static void at91_mci_intr(void *);
207
208/* helper routines */
209static int at91_mci_activate(device_t dev);
210static void at91_mci_deactivate(device_t dev);
211static int at91_mci_is_mci1rev2xx(void);
212#ifndef __rtems__
213static void at91_mci_read_done(struct at91_mci_softc *sc, uint32_t sr);
214#endif /* __rtems__ */
215static void at91_mci_write_done(struct at91_mci_softc *sc, uint32_t sr);
216
217#ifndef __rtems__
218#define AT91_MCI_LOCK(_sc)              mtx_lock(&(_sc)->sc_mtx)
219#define AT91_MCI_UNLOCK(_sc)            mtx_unlock(&(_sc)->sc_mtx)
220#define AT91_MCI_LOCK_INIT(_sc) \
221        mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \
222            "mci", MTX_DEF)
223#define AT91_MCI_LOCK_DESTROY(_sc)      mtx_destroy(&_sc->sc_mtx);
224#define AT91_MCI_ASSERT_LOCKED(_sc)     mtx_assert(&_sc->sc_mtx, MA_OWNED);
225#define AT91_MCI_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
226#else /* __rtems__ */
227#define AT91_MCI_LOCK(_sc) \
228        rtems_interrupt_lock_context at91_mci_lock_context; \
229        rtems_interrupt_lock_acquire(&(_sc)->sc_lock, &at91_mci_lock_context)
230#define AT91_MCI_UNLOCK(_sc) \
231        rtems_interrupt_lock_release(&(_sc)->sc_lock, &at91_mci_lock_context)
232#define AT91_MCI_LOCK_INIT(_sc) \
233        rtems_interrupt_lock_initialize(&(_sc)->sc_lock, \
234            device_get_nameunit((_sc)->dev))
235#define AT91_MCI_LOCK_DESTROY(_sc) \
236        rtems_interrupt_lock_destroy(&(_sc)->sc_mtx)
237#define AT91_MCI_BUS_LOCK(_sc)          mtx_lock(&(_sc)->sc_mtx)
238#define AT91_MCI_BUS_UNLOCK(_sc)                mtx_unlock(&(_sc)->sc_mtx)
239#define AT91_MCI_BUS_LOCK_INIT(_sc) \
240        mtx_init(&_sc->sc_mtx, device_get_nameunit((_sc)->dev), \
241            "mci", MTX_DEF)
242#endif /* __rtems__ */
243
244static inline uint32_t
245RD4(struct at91_mci_softc *sc, bus_size_t off)
246{
247        return (bus_read_4(sc->mem_res, off));
248}
249
250static inline void
251WR4(struct at91_mci_softc *sc, bus_size_t off, uint32_t val)
252{
253        bus_write_4(sc->mem_res, off, val);
254}
255
256#ifndef __rtems__
257static void
258at91_bswap_buf(struct at91_mci_softc *sc, void * dptr, void * sptr, uint32_t memsize)
259{
260        uint32_t * dst = (uint32_t *)dptr;
261        uint32_t * src = (uint32_t *)sptr;
262        uint32_t   i;
263
264        /*
265         * If the hardware doesn't need byte-swapping, let bcopy() do the
266         * work.  Use bounce buffer even if we don't need byteswap, since
267         * buffer may straddle a page boundary, and we don't handle
268         * multi-segment transfers in hardware.  Seen from 'bsdlabel -w' which
269         * uses raw geom access to the volume.  Greg Ansley (gja (at)
270         * ansley.com)
271         */
272        if (!(sc->sc_cap & CAP_NEEDS_BYTESWAP)) {
273                memcpy(dptr, sptr, memsize);
274                return;
275        }
276
277        /*
278         * Nice performance boost for slightly unrolling this loop.
279         * (But very little extra boost for further unrolling it.)
280         */
281        for (i = 0; i < memsize; i += 16) {
282                *dst++ = bswap32(*src++);
283                *dst++ = bswap32(*src++);
284                *dst++ = bswap32(*src++);
285                *dst++ = bswap32(*src++);
286        }
287
288        /* Mop up the last 1-3 words, if any. */
289        for (i = 0; i < (memsize & 0x0F); i += 4) {
290                *dst++ = bswap32(*src++);
291        }
292}
293
294static void
295at91_mci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
296{
297        if (error != 0)
298                return;
299        *(bus_addr_t *)arg = segs[0].ds_addr;
300}
301#endif /* __rtems__ */
302
303static void
304at91_mci_pdc_disable(struct at91_mci_softc *sc)
305{
306#ifndef __rtems__
307        WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS);
308        WR4(sc, PDC_RPR, 0);
309        WR4(sc, PDC_RCR, 0);
310        WR4(sc, PDC_RNPR, 0);
311        WR4(sc, PDC_RNCR, 0);
312        WR4(sc, PDC_TPR, 0);
313        WR4(sc, PDC_TCR, 0);
314        WR4(sc, PDC_TNPR, 0);
315        WR4(sc, PDC_TNCR, 0);
316#else /* __rtems__ */
317        /* On SAMV71 there is no PDC but a DMAC */
318        XDMAD_StopTransfer(pXdmad, sc->xdma_rx_channel);
319        XDMAD_StopTransfer(pXdmad, sc->xdma_tx_channel);
320        WR4(sc, MCI_DMA, 0);
321#endif /* __rtems__ */
322}
323
324/*
325 * Reset the controller, then restore most of the current state.
326 *
327 * This is called after detecting an error.  It's also called after stopping a
328 * multi-block write, to un-wedge the device so that it will handle the NOTBUSY
329 * signal correctly.  See comments in at91_mci_stop_done() for more details.
330 */
331static void at91_mci_reset(struct at91_mci_softc *sc)
332{
333        uint32_t mr;
334        uint32_t sdcr;
335        uint32_t dtor;
336        uint32_t imr;
337
338        at91_mci_pdc_disable(sc);
339
340        /* save current state */
341
342        imr  = RD4(sc, MCI_IMR);
343#ifndef __rtems__
344        mr   = RD4(sc, MCI_MR) & 0x7fff;
345#else /* __rtems__ */
346        mr   = RD4(sc, MCI_MR);
347#endif /* __rtems__ */
348        sdcr = RD4(sc, MCI_SDCR);
349        dtor = RD4(sc, MCI_DTOR);
350
351        /* reset the controller */
352
353        WR4(sc, MCI_IDR, 0xffffffff);
354        WR4(sc, MCI_CR, MCI_CR_MCIDIS | MCI_CR_SWRST);
355
356        /* restore state */
357
358        WR4(sc, MCI_CR, MCI_CR_MCIEN|MCI_CR_PWSEN);
359        WR4(sc, MCI_MR, mr);
360        WR4(sc, MCI_SDCR, sdcr);
361        WR4(sc, MCI_DTOR, dtor);
362        WR4(sc, MCI_IER, imr);
363
364        /*
365         * Make sure sdio interrupts will fire.  Not sure why reading
366         * SR ensures that, but this is in the linux driver.
367         */
368
369        RD4(sc, MCI_SR);
370}
371
372static void
373at91_mci_init(device_t dev)
374{
375        struct at91_mci_softc *sc = device_get_softc(dev);
376        uint32_t val;
377
378        WR4(sc, MCI_CR, MCI_CR_MCIDIS | MCI_CR_SWRST); /* device into reset */
379        WR4(sc, MCI_IDR, 0xffffffff);           /* Turn off interrupts */
380        WR4(sc, MCI_DTOR, MCI_DTOR_DTOMUL_1M | 1);
381#ifndef __rtems__
382        val = MCI_MR_PDCMODE;
383#else /* __rtems__ */
384        val = 0;
385        val |= MCI_MR_RDPROOF | MCI_MR_WRPROOF;
386#endif /* __rtems__ */
387        val |= 0x34a;                           /* PWSDIV = 3; CLKDIV = 74 */
388//      if (sc->sc_cap & CAP_MCI1_REV2XX)
389//              val |= MCI_MR_RDPROOF | MCI_MR_WRPROOF;
390        WR4(sc, MCI_MR, val);
391#ifndef  AT91_MCI_SLOT_B
392        WR4(sc, MCI_SDCR, 0);                   /* SLOT A, 1 bit bus */
393#else
394        /*
395         * XXX Really should add second "unit" but nobody using using
396         * a two slot card that we know of. XXX
397         */
398        WR4(sc, MCI_SDCR, 1);                   /* SLOT B, 1 bit bus */
399#endif
400        /*
401         * Enable controller, including power-save.  The slower clock
402         * of the power-save mode is only in effect when there is no
403         * transfer in progress, so it can be left in this mode all
404         * the time.
405         */
406        WR4(sc, MCI_CR, MCI_CR_MCIEN|MCI_CR_PWSEN);
407}
408
409static void
410at91_mci_fini(device_t dev)
411{
412        struct at91_mci_softc *sc = device_get_softc(dev);
413
414        WR4(sc, MCI_IDR, 0xffffffff);           /* Turn off interrupts */
415        at91_mci_pdc_disable(sc);
416        WR4(sc, MCI_CR, MCI_CR_MCIDIS | MCI_CR_SWRST); /* device into reset */
417}
418
419static int
420at91_mci_probe(device_t dev)
421{
422#ifdef FDT
423        if (!ofw_bus_is_compatible(dev, "atmel,hsmci"))
424                return (ENXIO);
425#endif
426        device_set_desc(dev, "MCI mmc/sd host bridge");
427        return (0);
428}
429
430static int
431at91_mci_attach(device_t dev)
432{
433        struct at91_mci_softc *sc = device_get_softc(dev);
434        struct sysctl_ctx_list *sctx;
435        struct sysctl_oid *soid;
436        device_t child;
437#ifndef __rtems__
438        int err, i;
439#else /* __rtems__ */
440        int err;
441#endif /* __rtems__ */
442
443#ifdef __rtems__
444#ifdef LIBBSP_ARM_ATSAM_BSP_H
445        PMC_EnablePeripheral(ID_HSMCI);
446        sc->xdma_tx_channel = XDMAD_ALLOC_FAILED;
447        sc->xdma_rx_channel = XDMAD_ALLOC_FAILED;
448#endif /* LIBBSP_ARM_ATSAM_BSP_H */
449#endif /* __rtems__ */
450        sctx = device_get_sysctl_ctx(dev);
451        soid = device_get_sysctl_tree(dev);
452
453        sc->dev = dev;
454        sc->sc_cap = 0;
455#ifndef __rtems__
456        if (at91_is_rm92())
457                sc->sc_cap |= CAP_NEEDS_BYTESWAP;
458#endif /* __rtems__ */
459        /*
460         * MCI1 Rev 2 controllers need some workarounds, flag if so.
461         */
462        if (at91_mci_is_mci1rev2xx())
463                sc->sc_cap |= CAP_MCI1_REV2XX;
464
465        err = at91_mci_activate(dev);
466        if (err)
467                goto out;
468
469#ifdef __rtems__
470        eXdmadRC rc;
471
472        /* Prepare some configurations so they don't have to be fetched on every
473         * setup */
474        sc->xdma_rx_perid = XDMAIF_Get_ChannelNumber(ID_HSMCI,
475            XDMAD_TRANSFER_RX);
476        sc->xdma_tx_perid = XDMAIF_Get_ChannelNumber(ID_HSMCI,
477            XDMAD_TRANSFER_TX);
478        memset(&sc->xdma_rx_cfg, 0, sizeof(sc->xdma_rx_cfg));
479        sc->xdma_rx_cfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN |
480            XDMAC_CC_MBSIZE_SINGLE | XDMAC_CC_DSYNC_PER2MEM |
481            XDMAC_CC_SWREQ_HWR_CONNECTED | XDMAC_CC_MEMSET_NORMAL_MODE |
482            XDMAC_CC_CSIZE_CHK_1 | XDMAC_CC_DWIDTH_WORD |
483            XDMAC_CC_SIF_AHB_IF1 | XDMAC_CC_DIF_AHB_IF1 |
484            XDMAC_CC_SAM_FIXED_AM | XDMAC_CC_DAM_INCREMENTED_AM |
485            XDMAC_CC_PERID(
486                XDMAIF_Get_ChannelNumber(ID_HSMCI,XDMAD_TRANSFER_RX));
487        memset(&sc->xdma_tx_cfg, 0, sizeof(sc->xdma_tx_cfg));
488        sc->xdma_tx_cfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN |
489            XDMAC_CC_MBSIZE_SINGLE | XDMAC_CC_DSYNC_MEM2PER |
490            XDMAC_CC_SWREQ_HWR_CONNECTED | XDMAC_CC_MEMSET_NORMAL_MODE |
491            XDMAC_CC_CSIZE_CHK_1 | XDMAC_CC_DWIDTH_WORD |
492            XDMAC_CC_SIF_AHB_IF1 | XDMAC_CC_DIF_AHB_IF1 |
493            XDMAC_CC_SAM_INCREMENTED_AM | XDMAC_CC_DAM_FIXED_AM |
494            XDMAC_CC_PERID(
495                XDMAIF_Get_ChannelNumber(ID_HSMCI,XDMAD_TRANSFER_TX));
496
497        sc->xdma_tx_channel = XDMAD_AllocateChannel(pXdmad,
498            XDMAD_TRANSFER_MEMORY, ID_HSMCI);
499        if (sc->xdma_tx_channel == XDMAD_ALLOC_FAILED)
500                goto out;
501
502        /* FIXME: The two DMA channels are not really necessary for the driver.
503         * But the XDMAD interface does not allow to allocate one and use it
504         * into two directions. The current (2017-07-11) implementation of
505         * the XDMAD interface should work with it. So we might could try it. */
506        sc->xdma_rx_channel = XDMAD_AllocateChannel(pXdmad, ID_HSMCI,
507            XDMAD_TRANSFER_MEMORY);
508        if (sc->xdma_rx_channel == XDMAD_ALLOC_FAILED)
509                goto out;
510
511        rc = XDMAD_PrepareChannel(pXdmad, sc->xdma_rx_channel);
512        if (rc != XDMAD_OK)
513                goto out;
514
515        rc = XDMAD_PrepareChannel(pXdmad, sc->xdma_tx_channel);
516        if (rc != XDMAD_OK)
517                goto out;
518
519        AT91_MCI_BUS_LOCK_INIT(sc);
520#endif /* __rtems__ */
521        AT91_MCI_LOCK_INIT(sc);
522
523        at91_mci_fini(dev);
524        at91_mci_init(dev);
525
526#ifndef __rtems__
527        /*
528         * Allocate DMA tags and maps and bounce buffers.
529         *
530         * The parms in the tag_create call cause the dmamem_alloc call to
531         * create each bounce buffer as a single contiguous buffer of BBSIZE
532         * bytes aligned to a 4096 byte boundary.
533         *
534         * Do not use DMA_COHERENT for these buffers because that maps the
535         * memory as non-cachable, which prevents cache line burst fills/writes,
536         * which is something we need since we're trying to overlap the
537         * byte-swapping with the DMA operations.
538         */
539        err = bus_dma_tag_create(bus_get_dma_tag(dev), 4096, 0,
540            BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
541            BBSIZE, 1, BBSIZE, 0, NULL, NULL, &sc->dmatag);
542        if (err != 0)
543                goto out;
544
545        for (i = 0; i < BBCOUNT; ++i) {
546                err = bus_dmamem_alloc(sc->dmatag, (void **)&sc->bbuf_vaddr[i],
547                    BUS_DMA_NOWAIT, &sc->bbuf_map[i]);
548                if (err != 0)
549                        goto out;
550        }
551
552        /*
553         * Activate the interrupt
554         */
555        err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
556            NULL, at91_mci_intr, sc, &sc->intrhand);
557#else /* __rtems__ */
558        err = rtems_interrupt_handler_install(rman_get_start(sc->irq_res),
559            device_get_nameunit(dev), RTEMS_INTERRUPT_SHARED, at91_mci_intr,
560            sc);
561#endif /* __rtems__ */
562        if (err) {
563                AT91_MCI_LOCK_DESTROY(sc);
564                goto out;
565        }
566
567        /*
568         * Allow 4-wire to be initially set via #define.
569         * Allow a device hint to override that.
570         * Allow a sysctl to override that.
571         */
572#if defined(AT91_MCI_HAS_4WIRE) && AT91_MCI_HAS_4WIRE != 0
573        sc->has_4wire = 1;
574#endif
575        resource_int_value(device_get_name(dev), device_get_unit(dev),
576                           "4wire", &sc->has_4wire);
577        SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "4wire",
578            CTLFLAG_RW, &sc->has_4wire, 0, "has 4 wire SD Card bus");
579        if (sc->has_4wire)
580                sc->sc_cap |= CAP_HAS_4WIRE;
581
582        sc->allow_overclock = AT91_MCI_ALLOW_OVERCLOCK;
583        resource_int_value(device_get_name(dev), device_get_unit(dev),
584                           "allow_overclock", &sc->allow_overclock);
585        SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "allow_overclock",
586            CTLFLAG_RW, &sc->allow_overclock, 0,
587            "Allow up to 30MHz clock for 25MHz request when next highest speed 15MHz or less.");
588
589#ifndef __rtems__
590        SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "debug",
591            CTLFLAG_RWTUN, &mci_debug, 0, "enable debug output");
592#endif /* __rtems__ */
593
594        /*
595         * Our real min freq is master_clock/512, but upper driver layers are
596         * going to set the min speed during card discovery, and the right speed
597         * for that is 400kHz, so advertise a safe value just under that.
598         *
599         * For max speed, while the rm9200 manual says the max is 50mhz, it also
600         * says it supports only the SD v1.0 spec, which means the real limit is
601         * 25mhz. On the other hand, historical use has been to slightly violate
602         * the standard by running the bus at 30MHz.  For more information on
603         * that, see the comments at the top of this file.
604         */
605        sc->host.f_min = 375000;
606        sc->host.f_max = at91_master_clock / 2;
607        if (sc->host.f_max > 25000000)
608                sc->host.f_max = 25000000;
609        sc->host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340;
610        sc->host.caps = 0;
611        if (sc->sc_cap & CAP_HAS_4WIRE)
612                sc->host.caps |= MMC_CAP_4_BIT_DATA;
613
614        child = device_add_child(dev, "mmc", 0);
615#ifdef __rtems__
616        (void)child;
617#endif /* __rtems__ */
618        device_set_ivars(dev, &sc->host);
619        err = bus_generic_attach(dev);
620out:
621        if (err)
622                at91_mci_deactivate(dev);
623        return (err);
624}
625
626static int
627at91_mci_detach(device_t dev)
628{
629#ifndef __rtems__
630        struct at91_mci_softc *sc = device_get_softc(dev);
631#endif /* __rtems__ */
632
633        at91_mci_fini(dev);
634        at91_mci_deactivate(dev);
635
636#ifndef __rtems__
637        bus_dmamem_free(sc->dmatag, sc->bbuf_vaddr[0], sc->bbuf_map[0]);
638        bus_dmamem_free(sc->dmatag, sc->bbuf_vaddr[1], sc->bbuf_map[1]);
639        bus_dma_tag_destroy(sc->dmatag);
640#endif /* __rtems__ */
641
642        return (EBUSY); /* XXX */
643}
644
645static int
646at91_mci_activate(device_t dev)
647{
648        struct at91_mci_softc *sc;
649        int rid;
650
651        sc = device_get_softc(dev);
652        rid = 0;
653        sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
654            RF_ACTIVE);
655        if (sc->mem_res == NULL)
656                goto errout;
657
658        rid = 0;
659        sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
660            RF_ACTIVE);
661        if (sc->irq_res == NULL)
662                goto errout;
663
664        return (0);
665errout:
666        at91_mci_deactivate(dev);
667        return (ENOMEM);
668}
669
670static void
671at91_mci_deactivate(device_t dev)
672{
673        struct at91_mci_softc *sc;
674
675        sc = device_get_softc(dev);
676        if (sc->intrhand)
677                bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
678        sc->intrhand = NULL;
679        bus_generic_detach(sc->dev);
680        if (sc->mem_res)
681                bus_release_resource(dev, SYS_RES_MEMORY,
682                    rman_get_rid(sc->mem_res), sc->mem_res);
683        sc->mem_res = NULL;
684        if (sc->irq_res)
685                bus_release_resource(dev, SYS_RES_IRQ,
686                    rman_get_rid(sc->irq_res), sc->irq_res);
687        sc->irq_res = NULL;
688#ifdef __rtems__
689        if (sc->xdma_rx_channel != XDMAD_ALLOC_FAILED) {
690                XDMAD_FreeChannel(pXdmad, sc->xdma_rx_channel);
691        }
692        if (sc->xdma_tx_channel != XDMAD_ALLOC_FAILED) {
693                XDMAD_FreeChannel(pXdmad, sc->xdma_tx_channel);
694        }
695#endif /* __rtems__ */
696        return;
697}
698
699static int
700at91_mci_is_mci1rev2xx(void)
701{
702
703#ifndef __rtems__
704        switch (soc_info.type) {
705        case AT91_T_SAM9260:
706        case AT91_T_SAM9263:
707        case AT91_T_CAP9:
708        case AT91_T_SAM9G10:
709        case AT91_T_SAM9G20:
710        case AT91_T_SAM9RL:
711                return(1);
712        default:
713                return (0);
714        }
715#else /* __rtems__ */
716        /* Currently only supports the SAM V71 */
717        return (1);
718#endif /* __rtems__ */
719}
720
721static int
722at91_mci_update_ios(device_t brdev, device_t reqdev)
723{
724        struct at91_mci_softc *sc;
725        struct mmc_ios *ios;
726        uint32_t clkdiv;
727        uint32_t freq;
728
729        sc = device_get_softc(brdev);
730        ios = &sc->host.ios;
731
732        /*
733         * Calculate our closest available clock speed that doesn't exceed the
734         * requested speed.
735         *
736         * When overclocking is allowed, the requested clock is 25MHz, the
737         * computed frequency is 15MHz or smaller and clockdiv is 1, use
738         * clockdiv of 0 to double that.  If less than 12.5MHz, double
739         * regardless of the overclocking setting.
740         *
741         * Whatever we come up with, store it back into ios->clock so that the
742         * upper layer drivers can report the actual speed of the bus.
743         */
744        if (ios->clock == 0) {
745                WR4(sc, MCI_CR, MCI_CR_MCIDIS);
746                clkdiv = 0;
747        } else {
748                WR4(sc, MCI_CR, MCI_CR_MCIEN|MCI_CR_PWSEN);
749                if ((at91_master_clock % (ios->clock * 2)) == 0)
750                        clkdiv = ((at91_master_clock / ios->clock) / 2) - 1;
751                else
752                        clkdiv = (at91_master_clock / ios->clock) / 2;
753                freq = at91_master_clock / ((clkdiv+1) * 2);
754                if (clkdiv == 1 && ios->clock == 25000000 && freq <= 15000000) {
755                        if (sc->allow_overclock || freq <= 12500000) {
756                                clkdiv = 0;
757                                freq = at91_master_clock / ((clkdiv+1) * 2);
758                        }
759                }
760                ios->clock = freq;
761        }
762        if (ios->bus_width == bus_width_4)
763                WR4(sc, MCI_SDCR, RD4(sc, MCI_SDCR) | MCI_SDCR_SDCBUS);
764        else
765                WR4(sc, MCI_SDCR, RD4(sc, MCI_SDCR) & ~MCI_SDCR_SDCBUS);
766        WR4(sc, MCI_MR, (RD4(sc, MCI_MR) & ~MCI_MR_CLKDIV) | clkdiv);
767        /* Do we need a settle time here? */
768        /* XXX We need to turn the device on/off here with a GPIO pin */
769        return (0);
770}
771
772#ifdef __rtems__
773static LinkedListDescriporView1 dma_desc[MAX_BLOCKS];
774
775static void
776at91_mci_setup_xdma(struct at91_mci_softc *sc, bool read, uint32_t block_size,
777    uint32_t block_count, void *data, uint32_t len)
778{
779        sXdmadCfg *xdma_cfg;
780        uint32_t xdma_channel;
781        const uint32_t xdma_cndc = XDMAC_CNDC_NDVIEW_NDV1 |
782            XDMAC_CNDC_NDE_DSCR_FETCH_EN |
783            XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED |
784            XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED;
785        const uint32_t sa_rdr = (uint32_t)(sc->mem_res->r_bushandle + MCI_RDR);
786        const uint32_t da_tdr = (uint32_t)(sc->mem_res->r_bushandle + MCI_TDR);
787        const uint32_t xdma_interrupt = XDMAC_CIE_BIE | XDMAC_CIE_DIE |
788            XDMAC_CIE_FIE | XDMAC_CIE_RBIE | XDMAC_CIE_WBIE | XDMAC_CIE_ROIE;
789        eXdmadRC rc;
790        size_t i;
791
792        if (read) {
793                xdma_cfg = &sc->xdma_rx_cfg;
794                xdma_channel = sc->xdma_rx_channel;
795        } else {
796                xdma_cfg = &sc->xdma_tx_cfg;
797                xdma_channel = sc->xdma_tx_channel;
798        }
799
800        for (i = 0; i < block_count; ++i) {
801                if (read) {
802                        dma_desc[i].mbr_sa = sa_rdr;
803                        dma_desc[i].mbr_da = ((uint32_t)data) + i * block_size;
804                } else {
805                        dma_desc[i].mbr_sa = ((uint32_t)data) + i * block_size;
806                        dma_desc[i].mbr_da = da_tdr;
807                }
808                dma_desc[i].mbr_ubc = XDMA_UBC_NVIEW_NDV1 |
809                    XDMA_UBC_NDEN_UPDATED | (block_size/4);
810                if (i == block_count - 1) {
811                        dma_desc[i].mbr_ubc |= XDMA_UBC_NDE_FETCH_DIS;
812                        dma_desc[i].mbr_nda = 0;
813                } else {
814                        dma_desc[i].mbr_ubc |= XDMA_UBC_NDE_FETCH_EN;
815                        dma_desc[i].mbr_nda = (uint32_t) &dma_desc[i+1];
816                }
817        }
818
819        rc = XDMAD_ConfigureTransfer(pXdmad, xdma_channel, xdma_cfg, xdma_cndc,
820            (uint32_t)dma_desc, xdma_interrupt);
821        if (rc != XDMAD_OK)
822                panic("Could not configure XDMA: %d.", rc);
823
824        /* FIXME: Is that correct? */
825        if (read) {
826                rtems_cache_invalidate_multiple_data_lines(data, len);
827        } else {
828                rtems_cache_flush_multiple_data_lines(data, len);
829        }
830        rtems_cache_flush_multiple_data_lines(dma_desc, sizeof(dma_desc));
831
832        rc = XDMAD_StartTransfer(pXdmad, xdma_channel);
833        if (rc != XDMAD_OK)
834                panic("Could not start XDMA: %d.", rc);
835
836}
837#endif /* __rtems__ */
838static void
839at91_mci_start_cmd(struct at91_mci_softc *sc, struct mmc_command *cmd)
840{
841        uint32_t cmdr, mr;
842        struct mmc_data *data;
843#ifdef __rtems__
844        uint32_t block_count;
845        uint32_t block_size;
846#endif /* __rtems__ */
847
848        sc->curcmd = cmd;
849        data = cmd->data;
850
851        /* XXX Upper layers don't always set this */
852        cmd->mrq = sc->req;
853
854        /* Begin setting up command register. */
855
856        cmdr = cmd->opcode;
857
858        if (sc->host.ios.bus_mode == opendrain)
859                cmdr |= MCI_CMDR_OPDCMD;
860
861        /* Set up response handling.  Allow max timeout for responses. */
862
863        if (MMC_RSP(cmd->flags) == MMC_RSP_NONE)
864                cmdr |= MCI_CMDR_RSPTYP_NO;
865        else {
866                cmdr |= MCI_CMDR_MAXLAT;
867                if (cmd->flags & MMC_RSP_136)
868                        cmdr |= MCI_CMDR_RSPTYP_136;
869                else
870                        cmdr |= MCI_CMDR_RSPTYP_48;
871        }
872
873        /*
874         * If there is no data transfer, just set up the right interrupt mask
875         * and start the command.
876         *
877         * The interrupt mask needs to be CMDRDY plus all non-data-transfer
878         * errors. It's important to leave the transfer-related errors out, to
879         * avoid spurious timeout or crc errors on a STOP command following a
880         * multiblock read.  When a multiblock read is in progress, sending a
881         * STOP in the middle of a block occasionally triggers such errors, but
882         * we're totally disinterested in them because we've already gotten all
883         * the data we wanted without error before sending the STOP command.
884         */
885
886        if (data == NULL) {
887                uint32_t ier = MCI_SR_CMDRDY |
888                    MCI_SR_RTOE | MCI_SR_RENDE |
889                    MCI_SR_RCRCE | MCI_SR_RDIRE | MCI_SR_RINDE;
890
891                at91_mci_pdc_disable(sc);
892
893                if (cmd->opcode == MMC_STOP_TRANSMISSION)
894                        cmdr |= MCI_CMDR_TRCMD_STOP;
895
896                /* Ignore response CRC on CMD2 and ACMD41, per standard. */
897
898                if (cmd->opcode == MMC_SEND_OP_COND ||
899                    cmd->opcode == ACMD_SD_SEND_OP_COND)
900                        ier &= ~MCI_SR_RCRCE;
901
902                if (mci_debug)
903                        printf("CMDR %x (opcode %d) ARGR %x no data\n",
904                            cmdr, cmd->opcode, cmd->arg);
905
906                WR4(sc, MCI_ARGR, cmd->arg);
907                WR4(sc, MCI_CMDR, cmdr);
908                WR4(sc, MCI_IDR, 0xffffffff);
909                WR4(sc, MCI_IER, ier);
910                return;
911        }
912
913        /* There is data, set up the transfer-related parts of the command. */
914
915        if (data->flags & MMC_DATA_READ)
916                cmdr |= MCI_CMDR_TRDIR;
917
918        if (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE))
919                cmdr |= MCI_CMDR_TRCMD_START;
920
921        if (data->flags & MMC_DATA_STREAM)
922                cmdr |= MCI_CMDR_TRTYP_STREAM;
923        else if (data->flags & MMC_DATA_MULTI) {
924                cmdr |= MCI_CMDR_TRTYP_MULTIPLE;
925                sc->flags |= (data->flags & MMC_DATA_READ) ?
926                    CMD_MULTIREAD : CMD_MULTIWRITE;
927        }
928
929        /*
930         * Disable PDC until we're ready.
931         *
932         * Set block size and turn on PDC mode for dma xfer.
933         * Note that the block size is the smaller of the amount of data to be
934         * transferred, or 512 bytes.  The 512 size is fixed by the standard;
935         * smaller blocks are possible, but never larger.
936         */
937
938#ifndef __rtems__
939        WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS);
940
941        mr = RD4(sc,MCI_MR) & ~MCI_MR_BLKLEN;
942        mr |=  min(data->len, 512) << 16;
943        WR4(sc, MCI_MR, mr | MCI_MR_PDCMODE|MCI_MR_PDCPADV);
944
945        /*
946         * Set up DMA.
947         *
948         * Use bounce buffers even if we don't need to byteswap, because doing
949         * multi-block IO with large DMA buffers is way fast (compared to
950         * single-block IO), even after incurring the overhead of also copying
951         * from/to the caller's buffers (which may be in non-contiguous physical
952         * pages).
953         *
954         * In an ideal non-byteswap world we could create a dma tag that allows
955         * for discontiguous segments and do the IO directly from/to the
956         * caller's buffer(s), using ENDRX/ENDTX interrupts to chain the
957         * discontiguous buffers through the PDC. Someday.
958         *
959         * If a read is bigger than 2k, split it in half so that we can start
960         * byte-swapping the first half while the second half is on the wire.
961         * It would be best if we could split it into 8k chunks, but we can't
962         * always keep up with the byte-swapping due to other system activity,
963         * and if an RXBUFF interrupt happens while we're still handling the
964         * byte-swap from the prior buffer (IE, we haven't returned from
965         * handling the prior interrupt yet), then data will get dropped on the
966         * floor and we can't easily recover from that.  The right fix for that
967         * would be to have the interrupt handling only keep the DMA flowing and
968         * enqueue filled buffers to be byte-swapped in a non-interrupt context.
969         * Even that won't work on the write side of things though; in that
970         * context we have to have all the data ready to go before starting the
971         * dma.
972         *
973         * XXX what about stream transfers?
974         */
975        sc->xfer_offset = 0;
976        sc->bbuf_curidx = 0;
977#else /* __rtems__ */
978        mr = RD4(sc,MCI_MR);
979        WR4(sc, MCI_MR, mr | MCI_MR_PDCPADV);
980
981        WR4(sc, MCI_DMA, MCI_DMA_DMAEN | MCI_DMA_CHKSIZE_1);
982
983        block_size = min(data->len, 512);
984        block_count = data->len / block_size;
985        WR4(sc, MCI_BLKR, (block_size << 16) | block_count);
986#endif /* __rtems__ */
987
988        if (data->flags & (MMC_DATA_READ | MMC_DATA_WRITE)) {
989#ifndef __rtems__
990                uint32_t len;
991                uint32_t remaining = data->len;
992                bus_addr_t paddr;
993                int err;
994
995                if (remaining > (BBCOUNT*BBSIZE))
996                        panic("IO read size exceeds MAXDATA\n");
997#endif /* __rtems__ */
998
999                if (data->flags & MMC_DATA_READ) {
1000#ifndef __rtems__
1001                        if (remaining > 2048) // XXX
1002                                len = remaining / 2;
1003                        else
1004                                len = remaining;
1005                        err = bus_dmamap_load(sc->dmatag, sc->bbuf_map[0],
1006                            sc->bbuf_vaddr[0], len, at91_mci_getaddr,
1007                            &paddr, BUS_DMA_NOWAIT);
1008                        if (err != 0)
1009                                panic("IO read dmamap_load failed\n");
1010                        bus_dmamap_sync(sc->dmatag, sc->bbuf_map[0],
1011                            BUS_DMASYNC_PREREAD);
1012                        WR4(sc, PDC_RPR, paddr);
1013                        WR4(sc, PDC_RCR, len / 4);
1014                        sc->bbuf_len[0] = len;
1015                        remaining -= len;
1016                        if (remaining == 0) {
1017                                sc->bbuf_len[1] = 0;
1018                        } else {
1019                                len = remaining;
1020                                err = bus_dmamap_load(sc->dmatag, sc->bbuf_map[1],
1021                                    sc->bbuf_vaddr[1], len, at91_mci_getaddr,
1022                                    &paddr, BUS_DMA_NOWAIT);
1023                                if (err != 0)
1024                                        panic("IO read dmamap_load failed\n");
1025                                bus_dmamap_sync(sc->dmatag, sc->bbuf_map[1],
1026                                    BUS_DMASYNC_PREREAD);
1027                                WR4(sc, PDC_RNPR, paddr);
1028                                WR4(sc, PDC_RNCR, len / 4);
1029                                sc->bbuf_len[1] = len;
1030                                remaining -= len;
1031                        }
1032                        WR4(sc, PDC_PTCR, PDC_PTCR_RXTEN);
1033#else /* __rtems__ */
1034                        at91_mci_setup_xdma(sc, true, block_size, block_count,
1035                            data->data, data->len);
1036#endif /* __rtems__ */
1037                } else {
1038#ifndef __rtems__
1039                        len = min(BBSIZE, remaining);
1040                        at91_bswap_buf(sc, sc->bbuf_vaddr[0], data->data, len);
1041                        err = bus_dmamap_load(sc->dmatag, sc->bbuf_map[0],
1042                            sc->bbuf_vaddr[0], len, at91_mci_getaddr,
1043                            &paddr, BUS_DMA_NOWAIT);
1044                        if (err != 0)
1045                                panic("IO write dmamap_load failed\n");
1046                        bus_dmamap_sync(sc->dmatag, sc->bbuf_map[0],
1047                            BUS_DMASYNC_PREWRITE);
1048                        /*
1049                         * Erratum workaround:  PDC transfer length on a write
1050                         * must not be smaller than 12 bytes (3 words); only
1051                         * blklen bytes (set above) are actually transferred.
1052                         */
1053                        WR4(sc, PDC_TPR,paddr);
1054                        WR4(sc, PDC_TCR, (len < 12) ? 3 : len / 4);
1055                        sc->bbuf_len[0] = len;
1056                        remaining -= len;
1057                        if (remaining == 0) {
1058                                sc->bbuf_len[1] = 0;
1059                        } else {
1060                                len = remaining;
1061                                at91_bswap_buf(sc, sc->bbuf_vaddr[1],
1062                                    ((char *)data->data)+BBSIZE, len);
1063                                err = bus_dmamap_load(sc->dmatag, sc->bbuf_map[1],
1064                                    sc->bbuf_vaddr[1], len, at91_mci_getaddr,
1065                                    &paddr, BUS_DMA_NOWAIT);
1066                                if (err != 0)
1067                                        panic("IO write dmamap_load failed\n");
1068                                bus_dmamap_sync(sc->dmatag, sc->bbuf_map[1],
1069                                    BUS_DMASYNC_PREWRITE);
1070                                WR4(sc, PDC_TNPR, paddr);
1071                                WR4(sc, PDC_TNCR, (len < 12) ? 3 : len / 4);
1072                                sc->bbuf_len[1] = len;
1073                                remaining -= len;
1074                        }
1075                        /* do not enable PDC xfer until CMDRDY asserted */
1076#else /* __rtems__ */
1077                        at91_mci_setup_xdma(sc, false, block_size, block_count,
1078                            data->data, data->len);
1079#endif /* __rtems__ */
1080                }
1081                data->xfer_len = 0; /* XXX what's this? appears to be unused. */
1082        }
1083
1084        if (mci_debug)
1085                printf("CMDR %x (opcode %d) ARGR %x with data len %d\n",
1086                       cmdr, cmd->opcode, cmd->arg, cmd->data->len);
1087
1088        WR4(sc, MCI_ARGR, cmd->arg);
1089        WR4(sc, MCI_CMDR, cmdr);
1090        WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_CMDRDY);
1091}
1092
1093static void
1094at91_mci_next_operation(struct at91_mci_softc *sc)
1095{
1096        struct mmc_request *req;
1097
1098        req = sc->req;
1099        if (req == NULL)
1100                return;
1101
1102        if (sc->flags & PENDING_CMD) {
1103                sc->flags &= ~PENDING_CMD;
1104                at91_mci_start_cmd(sc, req->cmd);
1105                return;
1106        } else if (sc->flags & PENDING_STOP) {
1107                sc->flags &= ~PENDING_STOP;
1108                at91_mci_start_cmd(sc, req->stop);
1109                return;
1110        }
1111
1112        WR4(sc, MCI_IDR, 0xffffffff);
1113        sc->req = NULL;
1114        sc->curcmd = NULL;
1115        //printf("req done\n");
1116        req->done(req);
1117}
1118
1119static int
1120at91_mci_request(device_t brdev, device_t reqdev, struct mmc_request *req)
1121{
1122        struct at91_mci_softc *sc = device_get_softc(brdev);
1123
1124        AT91_MCI_LOCK(sc);
1125        if (sc->req != NULL) {
1126                AT91_MCI_UNLOCK(sc);
1127                return (EBUSY);
1128        }
1129        //printf("new req\n");
1130        sc->req = req;
1131        sc->flags = PENDING_CMD;
1132        if (sc->req->stop)
1133                sc->flags |= PENDING_STOP;
1134        at91_mci_next_operation(sc);
1135        AT91_MCI_UNLOCK(sc);
1136        return (0);
1137}
1138
1139static int
1140at91_mci_get_ro(device_t brdev, device_t reqdev)
1141{
1142        return (0);
1143}
1144
1145static int
1146at91_mci_acquire_host(device_t brdev, device_t reqdev)
1147{
1148        struct at91_mci_softc *sc = device_get_softc(brdev);
1149        int err = 0;
1150
1151#ifndef __rtems__
1152        AT91_MCI_LOCK(sc);
1153#else /* __rtems__ */
1154        AT91_MCI_BUS_LOCK(sc);
1155#endif /* __rtems__ */
1156        while (sc->bus_busy)
1157                msleep(sc, &sc->sc_mtx, PZERO, "mciah", hz / 5);
1158        sc->bus_busy++;
1159#ifndef __rtems__
1160        AT91_MCI_UNLOCK(sc);
1161#else /* __rtems__ */
1162        AT91_MCI_BUS_UNLOCK(sc);
1163#endif /* __rtems__ */
1164        return (err);
1165}
1166
1167static int
1168at91_mci_release_host(device_t brdev, device_t reqdev)
1169{
1170        struct at91_mci_softc *sc = device_get_softc(brdev);
1171
1172#ifndef __rtems__
1173        AT91_MCI_LOCK(sc);
1174#else /* __rtems__ */
1175        AT91_MCI_BUS_LOCK(sc);
1176#endif /* __rtems__ */
1177        sc->bus_busy--;
1178        wakeup(sc);
1179#ifndef __rtems__
1180        AT91_MCI_UNLOCK(sc);
1181#else /* __rtems__ */
1182        AT91_MCI_BUS_UNLOCK(sc);
1183#endif /* __rtems__ */
1184        return (0);
1185}
1186
1187#ifndef __rtems__
1188static void
1189at91_mci_read_done(struct at91_mci_softc *sc, uint32_t sr)
1190{
1191        struct mmc_command *cmd = sc->curcmd;
1192        char * dataptr = (char *)cmd->data->data;
1193        uint32_t curidx = sc->bbuf_curidx;
1194        uint32_t len = sc->bbuf_len[curidx];
1195
1196        /*
1197         * We arrive here when a DMA transfer for a read is done, whether it's
1198         * a single or multi-block read.
1199         *
1200         * We byte-swap the buffer that just completed, and if that is the
1201         * last buffer that's part of this read then we move on to the next
1202         * operation, otherwise we wait for another ENDRX for the next bufer.
1203         */
1204
1205        bus_dmamap_sync(sc->dmatag, sc->bbuf_map[curidx], BUS_DMASYNC_POSTREAD);
1206        bus_dmamap_unload(sc->dmatag, sc->bbuf_map[curidx]);
1207
1208        at91_bswap_buf(sc, dataptr + sc->xfer_offset, sc->bbuf_vaddr[curidx], len);
1209
1210        if (mci_debug) {
1211                printf("read done sr %x curidx %d len %d xfer_offset %d\n",
1212                       sr, curidx, len, sc->xfer_offset);
1213        }
1214
1215        sc->xfer_offset += len;
1216        sc->bbuf_curidx = !curidx; /* swap buffers */
1217
1218        /*
1219         * If we've transferred all the data, move on to the next operation.
1220         *
1221         * If we're still transferring the last buffer, RNCR is already zero but
1222         * we have to write a zero anyway to clear the ENDRX status so we don't
1223         * re-interrupt until the last buffer is done.
1224         */
1225        if (sc->xfer_offset == cmd->data->len) {
1226                WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS);
1227                cmd->error = MMC_ERR_NONE;
1228                at91_mci_next_operation(sc);
1229        } else {
1230                WR4(sc, PDC_RNCR, 0);
1231                WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_ENDRX);
1232        }
1233}
1234#endif /* __rtems__ */
1235
1236static void
1237at91_mci_write_done(struct at91_mci_softc *sc, uint32_t sr)
1238{
1239        struct mmc_command *cmd = sc->curcmd;
1240
1241        /*
1242         * We arrive here when the entire DMA transfer for a write is done,
1243         * whether it's a single or multi-block write.  If it's multi-block we
1244         * have to immediately move on to the next operation which is to send
1245         * the stop command.  If it's a single-block transfer we need to wait
1246         * for NOTBUSY, but if that's already asserted we can avoid another
1247         * interrupt and just move on to completing the request right away.
1248         */
1249
1250        WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS);
1251
1252#ifndef __rtems__
1253        bus_dmamap_sync(sc->dmatag, sc->bbuf_map[sc->bbuf_curidx],
1254            BUS_DMASYNC_POSTWRITE);
1255        bus_dmamap_unload(sc->dmatag, sc->bbuf_map[sc->bbuf_curidx]);
1256#endif /* __rtems__ */
1257
1258        if ((cmd->data->flags & MMC_DATA_MULTI) || (sr & MCI_SR_NOTBUSY)) {
1259                cmd->error = MMC_ERR_NONE;
1260                at91_mci_next_operation(sc);
1261        } else {
1262                WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_NOTBUSY);
1263        }
1264}
1265
1266static void
1267at91_mci_notbusy(struct at91_mci_softc *sc)
1268{
1269        struct mmc_command *cmd = sc->curcmd;
1270
1271        /*
1272         * We arrive here by either completion of a single-block write, or
1273         * completion of the stop command that ended a multi-block write (and,
1274         * I suppose, after a card-select or erase, but I haven't tested
1275         * those).  Anyway, we're done and it's time to move on to the next
1276         * command.
1277         */
1278
1279        cmd->error = MMC_ERR_NONE;
1280        at91_mci_next_operation(sc);
1281}
1282
1283static void
1284at91_mci_stop_done(struct at91_mci_softc *sc, uint32_t sr)
1285{
1286        struct mmc_command *cmd = sc->curcmd;
1287
1288        /*
1289         * We arrive here after receiving CMDRDY for a MMC_STOP_TRANSMISSION
1290         * command.  Depending on the operation being stopped, we may have to
1291         * do some unusual things to work around hardware bugs.
1292         */
1293
1294        /*
1295         * This is known to be true of at91rm9200 hardware; it may or may not
1296         * apply to more recent chips:
1297         *
1298         * After stopping a multi-block write, the NOTBUSY bit in MCI_SR does
1299         * not properly reflect the actual busy state of the card as signaled
1300         * on the DAT0 line; it always claims the card is not-busy.  If we
1301         * believe that and let operations continue, following commands will
1302         * fail with response timeouts (except of course MMC_SEND_STATUS -- it
1303         * indicates the card is busy in the PRG state, which was the smoking
1304         * gun that showed MCI_SR NOTBUSY was not tracking DAT0 correctly).
1305         *
1306         * The atmel docs are emphatic: "This flag [NOTBUSY] must be used only
1307         * for Write Operations."  I guess technically since we sent a stop
1308         * it's not a write operation anymore.  But then just what did they
1309         * think it meant for the stop command to have "...an optional busy
1310         * signal transmitted on the data line" according to the SD spec?
1311         *
1312         * I tried a variety of things to un-wedge the MCI and get the status
1313         * register to reflect NOTBUSY correctly again, but the only thing
1314         * that worked was a full device reset.  It feels like an awfully big
1315         * hammer, but doing a full reset after every multiblock write is
1316         * still faster than doing single-block IO (by almost two orders of
1317         * magnitude: 20KB/sec improves to about 1.8MB/sec best case).
1318         *
1319         * After doing the reset, wait for a NOTBUSY interrupt before
1320         * continuing with the next operation.
1321         *
1322         * This workaround breaks multiwrite on the rev2xx parts, but some other
1323         * workaround is needed.
1324         */
1325        if ((sc->flags & CMD_MULTIWRITE) && (sc->sc_cap & CAP_NEEDS_BYTESWAP)) {
1326                at91_mci_reset(sc);
1327                WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_NOTBUSY);
1328                return;
1329        }
1330
1331        /*
1332         * This is known to be true of at91rm9200 hardware; it may or may not
1333         * apply to more recent chips:
1334         *
1335         * After stopping a multi-block read, loop to read and discard any
1336         * data that coasts in after we sent the stop command.  The docs don't
1337         * say anything about it, but empirical testing shows that 1-3
1338         * additional words of data get buffered up in some unmentioned
1339         * internal fifo and if we don't read and discard them here they end
1340         * up on the front of the next read DMA transfer we do.
1341         *
1342         * This appears to be unnecessary for rev2xx parts.
1343         */
1344        if ((sc->flags & CMD_MULTIREAD) && (sc->sc_cap & CAP_NEEDS_BYTESWAP)) {
1345                uint32_t sr;
1346                int count = 0;
1347
1348                do {
1349                        sr = RD4(sc, MCI_SR);
1350                        if (sr & MCI_SR_RXRDY) {
1351                                RD4(sc,  MCI_RDR);
1352                                ++count;
1353                        }
1354                } while (sr & MCI_SR_RXRDY);
1355                at91_mci_reset(sc);
1356        }
1357
1358        cmd->error = MMC_ERR_NONE;
1359        at91_mci_next_operation(sc);
1360
1361}
1362
1363static void
1364at91_mci_cmdrdy(struct at91_mci_softc *sc, uint32_t sr)
1365{
1366        struct mmc_command *cmd = sc->curcmd;
1367        int i;
1368
1369        if (cmd == NULL)
1370                return;
1371
1372        /*
1373         * We get here at the end of EVERY command.  We retrieve the command
1374         * response (if any) then decide what to do next based on the command.
1375         */
1376
1377        if (cmd->flags & MMC_RSP_PRESENT) {
1378                for (i = 0; i < ((cmd->flags & MMC_RSP_136) ? 4 : 1); i++) {
1379                        cmd->resp[i] = RD4(sc, MCI_RSPR + i * 4);
1380                        if (mci_debug)
1381                                printf("RSPR[%d] = %x sr=%x\n", i, cmd->resp[i],  sr);
1382                }
1383        }
1384
1385        /*
1386         * If this was a stop command, go handle the various special
1387         * conditions (read: bugs) that have to be dealt with following a stop.
1388         */
1389        if (cmd->opcode == MMC_STOP_TRANSMISSION) {
1390                at91_mci_stop_done(sc, sr);
1391                return;
1392        }
1393
1394        /*
1395         * If this command can continue to assert BUSY beyond the response then
1396         * we need to wait for NOTBUSY before the command is really done.
1397         *
1398         * Note that this may not work properly on the at91rm9200.  It certainly
1399         * doesn't work for the STOP command that follows a multi-block write,
1400         * so post-stop CMDRDY is handled separately; see the special handling
1401         * in at91_mci_stop_done().
1402         *
1403         * Beside STOP, there are other R1B-type commands that use the busy
1404         * signal after CMDRDY: CMD7 (card select), CMD28-29 (write protect),
1405         * CMD38 (erase). I haven't tested any of them, but I rather expect
1406         * them all to have the same sort of problem with MCI_SR not actually
1407         * reflecting the state of the DAT0-line busy indicator.  So this code
1408         * may need to grow some sort of special handling for them too. (This
1409         * just in: CMD7 isn't a problem right now because dev/mmc.c incorrectly
1410         * sets the response flags to R1 rather than R1B.) XXX
1411         */
1412        if ((cmd->flags & MMC_RSP_BUSY)) {
1413                WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_NOTBUSY);
1414                return;
1415        }
1416
1417        /*
1418         * If there is a data transfer with this command, then...
1419         * - If it's a read, we need to wait for ENDRX.
1420         * - If it's a write, now is the time to enable the PDC, and we need
1421         *   to wait for a BLKE that follows a TXBUFE, because if we're doing
1422         *   a split transfer we get a BLKE after the first half (when TPR/TCR
1423         *   get loaded from TNPR/TNCR).  So first we wait for the TXBUFE, and
1424         *   the handling for that interrupt will then invoke the wait for the
1425         *   subsequent BLKE which indicates actual completion.
1426         */
1427        if (cmd->data) {
1428                uint32_t ier;
1429#ifndef __rtems__
1430                if (cmd->data->flags & MMC_DATA_READ) {
1431                        ier = MCI_SR_ENDRX;
1432                } else {
1433                        ier = MCI_SR_TXBUFE;
1434                        WR4(sc, PDC_PTCR, PDC_PTCR_TXTEN);
1435                }
1436#else /* __rtems__ */
1437                ier = MCI_SR_XFRDONE;
1438#endif /* __rtems__ */
1439                WR4(sc, MCI_IER, MCI_SR_ERROR | ier);
1440                return;
1441        }
1442
1443        /*
1444         * If we made it to here, we don't need to wait for anything more for
1445         * the current command, move on to the next command (will complete the
1446         * request if there is no next command).
1447         */
1448        cmd->error = MMC_ERR_NONE;
1449        at91_mci_next_operation(sc);
1450}
1451
1452static void
1453at91_mci_intr(void *arg)
1454{
1455        struct at91_mci_softc *sc = (struct at91_mci_softc*)arg;
1456        struct mmc_command *cmd = sc->curcmd;
1457        uint32_t sr, isr;
1458
1459        AT91_MCI_LOCK(sc);
1460
1461        sr = RD4(sc, MCI_SR);
1462        isr = sr & RD4(sc, MCI_IMR);
1463
1464        if (mci_debug)
1465                printf("i 0x%x sr 0x%x\n", isr, sr);
1466
1467        /*
1468         * All interrupts are one-shot; disable it now.
1469         * The next operation will re-enable whatever interrupts it wants.
1470         */
1471        WR4(sc, MCI_IDR, isr);
1472        if (isr & MCI_SR_ERROR) {
1473                if (isr & (MCI_SR_RTOE | MCI_SR_DTOE))
1474                        cmd->error = MMC_ERR_TIMEOUT;
1475                else if (isr & (MCI_SR_RCRCE | MCI_SR_DCRCE))
1476                        cmd->error = MMC_ERR_BADCRC;
1477                else if (isr & (MCI_SR_OVRE | MCI_SR_UNRE))
1478                        cmd->error = MMC_ERR_FIFO;
1479                else
1480                        cmd->error = MMC_ERR_FAILED;
1481                /*
1482                 * CMD8 is used to probe for SDHC cards, a standard SD card
1483                 * will get a response timeout; don't report it because it's a
1484                 * normal and expected condition.  One might argue that all
1485                 * error reporting should be left to higher levels, but when
1486                 * they report at all it's always EIO, which isn't very
1487                 * helpful. XXX bootverbose?
1488                 */
1489                if (cmd->opcode != 8) {
1490                        device_printf(sc->dev,
1491                            "IO error; status MCI_SR = 0x%b cmd opcode = %d%s\n",
1492                            sr, MCI_SR_BITSTRING, cmd->opcode,
1493                            (cmd->opcode != 12) ? "" :
1494                            (sc->flags & CMD_MULTIREAD) ? " after read" : " after write");
1495                        /* XXX not sure RTOE needs a full reset, just a retry */
1496                        at91_mci_reset(sc);
1497                }
1498                at91_mci_next_operation(sc);
1499        } else {
1500#ifndef __rtems__
1501                if (isr & MCI_SR_TXBUFE) {
1502//                      printf("TXBUFE\n");
1503                        /*
1504                         * We need to wait for a BLKE that follows TXBUFE
1505                         * (intermediate BLKEs might happen after ENDTXes if
1506                         * we're chaining multiple buffers).  If BLKE is also
1507                         * asserted at the time we get TXBUFE, we can avoid
1508                         * another interrupt and process it right away, below.
1509                         */
1510                        if (sr & MCI_SR_BLKE)
1511                                isr |= MCI_SR_BLKE;
1512                        else
1513                                WR4(sc, MCI_IER, MCI_SR_BLKE);
1514                }
1515                if (isr & MCI_SR_RXBUFF) {
1516//                      printf("RXBUFF\n");
1517                }
1518                if (isr & MCI_SR_ENDTX) {
1519//                      printf("ENDTX\n");
1520                }
1521                if (isr & MCI_SR_ENDRX) {
1522//                      printf("ENDRX\n");
1523                        at91_mci_read_done(sc, sr);
1524                }
1525#else /* __rtems__ */
1526                if (isr & MCI_SR_XFRDONE) {
1527                        if (cmd->data->flags & MMC_DATA_READ) {
1528                                WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS |
1529                                    PDC_PTCR_TXTDIS);
1530                                cmd->error = MMC_ERR_NONE;
1531                                at91_mci_next_operation(sc);
1532                        } else {
1533                                if (sr & MCI_SR_BLKE)
1534                                        isr |= MCI_SR_BLKE;
1535                                else
1536                                        WR4(sc, MCI_IER, MCI_SR_BLKE);
1537                        }
1538                }
1539#endif /* __rtems__ */
1540                if (isr & MCI_SR_NOTBUSY) {
1541//                      printf("NOTBUSY\n");
1542                        at91_mci_notbusy(sc);
1543                }
1544                if (isr & MCI_SR_DTIP) {
1545//                      printf("Data transfer in progress\n");
1546                }
1547                if (isr & MCI_SR_BLKE) {
1548//                      printf("Block transfer end\n");
1549                        at91_mci_write_done(sc, sr);
1550                }
1551                if (isr & MCI_SR_TXRDY) {
1552//                      printf("Ready to transmit\n");
1553                }
1554                if (isr & MCI_SR_RXRDY) {
1555//                      printf("Ready to receive\n");
1556                }
1557                if (isr & MCI_SR_CMDRDY) {
1558//                      printf("Command ready\n");
1559                        at91_mci_cmdrdy(sc, sr);
1560                }
1561        }
1562        AT91_MCI_UNLOCK(sc);
1563}
1564
1565static int
1566at91_mci_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
1567{
1568        struct at91_mci_softc *sc = device_get_softc(bus);
1569
1570        switch (which) {
1571        default:
1572                return (EINVAL);
1573        case MMCBR_IVAR_BUS_MODE:
1574                *(int *)result = sc->host.ios.bus_mode;
1575                break;
1576        case MMCBR_IVAR_BUS_WIDTH:
1577                *(int *)result = sc->host.ios.bus_width;
1578                break;
1579        case MMCBR_IVAR_CHIP_SELECT:
1580                *(int *)result = sc->host.ios.chip_select;
1581                break;
1582        case MMCBR_IVAR_CLOCK:
1583                *(int *)result = sc->host.ios.clock;
1584                break;
1585        case MMCBR_IVAR_F_MIN:
1586                *(int *)result = sc->host.f_min;
1587                break;
1588        case MMCBR_IVAR_F_MAX:
1589                *(int *)result = sc->host.f_max;
1590                break;
1591        case MMCBR_IVAR_HOST_OCR:
1592                *(int *)result = sc->host.host_ocr;
1593                break;
1594        case MMCBR_IVAR_MODE:
1595                *(int *)result = sc->host.mode;
1596                break;
1597        case MMCBR_IVAR_OCR:
1598                *(int *)result = sc->host.ocr;
1599                break;
1600        case MMCBR_IVAR_POWER_MODE:
1601                *(int *)result = sc->host.ios.power_mode;
1602                break;
1603        case MMCBR_IVAR_VDD:
1604                *(int *)result = sc->host.ios.vdd;
1605                break;
1606        case MMCBR_IVAR_CAPS:
1607                if (sc->has_4wire) {
1608                        sc->sc_cap |= CAP_HAS_4WIRE;
1609                        sc->host.caps |= MMC_CAP_4_BIT_DATA;
1610                } else {
1611                        sc->sc_cap &= ~CAP_HAS_4WIRE;
1612                        sc->host.caps &= ~MMC_CAP_4_BIT_DATA;
1613                }
1614                *(int *)result = sc->host.caps;
1615                break;
1616#ifdef __rtems__
1617        case MMCBR_IVAR_TIMING:
1618                *result = sc->host.ios.timing;
1619                break;
1620#endif /* __rtems__ */
1621        case MMCBR_IVAR_MAX_DATA:
1622                /*
1623                 * Something is wrong with the 2x parts and multiblock, so
1624                 * just do 1 block at a time for now, which really kills
1625                 * performance.
1626                 */
1627                if (sc->sc_cap & CAP_MCI1_REV2XX)
1628                        *(int *)result = 1;
1629                else
1630                        *(int *)result = MAX_BLOCKS;
1631                break;
1632        }
1633        return (0);
1634}
1635
1636static int
1637at91_mci_write_ivar(device_t bus, device_t child, int which, uintptr_t value)
1638{
1639        struct at91_mci_softc *sc = device_get_softc(bus);
1640
1641        switch (which) {
1642        default:
1643                return (EINVAL);
1644        case MMCBR_IVAR_BUS_MODE:
1645                sc->host.ios.bus_mode = value;
1646                break;
1647        case MMCBR_IVAR_BUS_WIDTH:
1648                sc->host.ios.bus_width = value;
1649                break;
1650        case MMCBR_IVAR_CHIP_SELECT:
1651                sc->host.ios.chip_select = value;
1652                break;
1653        case MMCBR_IVAR_CLOCK:
1654                sc->host.ios.clock = value;
1655                break;
1656        case MMCBR_IVAR_MODE:
1657                sc->host.mode = value;
1658                break;
1659        case MMCBR_IVAR_OCR:
1660                sc->host.ocr = value;
1661                break;
1662        case MMCBR_IVAR_POWER_MODE:
1663                sc->host.ios.power_mode = value;
1664                break;
1665        case MMCBR_IVAR_VDD:
1666                sc->host.ios.vdd = value;
1667                break;
1668#ifdef __rtems__
1669        case MMCBR_IVAR_TIMING:
1670                sc->host.ios.timing = value;
1671                break;
1672#endif /* __rtems__ */
1673        /* These are read-only */
1674        case MMCBR_IVAR_CAPS:
1675        case MMCBR_IVAR_HOST_OCR:
1676        case MMCBR_IVAR_F_MIN:
1677        case MMCBR_IVAR_F_MAX:
1678        case MMCBR_IVAR_MAX_DATA:
1679                return (EINVAL);
1680        }
1681        return (0);
1682}
1683
1684static device_method_t at91_mci_methods[] = {
1685        /* device_if */
1686        DEVMETHOD(device_probe, at91_mci_probe),
1687        DEVMETHOD(device_attach, at91_mci_attach),
1688        DEVMETHOD(device_detach, at91_mci_detach),
1689
1690        /* Bus interface */
1691        DEVMETHOD(bus_read_ivar,        at91_mci_read_ivar),
1692        DEVMETHOD(bus_write_ivar,       at91_mci_write_ivar),
1693
1694        /* mmcbr_if */
1695        DEVMETHOD(mmcbr_update_ios, at91_mci_update_ios),
1696        DEVMETHOD(mmcbr_request, at91_mci_request),
1697        DEVMETHOD(mmcbr_get_ro, at91_mci_get_ro),
1698        DEVMETHOD(mmcbr_acquire_host, at91_mci_acquire_host),
1699        DEVMETHOD(mmcbr_release_host, at91_mci_release_host),
1700
1701        DEVMETHOD_END
1702};
1703
1704static driver_t at91_mci_driver = {
1705        "at91_mci",
1706        at91_mci_methods,
1707        sizeof(struct at91_mci_softc),
1708};
1709
1710static devclass_t at91_mci_devclass;
1711
1712#ifndef __rtems__
1713#ifdef FDT
1714DRIVER_MODULE(at91_mci, simplebus, at91_mci_driver, at91_mci_devclass, NULL,
1715    NULL);
1716#else
1717DRIVER_MODULE(at91_mci, atmelarm, at91_mci_driver, at91_mci_devclass, NULL,
1718    NULL);
1719#endif
1720
1721MMC_DECLARE_BRIDGE(at91_mci);
1722#else /* __rtems__ */
1723DRIVER_MODULE(at91_mci, nexus, at91_mci_driver, at91_mci_devclass, NULL, NULL);
1724#endif /* __rtems__ */
1725DRIVER_MODULE(mmc, at91_mci, mmc_driver, mmc_devclass, NULL, NULL);
1726MODULE_DEPEND(at91_mci, mmc, 1, 1, 1);
1727#endif /* __rtems__ && LIBBSP_ARM_ATSAM_BSP_H */
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