| 1 | /*- |
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| 2 | * Copyright (c) 1991 The Regents of the University of California. |
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| 3 | * All rights reserved. |
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| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * 1. Redistributions of source code must retain the above copyright |
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| 9 | * notice, this list of conditions and the following disclaimer. |
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| 10 | * 2. Redistributions in binary form must reproduce the above copyright |
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| 11 | * notice, this list of conditions and the following disclaimer in the |
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| 12 | * documentation and/or other materials provided with the distribution. |
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| 13 | * 4. Neither the name of the University nor the names of its contributors |
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| 14 | * may be used to endorse or promote products derived from this software |
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| 15 | * without specific prior written permission. |
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| 16 | * |
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND |
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| 18 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 19 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE |
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| 21 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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| 22 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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| 23 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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| 24 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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| 25 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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| 26 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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| 27 | * SUCH DAMAGE. |
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| 28 | * |
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| 29 | * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 |
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| 30 | * $FreeBSD$ |
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| 31 | */ |
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| 32 | |
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| 33 | #ifndef _MACHINE_SPECIALREG_HH_ |
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| 34 | #define _MACHINE_SPECIALREG_HH_ |
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| 35 | |
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| 36 | /* |
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| 37 | * Bits in 386 special registers: |
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| 38 | */ |
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| 39 | #define CR0_PE 0x00000001 /* Protected mode Enable */ |
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| 40 | #define CR0_MP 0x00000002 /* "Math" (fpu) Present */ |
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| 41 | #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ |
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| 42 | #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ |
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| 43 | #define CR0_PG 0x80000000 /* PaGing enable */ |
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| 44 | |
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| 45 | /* |
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| 46 | * Bits in 486 special registers: |
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| 47 | */ |
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| 48 | #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ |
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| 49 | #define CR0_WP 0x00010000 /* Write Protect (honor page protect in |
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| 50 | all modes) */ |
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| 51 | #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ |
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| 52 | #define CR0_NW 0x20000000 /* Not Write-through */ |
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| 53 | #define CR0_CD 0x40000000 /* Cache Disable */ |
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| 54 | |
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| 55 | /* |
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| 56 | * Bits in PPro special registers |
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| 57 | */ |
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| 58 | #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ |
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| 59 | #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ |
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| 60 | #define CR4_TSD 0x00000004 /* Time stamp disable */ |
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| 61 | #define CR4_DE 0x00000008 /* Debugging extensions */ |
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| 62 | #define CR4_PSE 0x00000010 /* Page size extensions */ |
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| 63 | #define CR4_PAE 0x00000020 /* Physical address extension */ |
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| 64 | #define CR4_MCE 0x00000040 /* Machine check enable */ |
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| 65 | #define CR4_PGE 0x00000080 /* Page global enable */ |
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| 66 | #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ |
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| 67 | #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ |
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| 68 | #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ |
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| 69 | |
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| 70 | /* |
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| 71 | * Bits in AMD64 special registers. EFER is 64 bits wide. |
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| 72 | */ |
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| 73 | #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ |
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| 74 | |
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| 75 | /* |
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| 76 | * CPUID instruction features register |
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| 77 | */ |
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| 78 | #define CPUID_FPU 0x00000001 |
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| 79 | #define CPUID_VME 0x00000002 |
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| 80 | #define CPUID_DE 0x00000004 |
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| 81 | #define CPUID_PSE 0x00000008 |
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| 82 | #define CPUID_TSC 0x00000010 |
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| 83 | #define CPUID_MSR 0x00000020 |
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| 84 | #define CPUID_PAE 0x00000040 |
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| 85 | #define CPUID_MCE 0x00000080 |
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| 86 | #define CPUID_CX8 0x00000100 |
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| 87 | #define CPUID_APIC 0x00000200 |
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| 88 | #define CPUID_B10 0x00000400 |
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| 89 | #define CPUID_SEP 0x00000800 |
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| 90 | #define CPUID_MTRR 0x00001000 |
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| 91 | #define CPUID_PGE 0x00002000 |
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| 92 | #define CPUID_MCA 0x00004000 |
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| 93 | #define CPUID_CMOV 0x00008000 |
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| 94 | #define CPUID_PAT 0x00010000 |
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| 95 | #define CPUID_PSE36 0x00020000 |
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| 96 | #define CPUID_PSN 0x00040000 |
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| 97 | #define CPUID_CLFSH 0x00080000 |
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| 98 | #define CPUID_B20 0x00100000 |
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| 99 | #define CPUID_DS 0x00200000 |
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| 100 | #define CPUID_ACPI 0x00400000 |
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| 101 | #define CPUID_MMX 0x00800000 |
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| 102 | #define CPUID_FXSR 0x01000000 |
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| 103 | #define CPUID_SSE 0x02000000 |
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| 104 | #define CPUID_XMM 0x02000000 |
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| 105 | #define CPUID_SSE2 0x04000000 |
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| 106 | #define CPUID_SS 0x08000000 |
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| 107 | #define CPUID_HTT 0x10000000 |
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| 108 | #define CPUID_TM 0x20000000 |
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| 109 | #define CPUID_IA64 0x40000000 |
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| 110 | #define CPUID_PBE 0x80000000 |
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| 111 | |
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| 112 | #define CPUID2_SSE3 0x00000001 |
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| 113 | #define CPUID2_PCLMULQDQ 0x00000002 |
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| 114 | #define CPUID2_DTES64 0x00000004 |
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| 115 | #define CPUID2_MON 0x00000008 |
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| 116 | #define CPUID2_DS_CPL 0x00000010 |
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| 117 | #define CPUID2_VMX 0x00000020 |
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| 118 | #define CPUID2_SMX 0x00000040 |
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| 119 | #define CPUID2_EST 0x00000080 |
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| 120 | #define CPUID2_TM2 0x00000100 |
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| 121 | #define CPUID2_SSSE3 0x00000200 |
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| 122 | #define CPUID2_CNXTID 0x00000400 |
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| 123 | #define CPUID2_CX16 0x00002000 |
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| 124 | #define CPUID2_XTPR 0x00004000 |
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| 125 | #define CPUID2_PDCM 0x00008000 |
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| 126 | #define CPUID2_PCID 0x00020000 |
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| 127 | #define CPUID2_DCA 0x00040000 |
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| 128 | #define CPUID2_SSE41 0x00080000 |
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| 129 | #define CPUID2_SSE42 0x00100000 |
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| 130 | #define CPUID2_X2APIC 0x00200000 |
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| 131 | #define CPUID2_MOVBE 0x00400000 |
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| 132 | #define CPUID2_POPCNT 0x00800000 |
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| 133 | #define CPUID2_AESNI 0x02000000 |
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| 134 | |
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| 135 | /* |
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| 136 | * Important bits in the AMD extended cpuid flags |
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| 137 | */ |
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| 138 | #define AMDID_SYSCALL 0x00000800 |
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| 139 | #define AMDID_MP 0x00080000 |
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| 140 | #define AMDID_NX 0x00100000 |
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| 141 | #define AMDID_EXT_MMX 0x00400000 |
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| 142 | #define AMDID_FFXSR 0x01000000 |
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| 143 | #define AMDID_PAGE1GB 0x04000000 |
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| 144 | #define AMDID_RDTSCP 0x08000000 |
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| 145 | #define AMDID_LM 0x20000000 |
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| 146 | #define AMDID_EXT_3DNOW 0x40000000 |
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| 147 | #define AMDID_3DNOW 0x80000000 |
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| 148 | |
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| 149 | #define AMDID2_LAHF 0x00000001 |
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| 150 | #define AMDID2_CMP 0x00000002 |
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| 151 | #define AMDID2_SVM 0x00000004 |
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| 152 | #define AMDID2_EXT_APIC 0x00000008 |
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| 153 | #define AMDID2_CR8 0x00000010 |
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| 154 | #define AMDID2_ABM 0x00000020 |
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| 155 | #define AMDID2_SSE4A 0x00000040 |
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| 156 | #define AMDID2_MAS 0x00000080 |
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| 157 | #define AMDID2_PREFETCH 0x00000100 |
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| 158 | #define AMDID2_OSVW 0x00000200 |
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| 159 | #define AMDID2_IBS 0x00000400 |
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| 160 | #define AMDID2_SSE5 0x00000800 |
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| 161 | #define AMDID2_SKINIT 0x00001000 |
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| 162 | #define AMDID2_WDT 0x00002000 |
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| 163 | |
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| 164 | /* |
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| 165 | * CPUID instruction 1 eax info |
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| 166 | */ |
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| 167 | #define CPUID_STEPPING 0x0000000f |
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| 168 | #define CPUID_MODEL 0x000000f0 |
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| 169 | #define CPUID_FAMILY 0x00000f00 |
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| 170 | #define CPUID_EXT_MODEL 0x000f0000 |
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| 171 | #define CPUID_EXT_FAMILY 0x0ff00000 |
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| 172 | #define CPUID_TO_MODEL(id) \ |
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| 173 | ((((id) & CPUID_MODEL) >> 4) | \ |
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| 174 | ((((id) & CPUID_FAMILY) >= 0x600) ? \ |
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| 175 | (((id) & CPUID_EXT_MODEL) >> 12) : 0)) |
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| 176 | #define CPUID_TO_FAMILY(id) \ |
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| 177 | ((((id) & CPUID_FAMILY) >> 8) + \ |
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| 178 | ((((id) & CPUID_FAMILY) == 0xf00) ? \ |
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| 179 | (((id) & CPUID_EXT_FAMILY) >> 20) : 0)) |
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| 180 | |
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| 181 | /* |
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| 182 | * CPUID instruction 1 ebx info |
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| 183 | */ |
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| 184 | #define CPUID_BRAND_INDEX 0x000000ff |
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| 185 | #define CPUID_CLFUSH_SIZE 0x0000ff00 |
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| 186 | #define CPUID_HTT_CORES 0x00ff0000 |
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| 187 | #define CPUID_LOCAL_APIC_ID 0xff000000 |
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| 188 | |
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| 189 | /* |
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| 190 | * CPUID instruction 0xb ebx info. |
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| 191 | */ |
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| 192 | #define CPUID_TYPE_INVAL 0 |
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| 193 | #define CPUID_TYPE_SMT 1 |
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| 194 | #define CPUID_TYPE_CORE 2 |
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| 195 | |
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| 196 | /* |
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| 197 | * AMD extended function 8000_0007h edx info |
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| 198 | */ |
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| 199 | #define AMDPM_TS 0x00000001 |
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| 200 | #define AMDPM_FID 0x00000002 |
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| 201 | #define AMDPM_VID 0x00000004 |
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| 202 | #define AMDPM_TTP 0x00000008 |
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| 203 | #define AMDPM_TM 0x00000010 |
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| 204 | #define AMDPM_STC 0x00000020 |
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| 205 | #define AMDPM_100MHZ_STEPS 0x00000040 |
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| 206 | #define AMDPM_HW_PSTATE 0x00000080 |
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| 207 | #define AMDPM_TSC_INVARIANT 0x00000100 |
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| 208 | |
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| 209 | /* |
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| 210 | * AMD extended function 8000_0008h ecx info |
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| 211 | */ |
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| 212 | #define AMDID_CMP_CORES 0x000000ff |
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| 213 | |
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| 214 | /* |
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| 215 | * CPUID manufacturers identifiers |
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| 216 | */ |
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| 217 | #define AMD_VENDOR_ID "AuthenticAMD" |
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| 218 | #define CENTAUR_VENDOR_ID "CentaurHauls" |
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| 219 | #define CYRIX_VENDOR_ID "CyrixInstead" |
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| 220 | #define INTEL_VENDOR_ID "GenuineIntel" |
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| 221 | #define NEXGEN_VENDOR_ID "NexGenDriven" |
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| 222 | #define NSC_VENDOR_ID "Geode by NSC" |
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| 223 | #define RISE_VENDOR_ID "RiseRiseRise" |
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| 224 | #define SIS_VENDOR_ID "SiS SiS SiS " |
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| 225 | #define TRANSMETA_VENDOR_ID "GenuineTMx86" |
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| 226 | #define UMC_VENDOR_ID "UMC UMC UMC " |
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| 227 | |
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| 228 | /* |
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| 229 | * Model-specific registers for the i386 family |
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| 230 | */ |
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| 231 | #define MSR_P5_MC_ADDR 0x000 |
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| 232 | #define MSR_P5_MC_TYPE 0x001 |
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| 233 | #define MSR_TSC 0x010 |
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| 234 | #define MSR_P5_CESR 0x011 |
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| 235 | #define MSR_P5_CTR0 0x012 |
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| 236 | #define MSR_P5_CTR1 0x013 |
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| 237 | #define MSR_IA32_PLATFORM_ID 0x017 |
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| 238 | #define MSR_APICBASE 0x01b |
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| 239 | #define MSR_EBL_CR_POWERON 0x02a |
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| 240 | #define MSR_TEST_CTL 0x033 |
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| 241 | #define MSR_BIOS_UPDT_TRIG 0x079 |
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| 242 | #define MSR_BBL_CR_D0 0x088 |
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| 243 | #define MSR_BBL_CR_D1 0x089 |
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| 244 | #define MSR_BBL_CR_D2 0x08a |
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| 245 | #define MSR_BIOS_SIGN 0x08b |
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| 246 | #define MSR_PERFCTR0 0x0c1 |
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| 247 | #define MSR_PERFCTR1 0x0c2 |
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| 248 | #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ |
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| 249 | #define MSR_MTRRcap 0x0fe |
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| 250 | #define MSR_BBL_CR_ADDR 0x116 |
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| 251 | #define MSR_BBL_CR_DECC 0x118 |
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| 252 | #define MSR_BBL_CR_CTL 0x119 |
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| 253 | #define MSR_BBL_CR_TRIG 0x11a |
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| 254 | #define MSR_BBL_CR_BUSY 0x11b |
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| 255 | #define MSR_BBL_CR_CTL3 0x11e |
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| 256 | #define MSR_SYSENTER_CS_MSR 0x174 |
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| 257 | #define MSR_SYSENTER_ESP_MSR 0x175 |
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| 258 | #define MSR_SYSENTER_EIP_MSR 0x176 |
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| 259 | #define MSR_MCG_CAP 0x179 |
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| 260 | #define MSR_MCG_STATUS 0x17a |
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| 261 | #define MSR_MCG_CTL 0x17b |
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| 262 | #define MSR_EVNTSEL0 0x186 |
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| 263 | #define MSR_EVNTSEL1 0x187 |
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| 264 | #define MSR_THERM_CONTROL 0x19a |
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| 265 | #define MSR_THERM_INTERRUPT 0x19b |
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| 266 | #define MSR_THERM_STATUS 0x19c |
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| 267 | #define MSR_IA32_MISC_ENABLE 0x1a0 |
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| 268 | #define MSR_IA32_TEMPERATURE_TARGET 0x1a2 |
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| 269 | #define MSR_DEBUGCTLMSR 0x1d9 |
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| 270 | #define MSR_LASTBRANCHFROMIP 0x1db |
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| 271 | #define MSR_LASTBRANCHTOIP 0x1dc |
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| 272 | #define MSR_LASTINTFROMIP 0x1dd |
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| 273 | #define MSR_LASTINTTOIP 0x1de |
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| 274 | #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 |
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| 275 | #define MSR_MTRRVarBase 0x200 |
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| 276 | #define MSR_MTRR64kBase 0x250 |
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| 277 | #define MSR_MTRR16kBase 0x258 |
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| 278 | #define MSR_MTRR4kBase 0x268 |
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| 279 | #define MSR_PAT 0x277 |
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| 280 | #define MSR_MC0_CTL2 0x280 |
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| 281 | #define MSR_MTRRdefType 0x2ff |
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| 282 | #define MSR_MC0_CTL 0x400 |
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| 283 | #define MSR_MC0_STATUS 0x401 |
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| 284 | #define MSR_MC0_ADDR 0x402 |
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| 285 | #define MSR_MC0_MISC 0x403 |
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| 286 | #define MSR_MC1_CTL 0x404 |
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| 287 | #define MSR_MC1_STATUS 0x405 |
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| 288 | #define MSR_MC1_ADDR 0x406 |
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| 289 | #define MSR_MC1_MISC 0x407 |
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| 290 | #define MSR_MC2_CTL 0x408 |
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| 291 | #define MSR_MC2_STATUS 0x409 |
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| 292 | #define MSR_MC2_ADDR 0x40a |
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| 293 | #define MSR_MC2_MISC 0x40b |
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| 294 | #define MSR_MC3_CTL 0x40c |
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| 295 | #define MSR_MC3_STATUS 0x40d |
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| 296 | #define MSR_MC3_ADDR 0x40e |
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| 297 | #define MSR_MC3_MISC 0x40f |
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| 298 | #define MSR_MC4_CTL 0x410 |
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| 299 | #define MSR_MC4_STATUS 0x411 |
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| 300 | #define MSR_MC4_ADDR 0x412 |
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| 301 | #define MSR_MC4_MISC 0x413 |
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| 302 | |
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| 303 | /* |
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| 304 | * Constants related to MSR's. |
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| 305 | */ |
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| 306 | #define APICBASE_RESERVED 0x000006ff |
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| 307 | #define APICBASE_BSP 0x00000100 |
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| 308 | #define APICBASE_ENABLED 0x00000800 |
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| 309 | #define APICBASE_ADDRESS 0xfffff000 |
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| 310 | |
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| 311 | /* |
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| 312 | * PAT modes. |
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| 313 | */ |
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| 314 | #define PAT_UNCACHEABLE 0x00 |
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| 315 | #define PAT_WRITE_COMBINING 0x01 |
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| 316 | #define PAT_WRITE_THROUGH 0x04 |
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| 317 | #define PAT_WRITE_PROTECTED 0x05 |
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| 318 | #define PAT_WRITE_BACK 0x06 |
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| 319 | #define PAT_UNCACHED 0x07 |
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| 320 | #define PAT_VALUE(i, m) ((long long)(m) << (8 * (i))) |
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| 321 | #define PAT_MASK(i) PAT_VALUE(i, 0xff) |
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| 322 | |
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| 323 | /* |
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| 324 | * Constants related to MTRRs |
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| 325 | */ |
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| 326 | #define MTRR_UNCACHEABLE 0x00 |
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| 327 | #define MTRR_WRITE_COMBINING 0x01 |
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| 328 | #define MTRR_WRITE_THROUGH 0x04 |
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| 329 | #define MTRR_WRITE_PROTECTED 0x05 |
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| 330 | #define MTRR_WRITE_BACK 0x06 |
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| 331 | #define MTRR_N64K 8 /* numbers of fixed-size entries */ |
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| 332 | #define MTRR_N16K 16 |
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| 333 | #define MTRR_N4K 64 |
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| 334 | #define MTRR_CAP_WC 0x0000000000000400 |
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| 335 | #define MTRR_CAP_FIXED 0x0000000000000100 |
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| 336 | #define MTRR_CAP_VCNT 0x00000000000000ff |
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| 337 | #define MTRR_DEF_ENABLE 0x0000000000000800 |
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| 338 | #define MTRR_DEF_FIXED_ENABLE 0x0000000000000400 |
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| 339 | #define MTRR_DEF_TYPE 0x00000000000000ff |
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| 340 | #define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000 |
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| 341 | #define MTRR_PHYSBASE_TYPE 0x00000000000000ff |
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| 342 | #define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000 |
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| 343 | #define MTRR_PHYSMASK_VALID 0x0000000000000800 |
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| 344 | |
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| 345 | /* |
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| 346 | * Cyrix configuration registers, accessible as IO ports. |
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| 347 | */ |
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| 348 | #define CCR0 0xc0 /* Configuration control register 0 */ |
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| 349 | #define CCR0_NC0 0x01 /* First 64K of each 1M memory region is |
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| 350 | non-cacheable */ |
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| 351 | #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ |
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| 352 | #define CCR0_A20M 0x04 /* Enables A20M# input pin */ |
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| 353 | #define CCR0_KEN 0x08 /* Enables KEN# input pin */ |
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| 354 | #define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */ |
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| 355 | #define CCR0_BARB 0x20 /* Flushes internal cache when entering hold |
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| 356 | state */ |
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| 357 | #define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set |
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| 358 | assoc */ |
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| 359 | #define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */ |
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| 360 | |
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| 361 | #define CCR1 0xc1 /* Configuration control register 1 */ |
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| 362 | #define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */ |
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| 363 | #define CCR1_SMI 0x02 /* Enables SMM pins */ |
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| 364 | #define CCR1_SMAC 0x04 /* System management memory access */ |
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| 365 | #define CCR1_MMAC 0x08 /* Main memory access */ |
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| 366 | #define CCR1_NO_LOCK 0x10 /* Negate LOCK# */ |
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| 367 | #define CCR1_SM3 0x80 /* SMM address space address region 3 */ |
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| 368 | |
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| 369 | #define CCR2 0xc2 |
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| 370 | #define CCR2_WB 0x02 /* Enables WB cache interface pins */ |
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| 371 | #define CCR2_SADS 0x02 /* Slow ADS */ |
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| 372 | #define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */ |
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| 373 | #define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */ |
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| 374 | #define CCR2_WT1 0x10 /* WT region 1 */ |
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| 375 | #define CCR2_WPR1 0x10 /* Write-protect region 1 */ |
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| 376 | #define CCR2_BARB 0x20 /* Flushes write-back cache when entering |
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| 377 | hold state. */ |
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| 378 | #define CCR2_BWRT 0x40 /* Enables burst write cycles */ |
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| 379 | #define CCR2_USE_SUSP 0x80 /* Enables suspend pins */ |
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| 380 | |
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| 381 | #define CCR3 0xc3 |
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| 382 | #define CCR3_SMILOCK 0x01 /* SMM register lock */ |
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| 383 | #define CCR3_NMI 0x02 /* Enables NMI during SMM */ |
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| 384 | #define CCR3_LINBRST 0x04 /* Linear address burst cycles */ |
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| 385 | #define CCR3_SMMMODE 0x08 /* SMM Mode */ |
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| 386 | #define CCR3_MAPEN0 0x10 /* Enables Map0 */ |
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| 387 | #define CCR3_MAPEN1 0x20 /* Enables Map1 */ |
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| 388 | #define CCR3_MAPEN2 0x40 /* Enables Map2 */ |
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| 389 | #define CCR3_MAPEN3 0x80 /* Enables Map3 */ |
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| 390 | |
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| 391 | #define CCR4 0xe8 |
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| 392 | #define CCR4_IOMASK 0x07 |
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| 393 | #define CCR4_MEM 0x08 /* Enables momory bypassing */ |
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| 394 | #define CCR4_DTE 0x10 /* Enables directory table entry cache */ |
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| 395 | #define CCR4_FASTFPE 0x20 /* Fast FPU exception */ |
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| 396 | #define CCR4_CPUID 0x80 /* Enables CPUID instruction */ |
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| 397 | |
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| 398 | #define CCR5 0xe9 |
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| 399 | #define CCR5_WT_ALLOC 0x01 /* Write-through allocate */ |
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| 400 | #define CCR5_SLOP 0x02 /* LOOP instruction slowed down */ |
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| 401 | #define CCR5_LBR1 0x10 /* Local bus region 1 */ |
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| 402 | #define CCR5_ARREN 0x20 /* Enables ARR region */ |
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| 403 | |
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| 404 | #define CCR6 0xea |
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| 405 | |
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| 406 | #define CCR7 0xeb |
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| 407 | |
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| 408 | /* Performance Control Register (5x86 only). */ |
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| 409 | #define PCR0 0x20 |
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| 410 | #define PCR0_RSTK 0x01 /* Enables return stack */ |
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| 411 | #define PCR0_BTB 0x02 /* Enables branch target buffer */ |
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| 412 | #define PCR0_LOOP 0x04 /* Enables loop */ |
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| 413 | #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to |
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| 414 | serialize pipe. */ |
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| 415 | #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ |
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| 416 | #define PCR0_BTBRT 0x40 /* Enables BTB test register. */ |
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| 417 | #define PCR0_LSSER 0x80 /* Disable reorder */ |
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| 418 | |
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| 419 | /* Device Identification Registers */ |
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| 420 | #define DIR0 0xfe |
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| 421 | #define DIR1 0xff |
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| 422 | |
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| 423 | /* |
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| 424 | * Machine Check register constants. |
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| 425 | */ |
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| 426 | #define MCG_CAP_COUNT 0x000000ff |
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| 427 | #define MCG_CAP_CTL_P 0x00000100 |
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| 428 | #define MCG_CAP_EXT_P 0x00000200 |
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| 429 | #define MCG_CAP_CMCI_P 0x00000400 |
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| 430 | #define MCG_CAP_TES_P 0x00000800 |
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| 431 | #define MCG_CAP_EXT_CNT 0x00ff0000 |
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| 432 | #define MCG_CAP_SER_P 0x01000000 |
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| 433 | #define MCG_STATUS_RIPV 0x00000001 |
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| 434 | #define MCG_STATUS_EIPV 0x00000002 |
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| 435 | #define MCG_STATUS_MCIP 0x00000004 |
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| 436 | #define MCG_CTL_ENABLE 0xffffffffffffffff |
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| 437 | #define MCG_CTL_DISABLE 0x0000000000000000 |
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| 438 | #define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4) |
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| 439 | #define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4) |
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| 440 | #define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4) |
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| 441 | #define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4) |
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| 442 | #define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */ |
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| 443 | #define MC_STATUS_MCA_ERROR 0x000000000000ffff |
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| 444 | #define MC_STATUS_MODEL_ERROR 0x00000000ffff0000 |
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| 445 | #define MC_STATUS_OTHER_INFO 0x01ffffff00000000 |
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| 446 | #define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_CMCI_P */ |
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| 447 | #define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */ |
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| 448 | #define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_TES_P */ |
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| 449 | #define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_TES_P */ |
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| 450 | #define MC_STATUS_PCC 0x0200000000000000 |
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| 451 | #define MC_STATUS_ADDRV 0x0400000000000000 |
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| 452 | #define MC_STATUS_MISCV 0x0800000000000000 |
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| 453 | #define MC_STATUS_EN 0x1000000000000000 |
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| 454 | #define MC_STATUS_UC 0x2000000000000000 |
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| 455 | #define MC_STATUS_OVER 0x4000000000000000 |
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| 456 | #define MC_STATUS_VAL 0x8000000000000000 |
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| 457 | #define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */ |
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| 458 | #define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */ |
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| 459 | #define MC_CTL2_THRESHOLD 0x0000000000007fff |
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| 460 | #define MC_CTL2_CMCI_EN 0x0000000040000000 |
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| 461 | |
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| 462 | /* |
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| 463 | * The following four 3-byte registers control the non-cacheable regions. |
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| 464 | * These registers must be written as three separate bytes. |
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| 465 | * |
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| 466 | * NCRx+0: A31-A24 of starting address |
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| 467 | * NCRx+1: A23-A16 of starting address |
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| 468 | * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. |
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| 469 | * |
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| 470 | * The non-cacheable region's starting address must be aligned to the |
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| 471 | * size indicated by the NCR_SIZE_xx field. |
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| 472 | */ |
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| 473 | #define NCR1 0xc4 |
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| 474 | #define NCR2 0xc7 |
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| 475 | #define NCR3 0xca |
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| 476 | #define NCR4 0xcd |
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| 477 | |
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| 478 | #define NCR_SIZE_0K 0 |
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| 479 | #define NCR_SIZE_4K 1 |
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| 480 | #define NCR_SIZE_8K 2 |
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| 481 | #define NCR_SIZE_16K 3 |
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| 482 | #define NCR_SIZE_32K 4 |
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| 483 | #define NCR_SIZE_64K 5 |
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| 484 | #define NCR_SIZE_128K 6 |
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| 485 | #define NCR_SIZE_256K 7 |
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| 486 | #define NCR_SIZE_512K 8 |
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| 487 | #define NCR_SIZE_1M 9 |
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| 488 | #define NCR_SIZE_2M 10 |
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| 489 | #define NCR_SIZE_4M 11 |
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| 490 | #define NCR_SIZE_8M 12 |
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| 491 | #define NCR_SIZE_16M 13 |
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| 492 | #define NCR_SIZE_32M 14 |
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| 493 | #define NCR_SIZE_4G 15 |
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| 494 | |
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| 495 | /* |
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| 496 | * The address region registers are used to specify the location and |
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| 497 | * size for the eight address regions. |
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| 498 | * |
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| 499 | * ARRx + 0: A31-A24 of start address |
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| 500 | * ARRx + 1: A23-A16 of start address |
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| 501 | * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx |
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| 502 | */ |
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| 503 | #define ARR0 0xc4 |
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| 504 | #define ARR1 0xc7 |
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| 505 | #define ARR2 0xca |
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| 506 | #define ARR3 0xcd |
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| 507 | #define ARR4 0xd0 |
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| 508 | #define ARR5 0xd3 |
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| 509 | #define ARR6 0xd6 |
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| 510 | #define ARR7 0xd9 |
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| 511 | |
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| 512 | #define ARR_SIZE_0K 0 |
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| 513 | #define ARR_SIZE_4K 1 |
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| 514 | #define ARR_SIZE_8K 2 |
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| 515 | #define ARR_SIZE_16K 3 |
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| 516 | #define ARR_SIZE_32K 4 |
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| 517 | #define ARR_SIZE_64K 5 |
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| 518 | #define ARR_SIZE_128K 6 |
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| 519 | #define ARR_SIZE_256K 7 |
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| 520 | #define ARR_SIZE_512K 8 |
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| 521 | #define ARR_SIZE_1M 9 |
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| 522 | #define ARR_SIZE_2M 10 |
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| 523 | #define ARR_SIZE_4M 11 |
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| 524 | #define ARR_SIZE_8M 12 |
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| 525 | #define ARR_SIZE_16M 13 |
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| 526 | #define ARR_SIZE_32M 14 |
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| 527 | #define ARR_SIZE_4G 15 |
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| 528 | |
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| 529 | /* |
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| 530 | * The region control registers specify the attributes associated with |
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| 531 | * the ARRx addres regions. |
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| 532 | */ |
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| 533 | #define RCR0 0xdc |
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| 534 | #define RCR1 0xdd |
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| 535 | #define RCR2 0xde |
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| 536 | #define RCR3 0xdf |
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| 537 | #define RCR4 0xe0 |
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| 538 | #define RCR5 0xe1 |
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| 539 | #define RCR6 0xe2 |
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| 540 | #define RCR7 0xe3 |
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| 541 | |
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| 542 | #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ |
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| 543 | #define RCR_RCE 0x01 /* Enables caching for ARR7. */ |
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| 544 | #define RCR_WWO 0x02 /* Weak write ordering. */ |
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| 545 | #define RCR_WL 0x04 /* Weak locking. */ |
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| 546 | #define RCR_WG 0x08 /* Write gathering. */ |
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| 547 | #define RCR_WT 0x10 /* Write-through. */ |
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| 548 | #define RCR_NLB 0x20 /* LBA# pin is not asserted. */ |
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| 549 | |
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| 550 | /* AMD Write Allocate Top-Of-Memory and Control Register */ |
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| 551 | #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ |
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| 552 | #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ |
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| 553 | #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ |
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| 554 | |
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| 555 | /* AMD64 MSR's */ |
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| 556 | #define MSR_EFER 0xc0000080 /* extended features */ |
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| 557 | #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ |
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| 558 | #define MSR_MC0_CTL_MASK 0xc0010044 |
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| 559 | |
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| 560 | /* VIA ACE crypto featureset: for via_feature_rng */ |
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| 561 | #define VIA_HAS_RNG 1 /* cpu has RNG */ |
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| 562 | |
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| 563 | /* VIA ACE crypto featureset: for via_feature_xcrypt */ |
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| 564 | #define VIA_HAS_AES 1 /* cpu has AES */ |
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| 565 | #define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ |
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| 566 | #define VIA_HAS_MM 4 /* cpu has RSA instructions */ |
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| 567 | #define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ |
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| 568 | |
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| 569 | /* Centaur Extended Feature flags */ |
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| 570 | #define VIA_CPUID_HAS_RNG 0x000004 |
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| 571 | #define VIA_CPUID_DO_RNG 0x000008 |
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| 572 | #define VIA_CPUID_HAS_ACE 0x000040 |
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| 573 | #define VIA_CPUID_DO_ACE 0x000080 |
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| 574 | #define VIA_CPUID_HAS_ACE2 0x000100 |
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| 575 | #define VIA_CPUID_DO_ACE2 0x000200 |
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| 576 | #define VIA_CPUID_HAS_PHE 0x000400 |
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| 577 | #define VIA_CPUID_DO_PHE 0x000800 |
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| 578 | #define VIA_CPUID_HAS_PMM 0x001000 |
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| 579 | #define VIA_CPUID_DO_PMM 0x002000 |
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| 580 | |
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| 581 | /* VIA ACE xcrypt-* instruction context control options */ |
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| 582 | #define VIA_CRYPT_CWLO_ROUND_M 0x0000000f |
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| 583 | #define VIA_CRYPT_CWLO_ALG_M 0x00000070 |
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| 584 | #define VIA_CRYPT_CWLO_ALG_AES 0x00000000 |
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| 585 | #define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080 |
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| 586 | #define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000 |
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| 587 | #define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080 |
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| 588 | #define VIA_CRYPT_CWLO_NORMAL 0x00000000 |
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| 589 | #define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100 |
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| 590 | #define VIA_CRYPT_CWLO_ENCRYPT 0x00000000 |
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| 591 | #define VIA_CRYPT_CWLO_DECRYPT 0x00000200 |
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| 592 | #define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ |
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| 593 | #define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ |
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| 594 | #define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ |
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| 595 | |
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| 596 | #endif /* !_MACHINE_SPECIALREG_HH_ */ |
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