1 | #include <freebsd/machine/rtems-bsd-config.h> |
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2 | |
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3 | /*- |
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4 | * Copyright (c) 2008 Benno Rice. All rights reserved. |
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5 | * |
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6 | * Redistribution and use in source and binary forms, with or without |
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7 | * modification, are permitted provided that the following conditions |
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8 | * are met: |
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9 | * 1. Redistributions of source code must retain the above copyright |
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10 | * notice, this list of conditions and the following disclaimer. |
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11 | * 2. Redistributions in binary form must reproduce the above copyright |
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12 | * notice, this list of conditions and the following disclaimer in the |
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13 | * documentation and/or other materials provided with the distribution. |
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14 | * |
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15 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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16 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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17 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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18 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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19 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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20 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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21 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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22 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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23 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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24 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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25 | */ |
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26 | |
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27 | #include <freebsd/sys/cdefs.h> |
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28 | __FBSDID("$FreeBSD$"); |
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29 | |
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30 | /* |
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31 | * Driver for SMSC LAN91C111, may work for older variants. |
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32 | */ |
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33 | |
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34 | #ifdef HAVE_KERNEL_OPTION_HEADERS |
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35 | #include <freebsd/local/opt_device_polling.h> |
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36 | #endif |
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37 | |
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38 | #include <freebsd/sys/param.h> |
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39 | #include <freebsd/sys/systm.h> |
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40 | #include <freebsd/sys/errno.h> |
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41 | #include <freebsd/sys/kernel.h> |
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42 | #include <freebsd/sys/sockio.h> |
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43 | #include <freebsd/sys/malloc.h> |
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44 | #include <freebsd/sys/mbuf.h> |
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45 | #include <freebsd/sys/queue.h> |
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46 | #include <freebsd/sys/socket.h> |
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47 | #include <freebsd/sys/syslog.h> |
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48 | #include <freebsd/sys/taskqueue.h> |
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49 | |
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50 | #include <freebsd/sys/module.h> |
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51 | #include <freebsd/sys/bus.h> |
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52 | |
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53 | #include <freebsd/machine/bus.h> |
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54 | #include <freebsd/machine/resource.h> |
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55 | #include <freebsd/sys/rman.h> |
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56 | |
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57 | #include <freebsd/net/ethernet.h> |
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58 | #include <freebsd/net/if.h> |
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59 | #include <freebsd/net/if_arp.h> |
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60 | #include <freebsd/net/if_dl.h> |
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61 | #include <freebsd/net/if_types.h> |
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62 | #include <freebsd/net/if_mib.h> |
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63 | #include <freebsd/net/if_media.h> |
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64 | |
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65 | #ifdef INET |
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66 | #include <freebsd/netinet/in.h> |
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67 | #include <freebsd/netinet/in_systm.h> |
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68 | #include <freebsd/netinet/in_var.h> |
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69 | #include <freebsd/netinet/ip.h> |
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70 | #endif |
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71 | |
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72 | #include <freebsd/net/bpf.h> |
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73 | #include <freebsd/net/bpfdesc.h> |
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74 | |
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75 | #include <freebsd/dev/smc/if_smcreg.h> |
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76 | #include <freebsd/dev/smc/if_smcvar.h> |
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77 | |
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78 | #include <freebsd/dev/mii/mii.h> |
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79 | #include <freebsd/dev/mii/miivar.h> |
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80 | |
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81 | #define SMC_LOCK(sc) mtx_lock(&(sc)->smc_mtx) |
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82 | #define SMC_UNLOCK(sc) mtx_unlock(&(sc)->smc_mtx) |
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83 | #define SMC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->smc_mtx, MA_OWNED) |
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84 | |
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85 | #define SMC_INTR_PRIORITY 0 |
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86 | #define SMC_RX_PRIORITY 5 |
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87 | #define SMC_TX_PRIORITY 10 |
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88 | |
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89 | devclass_t smc_devclass; |
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90 | |
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91 | static const char *smc_chip_ids[16] = { |
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92 | NULL, NULL, NULL, |
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93 | /* 3 */ "SMSC LAN91C90 or LAN91C92", |
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94 | /* 4 */ "SMSC LAN91C94", |
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95 | /* 5 */ "SMSC LAN91C95", |
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96 | /* 6 */ "SMSC LAN91C96", |
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97 | /* 7 */ "SMSC LAN91C100", |
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98 | /* 8 */ "SMSC LAN91C100FD", |
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99 | /* 9 */ "SMSC LAN91C110FD or LAN91C111FD", |
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100 | NULL, NULL, NULL, |
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101 | NULL, NULL, NULL |
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102 | }; |
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103 | |
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104 | static void smc_init(void *); |
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105 | static void smc_start(struct ifnet *); |
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106 | static void smc_stop(struct smc_softc *); |
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107 | static int smc_ioctl(struct ifnet *, u_long, caddr_t); |
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108 | |
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109 | static void smc_init_locked(struct smc_softc *); |
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110 | static void smc_start_locked(struct ifnet *); |
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111 | static void smc_reset(struct smc_softc *); |
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112 | static int smc_mii_ifmedia_upd(struct ifnet *); |
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113 | static void smc_mii_ifmedia_sts(struct ifnet *, struct ifmediareq *); |
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114 | static void smc_mii_tick(void *); |
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115 | static void smc_mii_mediachg(struct smc_softc *); |
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116 | static int smc_mii_mediaioctl(struct smc_softc *, struct ifreq *, u_long); |
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117 | |
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118 | static void smc_task_intr(void *, int); |
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119 | static void smc_task_rx(void *, int); |
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120 | static void smc_task_tx(void *, int); |
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121 | |
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122 | static driver_filter_t smc_intr; |
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123 | static timeout_t smc_watchdog; |
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124 | #ifdef DEVICE_POLLING |
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125 | static poll_handler_t smc_poll; |
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126 | #endif |
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127 | |
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128 | static __inline void |
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129 | smc_select_bank(struct smc_softc *sc, uint16_t bank) |
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130 | { |
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131 | |
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132 | bus_write_2(sc->smc_reg, BSR, bank & BSR_BANK_MASK); |
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133 | } |
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134 | |
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135 | /* Never call this when not in bank 2. */ |
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136 | static __inline void |
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137 | smc_mmu_wait(struct smc_softc *sc) |
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138 | { |
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139 | |
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140 | KASSERT((bus_read_2(sc->smc_reg, BSR) & |
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141 | BSR_BANK_MASK) == 2, ("%s: smc_mmu_wait called when not in bank 2", |
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142 | device_get_nameunit(sc->smc_dev))); |
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143 | while (bus_read_2(sc->smc_reg, MMUCR) & MMUCR_BUSY) |
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144 | ; |
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145 | } |
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146 | |
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147 | static __inline uint8_t |
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148 | smc_read_1(struct smc_softc *sc, bus_addr_t offset) |
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149 | { |
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150 | |
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151 | return (bus_read_1(sc->smc_reg, offset)); |
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152 | } |
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153 | |
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154 | static __inline void |
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155 | smc_write_1(struct smc_softc *sc, bus_addr_t offset, uint8_t val) |
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156 | { |
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157 | |
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158 | bus_write_1(sc->smc_reg, offset, val); |
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159 | } |
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160 | |
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161 | static __inline uint16_t |
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162 | smc_read_2(struct smc_softc *sc, bus_addr_t offset) |
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163 | { |
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164 | |
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165 | return (bus_read_2(sc->smc_reg, offset)); |
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166 | } |
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167 | |
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168 | static __inline void |
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169 | smc_write_2(struct smc_softc *sc, bus_addr_t offset, uint16_t val) |
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170 | { |
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171 | |
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172 | bus_write_2(sc->smc_reg, offset, val); |
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173 | } |
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174 | |
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175 | static __inline void |
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176 | smc_read_multi_2(struct smc_softc *sc, bus_addr_t offset, uint16_t *datap, |
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177 | bus_size_t count) |
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178 | { |
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179 | |
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180 | bus_read_multi_2(sc->smc_reg, offset, datap, count); |
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181 | } |
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182 | |
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183 | static __inline void |
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184 | smc_write_multi_2(struct smc_softc *sc, bus_addr_t offset, uint16_t *datap, |
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185 | bus_size_t count) |
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186 | { |
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187 | |
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188 | bus_write_multi_2(sc->smc_reg, offset, datap, count); |
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189 | } |
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190 | |
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191 | int |
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192 | smc_probe(device_t dev) |
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193 | { |
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194 | int rid, type, error; |
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195 | uint16_t val; |
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196 | struct smc_softc *sc; |
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197 | struct resource *reg; |
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198 | |
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199 | sc = device_get_softc(dev); |
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200 | rid = 0; |
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201 | type = SYS_RES_IOPORT; |
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202 | error = 0; |
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203 | |
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204 | if (sc->smc_usemem) |
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205 | type = SYS_RES_MEMORY; |
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206 | |
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207 | reg = bus_alloc_resource(dev, type, &rid, 0, ~0, 16, RF_ACTIVE); |
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208 | if (reg == NULL) { |
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209 | if (bootverbose) |
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210 | device_printf(dev, |
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211 | "could not allocate I/O resource for probe\n"); |
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212 | return (ENXIO); |
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213 | } |
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214 | |
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215 | /* Check for the identification value in the BSR. */ |
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216 | val = bus_read_2(reg, BSR); |
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217 | if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) { |
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218 | if (bootverbose) |
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219 | device_printf(dev, "identification value not in BSR\n"); |
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220 | error = ENXIO; |
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221 | goto done; |
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222 | } |
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223 | |
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224 | /* |
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225 | * Try switching banks and make sure we still get the identification |
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226 | * value. |
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227 | */ |
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228 | bus_write_2(reg, BSR, 0); |
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229 | val = bus_read_2(reg, BSR); |
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230 | if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) { |
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231 | if (bootverbose) |
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232 | device_printf(dev, |
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233 | "identification value not in BSR after write\n"); |
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234 | error = ENXIO; |
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235 | goto done; |
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236 | } |
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237 | |
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238 | #if 0 |
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239 | /* Check the BAR. */ |
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240 | bus_write_2(reg, BSR, 1); |
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241 | val = bus_read_2(reg, BAR); |
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242 | val = BAR_ADDRESS(val); |
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243 | if (rman_get_start(reg) != val) { |
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244 | if (bootverbose) |
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245 | device_printf(dev, "BAR address %x does not match " |
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246 | "I/O resource address %lx\n", val, |
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247 | rman_get_start(reg)); |
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248 | error = ENXIO; |
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249 | goto done; |
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250 | } |
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251 | #endif |
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252 | |
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253 | /* Compare REV against known chip revisions. */ |
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254 | bus_write_2(reg, BSR, 3); |
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255 | val = bus_read_2(reg, REV); |
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256 | val = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT; |
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257 | if (smc_chip_ids[val] == NULL) { |
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258 | if (bootverbose) |
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259 | device_printf(dev, "Unknown chip revision: %d\n", val); |
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260 | error = ENXIO; |
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261 | goto done; |
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262 | } |
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263 | |
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264 | device_set_desc(dev, smc_chip_ids[val]); |
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265 | |
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266 | done: |
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267 | bus_release_resource(dev, type, rid, reg); |
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268 | return (error); |
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269 | } |
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270 | |
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271 | int |
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272 | smc_attach(device_t dev) |
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273 | { |
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274 | int type, error; |
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275 | uint16_t val; |
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276 | u_char eaddr[ETHER_ADDR_LEN]; |
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277 | struct smc_softc *sc; |
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278 | struct ifnet *ifp; |
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279 | |
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280 | sc = device_get_softc(dev); |
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281 | error = 0; |
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282 | |
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283 | sc->smc_dev = dev; |
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284 | |
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285 | ifp = sc->smc_ifp = if_alloc(IFT_ETHER); |
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286 | if (ifp == NULL) { |
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287 | error = ENOSPC; |
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288 | goto done; |
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289 | } |
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290 | |
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291 | mtx_init(&sc->smc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); |
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292 | |
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293 | /* Set up watchdog callout. */ |
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294 | callout_init_mtx(&sc->smc_watchdog, &sc->smc_mtx, 0); |
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295 | |
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296 | type = SYS_RES_IOPORT; |
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297 | if (sc->smc_usemem) |
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298 | type = SYS_RES_MEMORY; |
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299 | |
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300 | sc->smc_reg_rid = 0; |
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301 | sc->smc_reg = bus_alloc_resource(dev, type, &sc->smc_reg_rid, 0, ~0, |
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302 | 16, RF_ACTIVE); |
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303 | if (sc->smc_reg == NULL) { |
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304 | error = ENXIO; |
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305 | goto done; |
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306 | } |
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307 | |
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308 | sc->smc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->smc_irq_rid, 0, |
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309 | ~0, 1, RF_ACTIVE | RF_SHAREABLE); |
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310 | if (sc->smc_irq == NULL) { |
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311 | error = ENXIO; |
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312 | goto done; |
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313 | } |
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314 | |
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315 | SMC_LOCK(sc); |
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316 | smc_reset(sc); |
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317 | SMC_UNLOCK(sc); |
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318 | |
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319 | smc_select_bank(sc, 3); |
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320 | val = smc_read_2(sc, REV); |
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321 | sc->smc_chip = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT; |
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322 | sc->smc_rev = (val * REV_REV_MASK) >> REV_REV_SHIFT; |
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323 | if (bootverbose) |
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324 | device_printf(dev, "revision %x\n", sc->smc_rev); |
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325 | |
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326 | callout_init_mtx(&sc->smc_mii_tick_ch, &sc->smc_mtx, |
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327 | CALLOUT_RETURNUNLOCKED); |
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328 | if (sc->smc_chip >= REV_CHIP_91110FD) { |
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329 | (void)mii_attach(dev, &sc->smc_miibus, ifp, |
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330 | smc_mii_ifmedia_upd, smc_mii_ifmedia_sts, BMSR_DEFCAPMASK, |
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331 | MII_PHY_ANY, MII_OFFSET_ANY, 0); |
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332 | if (sc->smc_miibus != NULL) { |
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333 | sc->smc_mii_tick = smc_mii_tick; |
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334 | sc->smc_mii_mediachg = smc_mii_mediachg; |
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335 | sc->smc_mii_mediaioctl = smc_mii_mediaioctl; |
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336 | } |
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337 | } |
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338 | |
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339 | smc_select_bank(sc, 1); |
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340 | eaddr[0] = smc_read_1(sc, IAR0); |
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341 | eaddr[1] = smc_read_1(sc, IAR1); |
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342 | eaddr[2] = smc_read_1(sc, IAR2); |
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343 | eaddr[3] = smc_read_1(sc, IAR3); |
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344 | eaddr[4] = smc_read_1(sc, IAR4); |
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345 | eaddr[5] = smc_read_1(sc, IAR5); |
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346 | |
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347 | if_initname(ifp, device_get_name(dev), device_get_unit(dev)); |
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348 | ifp->if_softc = sc; |
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349 | ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; |
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350 | ifp->if_init = smc_init; |
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351 | ifp->if_ioctl = smc_ioctl; |
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352 | ifp->if_start = smc_start; |
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353 | IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); |
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354 | IFQ_SET_READY(&ifp->if_snd); |
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355 | |
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356 | ifp->if_capabilities = ifp->if_capenable = 0; |
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357 | |
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358 | #ifdef DEVICE_POLLING |
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359 | ifp->if_capabilities |= IFCAP_POLLING; |
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360 | #endif |
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361 | |
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362 | ether_ifattach(ifp, eaddr); |
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363 | |
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364 | /* Set up taskqueue */ |
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365 | TASK_INIT(&sc->smc_intr, SMC_INTR_PRIORITY, smc_task_intr, ifp); |
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366 | TASK_INIT(&sc->smc_rx, SMC_RX_PRIORITY, smc_task_rx, ifp); |
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367 | TASK_INIT(&sc->smc_tx, SMC_TX_PRIORITY, smc_task_tx, ifp); |
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368 | sc->smc_tq = taskqueue_create_fast("smc_taskq", M_NOWAIT, |
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369 | taskqueue_thread_enqueue, &sc->smc_tq); |
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370 | taskqueue_start_threads(&sc->smc_tq, 1, PI_NET, "%s taskq", |
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371 | device_get_nameunit(sc->smc_dev)); |
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372 | |
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373 | /* Mask all interrupts. */ |
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374 | sc->smc_mask = 0; |
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375 | smc_write_1(sc, MSK, 0); |
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376 | |
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377 | /* Wire up interrupt */ |
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378 | error = bus_setup_intr(dev, sc->smc_irq, |
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379 | INTR_TYPE_NET|INTR_MPSAFE, smc_intr, NULL, sc, &sc->smc_ih); |
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380 | if (error != 0) |
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381 | goto done; |
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382 | |
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383 | done: |
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384 | if (error != 0) |
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385 | smc_detach(dev); |
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386 | return (error); |
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387 | } |
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388 | |
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389 | int |
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390 | smc_detach(device_t dev) |
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391 | { |
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392 | int type; |
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393 | struct smc_softc *sc; |
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394 | |
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395 | sc = device_get_softc(dev); |
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396 | SMC_LOCK(sc); |
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397 | smc_stop(sc); |
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398 | SMC_UNLOCK(sc); |
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399 | |
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400 | if (sc->smc_ifp != NULL) { |
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401 | ether_ifdetach(sc->smc_ifp); |
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402 | } |
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403 | |
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404 | callout_drain(&sc->smc_watchdog); |
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405 | callout_drain(&sc->smc_mii_tick_ch); |
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406 | |
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407 | #ifdef DEVICE_POLLING |
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408 | if (sc->smc_ifp->if_capenable & IFCAP_POLLING) |
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409 | ether_poll_deregister(sc->smc_ifp); |
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410 | #endif |
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411 | |
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412 | if (sc->smc_ih != NULL) |
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413 | bus_teardown_intr(sc->smc_dev, sc->smc_irq, sc->smc_ih); |
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414 | |
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415 | if (sc->smc_tq != NULL) { |
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416 | taskqueue_drain(sc->smc_tq, &sc->smc_intr); |
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417 | taskqueue_drain(sc->smc_tq, &sc->smc_rx); |
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418 | taskqueue_drain(sc->smc_tq, &sc->smc_tx); |
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419 | taskqueue_free(sc->smc_tq); |
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420 | sc->smc_tq = NULL; |
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421 | } |
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422 | |
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423 | if (sc->smc_ifp != NULL) { |
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424 | if_free(sc->smc_ifp); |
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425 | } |
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426 | |
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427 | if (sc->smc_miibus != NULL) { |
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428 | device_delete_child(sc->smc_dev, sc->smc_miibus); |
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429 | bus_generic_detach(sc->smc_dev); |
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430 | } |
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431 | |
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432 | if (sc->smc_reg != NULL) { |
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433 | type = SYS_RES_IOPORT; |
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434 | if (sc->smc_usemem) |
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435 | type = SYS_RES_MEMORY; |
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436 | |
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437 | bus_release_resource(sc->smc_dev, type, sc->smc_reg_rid, |
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438 | sc->smc_reg); |
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439 | } |
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440 | |
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441 | if (sc->smc_irq != NULL) |
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442 | bus_release_resource(sc->smc_dev, SYS_RES_IRQ, sc->smc_irq_rid, |
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443 | sc->smc_irq); |
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444 | |
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445 | if (mtx_initialized(&sc->smc_mtx)) |
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446 | mtx_destroy(&sc->smc_mtx); |
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447 | |
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448 | return (0); |
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449 | } |
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450 | |
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451 | static void |
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452 | smc_start(struct ifnet *ifp) |
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453 | { |
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454 | struct smc_softc *sc; |
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455 | |
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456 | sc = ifp->if_softc; |
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457 | SMC_LOCK(sc); |
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458 | smc_start_locked(ifp); |
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459 | SMC_UNLOCK(sc); |
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460 | } |
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461 | |
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462 | static void |
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463 | smc_start_locked(struct ifnet *ifp) |
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464 | { |
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465 | struct smc_softc *sc; |
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466 | struct mbuf *m; |
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467 | u_int len, npages, spin_count; |
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468 | |
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469 | sc = ifp->if_softc; |
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470 | SMC_ASSERT_LOCKED(sc); |
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471 | |
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472 | if (ifp->if_drv_flags & IFF_DRV_OACTIVE) |
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473 | return; |
---|
474 | if (IFQ_IS_EMPTY(&ifp->if_snd)) |
---|
475 | return; |
---|
476 | |
---|
477 | /* |
---|
478 | * Grab the next packet. If it's too big, drop it. |
---|
479 | */ |
---|
480 | IFQ_DRV_DEQUEUE(&ifp->if_snd, m); |
---|
481 | len = m_length(m, NULL); |
---|
482 | len += (len & 1); |
---|
483 | if (len > ETHER_MAX_LEN - ETHER_CRC_LEN) { |
---|
484 | if_printf(ifp, "large packet discarded\n"); |
---|
485 | ++ifp->if_oerrors; |
---|
486 | m_freem(m); |
---|
487 | return; /* XXX readcheck? */ |
---|
488 | } |
---|
489 | |
---|
490 | /* |
---|
491 | * Flag that we're busy. |
---|
492 | */ |
---|
493 | ifp->if_drv_flags |= IFF_DRV_OACTIVE; |
---|
494 | sc->smc_pending = m; |
---|
495 | |
---|
496 | /* |
---|
497 | * Work out how many 256 byte "pages" we need. We have to include the |
---|
498 | * control data for the packet in this calculation. |
---|
499 | */ |
---|
500 | npages = (len * PKT_CTRL_DATA_LEN) >> 8; |
---|
501 | if (npages == 0) |
---|
502 | npages = 1; |
---|
503 | |
---|
504 | /* |
---|
505 | * Request memory. |
---|
506 | */ |
---|
507 | smc_select_bank(sc, 2); |
---|
508 | smc_mmu_wait(sc); |
---|
509 | smc_write_2(sc, MMUCR, MMUCR_CMD_TX_ALLOC | npages); |
---|
510 | |
---|
511 | /* |
---|
512 | * Spin briefly to see if the allocation succeeds. |
---|
513 | */ |
---|
514 | spin_count = TX_ALLOC_WAIT_TIME; |
---|
515 | do { |
---|
516 | if (smc_read_1(sc, IST) & ALLOC_INT) { |
---|
517 | smc_write_1(sc, ACK, ALLOC_INT); |
---|
518 | break; |
---|
519 | } |
---|
520 | } while (--spin_count); |
---|
521 | |
---|
522 | /* |
---|
523 | * If the allocation is taking too long, unmask the alloc interrupt |
---|
524 | * and wait. |
---|
525 | */ |
---|
526 | if (spin_count == 0) { |
---|
527 | sc->smc_mask |= ALLOC_INT; |
---|
528 | if ((ifp->if_capenable & IFCAP_POLLING) == 0) |
---|
529 | smc_write_1(sc, MSK, sc->smc_mask); |
---|
530 | return; |
---|
531 | } |
---|
532 | |
---|
533 | taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx); |
---|
534 | } |
---|
535 | |
---|
536 | static void |
---|
537 | smc_task_tx(void *context, int pending) |
---|
538 | { |
---|
539 | struct ifnet *ifp; |
---|
540 | struct smc_softc *sc; |
---|
541 | struct mbuf *m, *m0; |
---|
542 | u_int packet, len; |
---|
543 | uint8_t *data; |
---|
544 | |
---|
545 | (void)pending; |
---|
546 | ifp = (struct ifnet *)context; |
---|
547 | sc = ifp->if_softc; |
---|
548 | |
---|
549 | SMC_LOCK(sc); |
---|
550 | |
---|
551 | if (sc->smc_pending == NULL) { |
---|
552 | SMC_UNLOCK(sc); |
---|
553 | goto next_packet; |
---|
554 | } |
---|
555 | |
---|
556 | m = m0 = sc->smc_pending; |
---|
557 | sc->smc_pending = NULL; |
---|
558 | smc_select_bank(sc, 2); |
---|
559 | |
---|
560 | /* |
---|
561 | * Check the allocation result. |
---|
562 | */ |
---|
563 | packet = smc_read_1(sc, ARR); |
---|
564 | |
---|
565 | /* |
---|
566 | * If the allocation failed, requeue the packet and retry. |
---|
567 | */ |
---|
568 | if (packet & ARR_FAILED) { |
---|
569 | IFQ_DRV_PREPEND(&ifp->if_snd, m); |
---|
570 | ++ifp->if_oerrors; |
---|
571 | ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; |
---|
572 | smc_start_locked(ifp); |
---|
573 | SMC_UNLOCK(sc); |
---|
574 | return; |
---|
575 | } |
---|
576 | |
---|
577 | /* |
---|
578 | * Tell the device to write to our packet number. |
---|
579 | */ |
---|
580 | smc_write_1(sc, PNR, packet); |
---|
581 | smc_write_2(sc, PTR, 0 | PTR_AUTO_INCR); |
---|
582 | |
---|
583 | /* |
---|
584 | * Tell the device how long the packet is (including control data). |
---|
585 | */ |
---|
586 | len = m_length(m, 0); |
---|
587 | len += PKT_CTRL_DATA_LEN; |
---|
588 | smc_write_2(sc, DATA0, 0); |
---|
589 | smc_write_2(sc, DATA0, len); |
---|
590 | |
---|
591 | /* |
---|
592 | * Push the data out to the device. |
---|
593 | */ |
---|
594 | data = NULL; |
---|
595 | for (; m != NULL; m = m->m_next) { |
---|
596 | data = mtod(m, uint8_t *); |
---|
597 | smc_write_multi_2(sc, DATA0, (uint16_t *)data, m->m_len / 2); |
---|
598 | } |
---|
599 | |
---|
600 | /* |
---|
601 | * Push out the control byte and and the odd byte if needed. |
---|
602 | */ |
---|
603 | if ((len & 1) != 0 && data != NULL) |
---|
604 | smc_write_2(sc, DATA0, (CTRL_ODD << 8) | data[m->m_len - 1]); |
---|
605 | else |
---|
606 | smc_write_2(sc, DATA0, 0); |
---|
607 | |
---|
608 | /* |
---|
609 | * Unmask the TX empty interrupt. |
---|
610 | */ |
---|
611 | sc->smc_mask |= TX_EMPTY_INT; |
---|
612 | if ((ifp->if_capenable & IFCAP_POLLING) == 0) |
---|
613 | smc_write_1(sc, MSK, sc->smc_mask); |
---|
614 | |
---|
615 | /* |
---|
616 | * Enqueue the packet. |
---|
617 | */ |
---|
618 | smc_mmu_wait(sc); |
---|
619 | smc_write_2(sc, MMUCR, MMUCR_CMD_ENQUEUE); |
---|
620 | callout_reset(&sc->smc_watchdog, hz * 2, smc_watchdog, sc); |
---|
621 | |
---|
622 | /* |
---|
623 | * Finish up. |
---|
624 | */ |
---|
625 | ifp->if_opackets++; |
---|
626 | ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; |
---|
627 | SMC_UNLOCK(sc); |
---|
628 | BPF_MTAP(ifp, m0); |
---|
629 | m_freem(m0); |
---|
630 | |
---|
631 | next_packet: |
---|
632 | /* |
---|
633 | * See if there's anything else to do. |
---|
634 | */ |
---|
635 | smc_start(ifp); |
---|
636 | } |
---|
637 | |
---|
638 | static void |
---|
639 | smc_task_rx(void *context, int pending) |
---|
640 | { |
---|
641 | u_int packet, status, len; |
---|
642 | uint8_t *data; |
---|
643 | struct ifnet *ifp; |
---|
644 | struct smc_softc *sc; |
---|
645 | struct mbuf *m, *mhead, *mtail; |
---|
646 | |
---|
647 | (void)pending; |
---|
648 | ifp = (struct ifnet *)context; |
---|
649 | sc = ifp->if_softc; |
---|
650 | mhead = mtail = NULL; |
---|
651 | |
---|
652 | SMC_LOCK(sc); |
---|
653 | |
---|
654 | packet = smc_read_1(sc, FIFO_RX); |
---|
655 | while ((packet & FIFO_EMPTY) == 0) { |
---|
656 | /* |
---|
657 | * Grab an mbuf and attach a cluster. |
---|
658 | */ |
---|
659 | MGETHDR(m, M_DONTWAIT, MT_DATA); |
---|
660 | if (m == NULL) { |
---|
661 | break; |
---|
662 | } |
---|
663 | MCLGET(m, M_DONTWAIT); |
---|
664 | if ((m->m_flags & M_EXT) == 0) { |
---|
665 | m_freem(m); |
---|
666 | break; |
---|
667 | } |
---|
668 | |
---|
669 | /* |
---|
670 | * Point to the start of the packet. |
---|
671 | */ |
---|
672 | smc_select_bank(sc, 2); |
---|
673 | smc_write_1(sc, PNR, packet); |
---|
674 | smc_write_2(sc, PTR, 0 | PTR_READ | PTR_RCV | PTR_AUTO_INCR); |
---|
675 | |
---|
676 | /* |
---|
677 | * Grab status and packet length. |
---|
678 | */ |
---|
679 | status = smc_read_2(sc, DATA0); |
---|
680 | len = smc_read_2(sc, DATA0) & RX_LEN_MASK; |
---|
681 | len -= 6; |
---|
682 | if (status & RX_ODDFRM) |
---|
683 | len += 1; |
---|
684 | |
---|
685 | /* |
---|
686 | * Check for errors. |
---|
687 | */ |
---|
688 | if (status & (RX_TOOSHORT | RX_TOOLNG | RX_BADCRC | RX_ALGNERR)) { |
---|
689 | smc_mmu_wait(sc); |
---|
690 | smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE); |
---|
691 | ifp->if_ierrors++; |
---|
692 | m_freem(m); |
---|
693 | break; |
---|
694 | } |
---|
695 | |
---|
696 | /* |
---|
697 | * Set the mbuf up the way we want it. |
---|
698 | */ |
---|
699 | m->m_pkthdr.rcvif = ifp; |
---|
700 | m->m_pkthdr.len = m->m_len = len + 2; /* XXX: Is this right? */ |
---|
701 | m_adj(m, ETHER_ALIGN); |
---|
702 | |
---|
703 | /* |
---|
704 | * Pull the packet out of the device. Make sure we're in the |
---|
705 | * right bank first as things may have changed while we were |
---|
706 | * allocating our mbuf. |
---|
707 | */ |
---|
708 | smc_select_bank(sc, 2); |
---|
709 | smc_write_1(sc, PNR, packet); |
---|
710 | smc_write_2(sc, PTR, 4 | PTR_READ | PTR_RCV | PTR_AUTO_INCR); |
---|
711 | data = mtod(m, uint8_t *); |
---|
712 | smc_read_multi_2(sc, DATA0, (uint16_t *)data, len >> 1); |
---|
713 | if (len & 1) { |
---|
714 | data += len & ~1; |
---|
715 | *data = smc_read_1(sc, DATA0); |
---|
716 | } |
---|
717 | |
---|
718 | /* |
---|
719 | * Tell the device we're done. |
---|
720 | */ |
---|
721 | smc_mmu_wait(sc); |
---|
722 | smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE); |
---|
723 | if (m == NULL) { |
---|
724 | break; |
---|
725 | } |
---|
726 | |
---|
727 | if (mhead == NULL) { |
---|
728 | mhead = mtail = m; |
---|
729 | m->m_next = NULL; |
---|
730 | } else { |
---|
731 | mtail->m_next = m; |
---|
732 | mtail = m; |
---|
733 | } |
---|
734 | packet = smc_read_1(sc, FIFO_RX); |
---|
735 | } |
---|
736 | |
---|
737 | sc->smc_mask |= RCV_INT; |
---|
738 | if ((ifp->if_capenable & IFCAP_POLLING) == 0) |
---|
739 | smc_write_1(sc, MSK, sc->smc_mask); |
---|
740 | |
---|
741 | SMC_UNLOCK(sc); |
---|
742 | |
---|
743 | while (mhead != NULL) { |
---|
744 | m = mhead; |
---|
745 | mhead = mhead->m_next; |
---|
746 | m->m_next = NULL; |
---|
747 | ifp->if_ipackets++; |
---|
748 | (*ifp->if_input)(ifp, m); |
---|
749 | } |
---|
750 | } |
---|
751 | |
---|
752 | #ifdef DEVICE_POLLING |
---|
753 | static void |
---|
754 | smc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) |
---|
755 | { |
---|
756 | struct smc_softc *sc; |
---|
757 | |
---|
758 | sc = ifp->if_softc; |
---|
759 | |
---|
760 | SMC_LOCK(sc); |
---|
761 | if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { |
---|
762 | SMC_UNLOCK(sc); |
---|
763 | return; |
---|
764 | } |
---|
765 | SMC_UNLOCK(sc); |
---|
766 | |
---|
767 | if (cmd == POLL_AND_CHECK_STATUS) |
---|
768 | taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_intr); |
---|
769 | } |
---|
770 | #endif |
---|
771 | |
---|
772 | static int |
---|
773 | smc_intr(void *context) |
---|
774 | { |
---|
775 | struct smc_softc *sc; |
---|
776 | |
---|
777 | sc = (struct smc_softc *)context; |
---|
778 | taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_intr); |
---|
779 | return (FILTER_HANDLED); |
---|
780 | } |
---|
781 | |
---|
782 | static void |
---|
783 | smc_task_intr(void *context, int pending) |
---|
784 | { |
---|
785 | struct smc_softc *sc; |
---|
786 | struct ifnet *ifp; |
---|
787 | u_int status, packet, counter, tcr; |
---|
788 | |
---|
789 | (void)pending; |
---|
790 | ifp = (struct ifnet *)context; |
---|
791 | sc = ifp->if_softc; |
---|
792 | |
---|
793 | SMC_LOCK(sc); |
---|
794 | |
---|
795 | smc_select_bank(sc, 2); |
---|
796 | |
---|
797 | /* |
---|
798 | * Get the current mask, and then block all interrupts while we're |
---|
799 | * working. |
---|
800 | */ |
---|
801 | if ((ifp->if_capenable & IFCAP_POLLING) == 0) |
---|
802 | smc_write_1(sc, MSK, 0); |
---|
803 | |
---|
804 | /* |
---|
805 | * Find out what interrupts are flagged. |
---|
806 | */ |
---|
807 | status = smc_read_1(sc, IST) & sc->smc_mask; |
---|
808 | |
---|
809 | /* |
---|
810 | * Transmit error |
---|
811 | */ |
---|
812 | if (status & TX_INT) { |
---|
813 | /* |
---|
814 | * Kill off the packet if there is one and re-enable transmit. |
---|
815 | */ |
---|
816 | packet = smc_read_1(sc, FIFO_TX); |
---|
817 | if ((packet & FIFO_EMPTY) == 0) { |
---|
818 | smc_write_1(sc, PNR, packet); |
---|
819 | smc_write_2(sc, PTR, 0 | PTR_READ | |
---|
820 | PTR_AUTO_INCR); |
---|
821 | tcr = smc_read_2(sc, DATA0); |
---|
822 | if ((tcr & EPHSR_TX_SUC) == 0) |
---|
823 | device_printf(sc->smc_dev, |
---|
824 | "bad packet\n"); |
---|
825 | smc_mmu_wait(sc); |
---|
826 | smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE_PKT); |
---|
827 | |
---|
828 | smc_select_bank(sc, 0); |
---|
829 | tcr = smc_read_2(sc, TCR); |
---|
830 | tcr |= TCR_TXENA | TCR_PAD_EN; |
---|
831 | smc_write_2(sc, TCR, tcr); |
---|
832 | smc_select_bank(sc, 2); |
---|
833 | taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx); |
---|
834 | } |
---|
835 | |
---|
836 | /* |
---|
837 | * Ack the interrupt. |
---|
838 | */ |
---|
839 | smc_write_1(sc, ACK, TX_INT); |
---|
840 | } |
---|
841 | |
---|
842 | /* |
---|
843 | * Receive |
---|
844 | */ |
---|
845 | if (status & RCV_INT) { |
---|
846 | smc_write_1(sc, ACK, RCV_INT); |
---|
847 | sc->smc_mask &= ~RCV_INT; |
---|
848 | taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_rx); |
---|
849 | } |
---|
850 | |
---|
851 | /* |
---|
852 | * Allocation |
---|
853 | */ |
---|
854 | if (status & ALLOC_INT) { |
---|
855 | smc_write_1(sc, ACK, ALLOC_INT); |
---|
856 | sc->smc_mask &= ~ALLOC_INT; |
---|
857 | taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx); |
---|
858 | } |
---|
859 | |
---|
860 | /* |
---|
861 | * Receive overrun |
---|
862 | */ |
---|
863 | if (status & RX_OVRN_INT) { |
---|
864 | smc_write_1(sc, ACK, RX_OVRN_INT); |
---|
865 | ifp->if_ierrors++; |
---|
866 | } |
---|
867 | |
---|
868 | /* |
---|
869 | * Transmit empty |
---|
870 | */ |
---|
871 | if (status & TX_EMPTY_INT) { |
---|
872 | smc_write_1(sc, ACK, TX_EMPTY_INT); |
---|
873 | sc->smc_mask &= ~TX_EMPTY_INT; |
---|
874 | callout_stop(&sc->smc_watchdog); |
---|
875 | |
---|
876 | /* |
---|
877 | * Update collision stats. |
---|
878 | */ |
---|
879 | smc_select_bank(sc, 0); |
---|
880 | counter = smc_read_2(sc, ECR); |
---|
881 | smc_select_bank(sc, 2); |
---|
882 | ifp->if_collisions += |
---|
883 | (counter & ECR_SNGLCOL_MASK) >> ECR_SNGLCOL_SHIFT; |
---|
884 | ifp->if_collisions += |
---|
885 | (counter & ECR_MULCOL_MASK) >> ECR_MULCOL_SHIFT; |
---|
886 | |
---|
887 | /* |
---|
888 | * See if there are any packets to transmit. |
---|
889 | */ |
---|
890 | taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx); |
---|
891 | } |
---|
892 | |
---|
893 | /* |
---|
894 | * Update the interrupt mask. |
---|
895 | */ |
---|
896 | if ((ifp->if_capenable & IFCAP_POLLING) == 0) |
---|
897 | smc_write_1(sc, MSK, sc->smc_mask); |
---|
898 | |
---|
899 | SMC_UNLOCK(sc); |
---|
900 | } |
---|
901 | |
---|
902 | static u_int |
---|
903 | smc_mii_readbits(struct smc_softc *sc, int nbits) |
---|
904 | { |
---|
905 | u_int mgmt, mask, val; |
---|
906 | |
---|
907 | SMC_ASSERT_LOCKED(sc); |
---|
908 | KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3, |
---|
909 | ("%s: smc_mii_readbits called with bank %d (!= 3)", |
---|
910 | device_get_nameunit(sc->smc_dev), |
---|
911 | smc_read_2(sc, BSR) & BSR_BANK_MASK)); |
---|
912 | |
---|
913 | /* |
---|
914 | * Set up the MGMT (aka MII) register. |
---|
915 | */ |
---|
916 | mgmt = smc_read_2(sc, MGMT) & ~(MGMT_MCLK | MGMT_MDOE | MGMT_MDO); |
---|
917 | smc_write_2(sc, MGMT, mgmt); |
---|
918 | |
---|
919 | /* |
---|
920 | * Read the bits in. |
---|
921 | */ |
---|
922 | for (mask = 1 << (nbits - 1), val = 0; mask; mask >>= 1) { |
---|
923 | if (smc_read_2(sc, MGMT) & MGMT_MDI) |
---|
924 | val |= mask; |
---|
925 | |
---|
926 | smc_write_2(sc, MGMT, mgmt); |
---|
927 | DELAY(1); |
---|
928 | smc_write_2(sc, MGMT, mgmt | MGMT_MCLK); |
---|
929 | DELAY(1); |
---|
930 | } |
---|
931 | |
---|
932 | return (val); |
---|
933 | } |
---|
934 | |
---|
935 | static void |
---|
936 | smc_mii_writebits(struct smc_softc *sc, u_int val, int nbits) |
---|
937 | { |
---|
938 | u_int mgmt, mask; |
---|
939 | |
---|
940 | SMC_ASSERT_LOCKED(sc); |
---|
941 | KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3, |
---|
942 | ("%s: smc_mii_writebits called with bank %d (!= 3)", |
---|
943 | device_get_nameunit(sc->smc_dev), |
---|
944 | smc_read_2(sc, BSR) & BSR_BANK_MASK)); |
---|
945 | |
---|
946 | /* |
---|
947 | * Set up the MGMT (aka MII) register). |
---|
948 | */ |
---|
949 | mgmt = smc_read_2(sc, MGMT) & ~(MGMT_MCLK | MGMT_MDOE | MGMT_MDO); |
---|
950 | mgmt |= MGMT_MDOE; |
---|
951 | |
---|
952 | /* |
---|
953 | * Push the bits out. |
---|
954 | */ |
---|
955 | for (mask = 1 << (nbits - 1); mask; mask >>= 1) { |
---|
956 | if (val & mask) |
---|
957 | mgmt |= MGMT_MDO; |
---|
958 | else |
---|
959 | mgmt &= ~MGMT_MDO; |
---|
960 | |
---|
961 | smc_write_2(sc, MGMT, mgmt); |
---|
962 | DELAY(1); |
---|
963 | smc_write_2(sc, MGMT, mgmt | MGMT_MCLK); |
---|
964 | DELAY(1); |
---|
965 | } |
---|
966 | } |
---|
967 | |
---|
968 | int |
---|
969 | smc_miibus_readreg(device_t dev, int phy, int reg) |
---|
970 | { |
---|
971 | struct smc_softc *sc; |
---|
972 | int val; |
---|
973 | |
---|
974 | sc = device_get_softc(dev); |
---|
975 | |
---|
976 | SMC_LOCK(sc); |
---|
977 | |
---|
978 | smc_select_bank(sc, 3); |
---|
979 | |
---|
980 | /* |
---|
981 | * Send out the idle pattern. |
---|
982 | */ |
---|
983 | smc_mii_writebits(sc, 0xffffffff, 32); |
---|
984 | |
---|
985 | /* |
---|
986 | * Start code + read opcode + phy address + phy register |
---|
987 | */ |
---|
988 | smc_mii_writebits(sc, 6 << 10 | phy << 5 | reg, 14); |
---|
989 | |
---|
990 | /* |
---|
991 | * Turnaround + data |
---|
992 | */ |
---|
993 | val = smc_mii_readbits(sc, 18); |
---|
994 | |
---|
995 | /* |
---|
996 | * Reset the MDIO interface. |
---|
997 | */ |
---|
998 | smc_write_2(sc, MGMT, |
---|
999 | smc_read_2(sc, MGMT) & ~(MGMT_MCLK | MGMT_MDOE | MGMT_MDO)); |
---|
1000 | |
---|
1001 | SMC_UNLOCK(sc); |
---|
1002 | return (val); |
---|
1003 | } |
---|
1004 | |
---|
1005 | int |
---|
1006 | smc_miibus_writereg(device_t dev, int phy, int reg, int data) |
---|
1007 | { |
---|
1008 | struct smc_softc *sc; |
---|
1009 | |
---|
1010 | sc = device_get_softc(dev); |
---|
1011 | |
---|
1012 | SMC_LOCK(sc); |
---|
1013 | |
---|
1014 | smc_select_bank(sc, 3); |
---|
1015 | |
---|
1016 | /* |
---|
1017 | * Send idle pattern. |
---|
1018 | */ |
---|
1019 | smc_mii_writebits(sc, 0xffffffff, 32); |
---|
1020 | |
---|
1021 | /* |
---|
1022 | * Start code + write opcode + phy address + phy register + turnaround |
---|
1023 | * + data. |
---|
1024 | */ |
---|
1025 | smc_mii_writebits(sc, 5 << 28 | phy << 23 | reg << 18 | 2 << 16 | data, |
---|
1026 | 32); |
---|
1027 | |
---|
1028 | /* |
---|
1029 | * Reset MDIO interface. |
---|
1030 | */ |
---|
1031 | smc_write_2(sc, MGMT, |
---|
1032 | smc_read_2(sc, MGMT) & ~(MGMT_MCLK | MGMT_MDOE | MGMT_MDO)); |
---|
1033 | |
---|
1034 | SMC_UNLOCK(sc); |
---|
1035 | return (0); |
---|
1036 | } |
---|
1037 | |
---|
1038 | void |
---|
1039 | smc_miibus_statchg(device_t dev) |
---|
1040 | { |
---|
1041 | struct smc_softc *sc; |
---|
1042 | struct mii_data *mii; |
---|
1043 | uint16_t tcr; |
---|
1044 | |
---|
1045 | sc = device_get_softc(dev); |
---|
1046 | mii = device_get_softc(sc->smc_miibus); |
---|
1047 | |
---|
1048 | SMC_LOCK(sc); |
---|
1049 | |
---|
1050 | smc_select_bank(sc, 0); |
---|
1051 | tcr = smc_read_2(sc, TCR); |
---|
1052 | |
---|
1053 | if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) |
---|
1054 | tcr |= TCR_SWFDUP; |
---|
1055 | else |
---|
1056 | tcr &= ~TCR_SWFDUP; |
---|
1057 | |
---|
1058 | smc_write_2(sc, TCR, tcr); |
---|
1059 | |
---|
1060 | SMC_UNLOCK(sc); |
---|
1061 | } |
---|
1062 | |
---|
1063 | static int |
---|
1064 | smc_mii_ifmedia_upd(struct ifnet *ifp) |
---|
1065 | { |
---|
1066 | struct smc_softc *sc; |
---|
1067 | struct mii_data *mii; |
---|
1068 | |
---|
1069 | sc = ifp->if_softc; |
---|
1070 | if (sc->smc_miibus == NULL) |
---|
1071 | return (ENXIO); |
---|
1072 | |
---|
1073 | mii = device_get_softc(sc->smc_miibus); |
---|
1074 | return (mii_mediachg(mii)); |
---|
1075 | } |
---|
1076 | |
---|
1077 | static void |
---|
1078 | smc_mii_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) |
---|
1079 | { |
---|
1080 | struct smc_softc *sc; |
---|
1081 | struct mii_data *mii; |
---|
1082 | |
---|
1083 | sc = ifp->if_softc; |
---|
1084 | if (sc->smc_miibus == NULL) |
---|
1085 | return; |
---|
1086 | |
---|
1087 | mii = device_get_softc(sc->smc_miibus); |
---|
1088 | mii_pollstat(mii); |
---|
1089 | ifmr->ifm_active = mii->mii_media_active; |
---|
1090 | ifmr->ifm_status = mii->mii_media_status; |
---|
1091 | } |
---|
1092 | |
---|
1093 | static void |
---|
1094 | smc_mii_tick(void *context) |
---|
1095 | { |
---|
1096 | struct smc_softc *sc; |
---|
1097 | |
---|
1098 | sc = (struct smc_softc *)context; |
---|
1099 | |
---|
1100 | if (sc->smc_miibus == NULL) |
---|
1101 | return; |
---|
1102 | |
---|
1103 | SMC_UNLOCK(sc); |
---|
1104 | |
---|
1105 | mii_tick(device_get_softc(sc->smc_miibus)); |
---|
1106 | callout_reset(&sc->smc_mii_tick_ch, hz, smc_mii_tick, sc); |
---|
1107 | } |
---|
1108 | |
---|
1109 | static void |
---|
1110 | smc_mii_mediachg(struct smc_softc *sc) |
---|
1111 | { |
---|
1112 | |
---|
1113 | if (sc->smc_miibus == NULL) |
---|
1114 | return; |
---|
1115 | mii_mediachg(device_get_softc(sc->smc_miibus)); |
---|
1116 | } |
---|
1117 | |
---|
1118 | static int |
---|
1119 | smc_mii_mediaioctl(struct smc_softc *sc, struct ifreq *ifr, u_long command) |
---|
1120 | { |
---|
1121 | struct mii_data *mii; |
---|
1122 | |
---|
1123 | if (sc->smc_miibus == NULL) |
---|
1124 | return (EINVAL); |
---|
1125 | |
---|
1126 | mii = device_get_softc(sc->smc_miibus); |
---|
1127 | return (ifmedia_ioctl(sc->smc_ifp, ifr, &mii->mii_media, command)); |
---|
1128 | } |
---|
1129 | |
---|
1130 | static void |
---|
1131 | smc_reset(struct smc_softc *sc) |
---|
1132 | { |
---|
1133 | u_int ctr; |
---|
1134 | |
---|
1135 | SMC_ASSERT_LOCKED(sc); |
---|
1136 | |
---|
1137 | smc_select_bank(sc, 2); |
---|
1138 | |
---|
1139 | /* |
---|
1140 | * Mask all interrupts. |
---|
1141 | */ |
---|
1142 | smc_write_1(sc, MSK, 0); |
---|
1143 | |
---|
1144 | /* |
---|
1145 | * Tell the device to reset. |
---|
1146 | */ |
---|
1147 | smc_select_bank(sc, 0); |
---|
1148 | smc_write_2(sc, RCR, RCR_SOFT_RST); |
---|
1149 | |
---|
1150 | /* |
---|
1151 | * Set up the configuration register. |
---|
1152 | */ |
---|
1153 | smc_select_bank(sc, 1); |
---|
1154 | smc_write_2(sc, CR, CR_EPH_POWER_EN); |
---|
1155 | DELAY(1); |
---|
1156 | |
---|
1157 | /* |
---|
1158 | * Turn off transmit and receive. |
---|
1159 | */ |
---|
1160 | smc_select_bank(sc, 0); |
---|
1161 | smc_write_2(sc, TCR, 0); |
---|
1162 | smc_write_2(sc, RCR, 0); |
---|
1163 | |
---|
1164 | /* |
---|
1165 | * Set up the control register. |
---|
1166 | */ |
---|
1167 | smc_select_bank(sc, 1); |
---|
1168 | ctr = smc_read_2(sc, CTR); |
---|
1169 | ctr |= CTR_LE_ENABLE | CTR_AUTO_RELEASE; |
---|
1170 | smc_write_2(sc, CTR, ctr); |
---|
1171 | |
---|
1172 | /* |
---|
1173 | * Reset the MMU. |
---|
1174 | */ |
---|
1175 | smc_select_bank(sc, 2); |
---|
1176 | smc_mmu_wait(sc); |
---|
1177 | smc_write_2(sc, MMUCR, MMUCR_CMD_MMU_RESET); |
---|
1178 | } |
---|
1179 | |
---|
1180 | static void |
---|
1181 | smc_enable(struct smc_softc *sc) |
---|
1182 | { |
---|
1183 | struct ifnet *ifp; |
---|
1184 | |
---|
1185 | SMC_ASSERT_LOCKED(sc); |
---|
1186 | ifp = sc->smc_ifp; |
---|
1187 | |
---|
1188 | /* |
---|
1189 | * Set up the receive/PHY control register. |
---|
1190 | */ |
---|
1191 | smc_select_bank(sc, 0); |
---|
1192 | smc_write_2(sc, RPCR, RPCR_ANEG | (RPCR_LED_LINK_ANY << RPCR_LSA_SHIFT) |
---|
1193 | | (RPCR_LED_ACT_ANY << RPCR_LSB_SHIFT)); |
---|
1194 | |
---|
1195 | /* |
---|
1196 | * Set up the transmit and receive control registers. |
---|
1197 | */ |
---|
1198 | smc_write_2(sc, TCR, TCR_TXENA | TCR_PAD_EN); |
---|
1199 | smc_write_2(sc, RCR, RCR_RXEN | RCR_STRIP_CRC); |
---|
1200 | |
---|
1201 | /* |
---|
1202 | * Set up the interrupt mask. |
---|
1203 | */ |
---|
1204 | smc_select_bank(sc, 2); |
---|
1205 | sc->smc_mask = EPH_INT | RX_OVRN_INT | RCV_INT | TX_INT; |
---|
1206 | if ((ifp->if_capenable & IFCAP_POLLING) != 0) |
---|
1207 | smc_write_1(sc, MSK, sc->smc_mask); |
---|
1208 | } |
---|
1209 | |
---|
1210 | static void |
---|
1211 | smc_stop(struct smc_softc *sc) |
---|
1212 | { |
---|
1213 | |
---|
1214 | SMC_ASSERT_LOCKED(sc); |
---|
1215 | |
---|
1216 | /* |
---|
1217 | * Turn off callouts. |
---|
1218 | */ |
---|
1219 | callout_stop(&sc->smc_watchdog); |
---|
1220 | callout_stop(&sc->smc_mii_tick_ch); |
---|
1221 | |
---|
1222 | /* |
---|
1223 | * Mask all interrupts. |
---|
1224 | */ |
---|
1225 | smc_select_bank(sc, 2); |
---|
1226 | sc->smc_mask = 0; |
---|
1227 | smc_write_1(sc, MSK, 0); |
---|
1228 | #ifdef DEVICE_POLLING |
---|
1229 | ether_poll_deregister(sc->smc_ifp); |
---|
1230 | sc->smc_ifp->if_capenable &= ~IFCAP_POLLING; |
---|
1231 | sc->smc_ifp->if_capenable &= ~IFCAP_POLLING_NOCOUNT; |
---|
1232 | #endif |
---|
1233 | |
---|
1234 | /* |
---|
1235 | * Disable transmit and receive. |
---|
1236 | */ |
---|
1237 | smc_select_bank(sc, 0); |
---|
1238 | smc_write_2(sc, TCR, 0); |
---|
1239 | smc_write_2(sc, RCR, 0); |
---|
1240 | |
---|
1241 | sc->smc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; |
---|
1242 | } |
---|
1243 | |
---|
1244 | static void |
---|
1245 | smc_watchdog(void *arg) |
---|
1246 | { |
---|
1247 | struct smc_softc *sc; |
---|
1248 | |
---|
1249 | sc = (struct smc_softc *)arg; |
---|
1250 | device_printf(sc->smc_dev, "watchdog timeout\n"); |
---|
1251 | taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_intr); |
---|
1252 | } |
---|
1253 | |
---|
1254 | static void |
---|
1255 | smc_init(void *context) |
---|
1256 | { |
---|
1257 | struct smc_softc *sc; |
---|
1258 | |
---|
1259 | sc = (struct smc_softc *)context; |
---|
1260 | SMC_LOCK(sc); |
---|
1261 | smc_init_locked(sc); |
---|
1262 | SMC_UNLOCK(sc); |
---|
1263 | } |
---|
1264 | |
---|
1265 | static void |
---|
1266 | smc_init_locked(struct smc_softc *sc) |
---|
1267 | { |
---|
1268 | struct ifnet *ifp; |
---|
1269 | |
---|
1270 | ifp = sc->smc_ifp; |
---|
1271 | |
---|
1272 | SMC_ASSERT_LOCKED(sc); |
---|
1273 | |
---|
1274 | smc_reset(sc); |
---|
1275 | smc_enable(sc); |
---|
1276 | |
---|
1277 | ifp->if_drv_flags |= IFF_DRV_RUNNING; |
---|
1278 | ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; |
---|
1279 | |
---|
1280 | smc_start_locked(ifp); |
---|
1281 | |
---|
1282 | if (sc->smc_mii_tick != NULL) |
---|
1283 | callout_reset(&sc->smc_mii_tick_ch, hz, sc->smc_mii_tick, sc); |
---|
1284 | |
---|
1285 | #ifdef DEVICE_POLLING |
---|
1286 | SMC_UNLOCK(sc); |
---|
1287 | ether_poll_register(smc_poll, ifp); |
---|
1288 | SMC_LOCK(sc); |
---|
1289 | ifp->if_capenable |= IFCAP_POLLING; |
---|
1290 | ifp->if_capenable |= IFCAP_POLLING_NOCOUNT; |
---|
1291 | #endif |
---|
1292 | } |
---|
1293 | |
---|
1294 | static int |
---|
1295 | smc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) |
---|
1296 | { |
---|
1297 | struct smc_softc *sc; |
---|
1298 | int error; |
---|
1299 | |
---|
1300 | sc = ifp->if_softc; |
---|
1301 | error = 0; |
---|
1302 | |
---|
1303 | switch (cmd) { |
---|
1304 | case SIOCSIFFLAGS: |
---|
1305 | if ((ifp->if_flags & IFF_UP) == 0 && |
---|
1306 | (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { |
---|
1307 | SMC_LOCK(sc); |
---|
1308 | smc_stop(sc); |
---|
1309 | SMC_UNLOCK(sc); |
---|
1310 | } else { |
---|
1311 | smc_init(sc); |
---|
1312 | if (sc->smc_mii_mediachg != NULL) |
---|
1313 | sc->smc_mii_mediachg(sc); |
---|
1314 | } |
---|
1315 | break; |
---|
1316 | |
---|
1317 | case SIOCADDMULTI: |
---|
1318 | case SIOCDELMULTI: |
---|
1319 | /* XXX |
---|
1320 | SMC_LOCK(sc); |
---|
1321 | smc_setmcast(sc); |
---|
1322 | SMC_UNLOCK(sc); |
---|
1323 | */ |
---|
1324 | error = EINVAL; |
---|
1325 | break; |
---|
1326 | |
---|
1327 | case SIOCGIFMEDIA: |
---|
1328 | case SIOCSIFMEDIA: |
---|
1329 | if (sc->smc_mii_mediaioctl == NULL) { |
---|
1330 | error = EINVAL; |
---|
1331 | break; |
---|
1332 | } |
---|
1333 | sc->smc_mii_mediaioctl(sc, (struct ifreq *)data, cmd); |
---|
1334 | break; |
---|
1335 | |
---|
1336 | default: |
---|
1337 | error = ether_ioctl(ifp, cmd, data); |
---|
1338 | break; |
---|
1339 | } |
---|
1340 | |
---|
1341 | return (error); |
---|
1342 | } |
---|