| 1 | /*- |
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| 2 | * Copyright (c) 1997, Stefan Esser <se@freebsd.org> |
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| 3 | * All rights reserved. |
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| 4 | * |
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| 5 | * Redistribution and use in source and binary forms, with or without |
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| 6 | * modification, are permitted provided that the following conditions |
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| 7 | * are met: |
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| 8 | * 1. Redistributions of source code must retain the above copyright |
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| 9 | * notice unmodified, this list of conditions, and the following |
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| 10 | * disclaimer. |
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| 11 | * 2. Redistributions in binary form must reproduce the above copyright |
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| 12 | * notice, this list of conditions and the following disclaimer in the |
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| 13 | * documentation and/or other materials provided with the distribution. |
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| 14 | * |
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| 15 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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| 16 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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| 17 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 18 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 19 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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| 20 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| 21 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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| 22 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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| 23 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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| 24 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 25 | * |
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| 26 | * $FreeBSD$ |
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| 27 | * |
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| 28 | */ |
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| 29 | |
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| 30 | #ifndef _PCIVAR_HH_ |
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| 31 | #define _PCIVAR_HH_ |
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| 32 | |
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| 33 | #include <freebsd/sys/queue.h> |
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| 34 | |
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| 35 | /* some PCI bus constants */ |
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| 36 | #define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ |
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| 37 | #define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ |
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| 38 | #define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ |
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| 39 | |
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| 40 | typedef uint64_t pci_addr_t; |
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| 41 | |
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| 42 | /* Interesting values for PCI power management */ |
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| 43 | struct pcicfg_pp { |
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| 44 | uint16_t pp_cap; /* PCI power management capabilities */ |
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| 45 | uint8_t pp_status; /* config space address of PCI power status reg */ |
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| 46 | uint8_t pp_pmcsr; /* config space address of PMCSR reg */ |
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| 47 | uint8_t pp_data; /* config space address of PCI power data reg */ |
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| 48 | }; |
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| 49 | |
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| 50 | struct vpd_readonly { |
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| 51 | char keyword[2]; |
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| 52 | char *value; |
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| 53 | }; |
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| 54 | |
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| 55 | struct vpd_write { |
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| 56 | char keyword[2]; |
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| 57 | char *value; |
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| 58 | int start; |
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| 59 | int len; |
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| 60 | }; |
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| 61 | |
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| 62 | struct pcicfg_vpd { |
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| 63 | uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */ |
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| 64 | char vpd_cached; |
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| 65 | char *vpd_ident; /* string identifier */ |
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| 66 | int vpd_rocnt; |
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| 67 | struct vpd_readonly *vpd_ros; |
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| 68 | int vpd_wcnt; |
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| 69 | struct vpd_write *vpd_w; |
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| 70 | }; |
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| 71 | |
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| 72 | /* Interesting values for PCI MSI */ |
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| 73 | struct pcicfg_msi { |
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| 74 | uint16_t msi_ctrl; /* Message Control */ |
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| 75 | uint8_t msi_location; /* Offset of MSI capability registers. */ |
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| 76 | uint8_t msi_msgnum; /* Number of messages */ |
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| 77 | int msi_alloc; /* Number of allocated messages. */ |
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| 78 | uint64_t msi_addr; /* Contents of address register. */ |
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| 79 | uint16_t msi_data; /* Contents of data register. */ |
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| 80 | u_int msi_handlers; |
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| 81 | }; |
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| 82 | |
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| 83 | /* Interesting values for PCI MSI-X */ |
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| 84 | struct msix_vector { |
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| 85 | uint64_t mv_address; /* Contents of address register. */ |
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| 86 | uint32_t mv_data; /* Contents of data register. */ |
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| 87 | int mv_irq; |
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| 88 | }; |
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| 89 | |
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| 90 | struct msix_table_entry { |
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| 91 | u_int mte_vector; /* 1-based index into msix_vectors array. */ |
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| 92 | u_int mte_handlers; |
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| 93 | }; |
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| 94 | |
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| 95 | struct pcicfg_msix { |
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| 96 | uint16_t msix_ctrl; /* Message Control */ |
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| 97 | uint16_t msix_msgnum; /* Number of messages */ |
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| 98 | uint8_t msix_location; /* Offset of MSI-X capability registers. */ |
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| 99 | uint8_t msix_table_bar; /* BAR containing vector table. */ |
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| 100 | uint8_t msix_pba_bar; /* BAR containing PBA. */ |
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| 101 | uint32_t msix_table_offset; |
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| 102 | uint32_t msix_pba_offset; |
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| 103 | int msix_alloc; /* Number of allocated vectors. */ |
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| 104 | int msix_table_len; /* Length of virtual table. */ |
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| 105 | struct msix_table_entry *msix_table; /* Virtual table. */ |
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| 106 | struct msix_vector *msix_vectors; /* Array of allocated vectors. */ |
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| 107 | struct resource *msix_table_res; /* Resource containing vector table. */ |
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| 108 | struct resource *msix_pba_res; /* Resource containing PBA. */ |
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| 109 | }; |
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| 110 | |
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| 111 | /* Interesting values for HyperTransport */ |
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| 112 | struct pcicfg_ht { |
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| 113 | uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */ |
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| 114 | uint16_t ht_msictrl; /* MSI mapping control */ |
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| 115 | uint64_t ht_msiaddr; /* MSI mapping base address */ |
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| 116 | }; |
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| 117 | |
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| 118 | /* config header information common to all header types */ |
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| 119 | typedef struct pcicfg { |
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| 120 | struct device *dev; /* device which owns this */ |
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| 121 | |
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| 122 | uint32_t bar[PCI_MAXMAPS_0]; /* BARs */ |
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| 123 | uint32_t bios; /* BIOS mapping */ |
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| 124 | |
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| 125 | uint16_t subvendor; /* card vendor ID */ |
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| 126 | uint16_t subdevice; /* card device ID, assigned by card vendor */ |
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| 127 | uint16_t vendor; /* chip vendor ID */ |
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| 128 | uint16_t device; /* chip device ID, assigned by chip vendor */ |
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| 129 | |
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| 130 | uint16_t cmdreg; /* disable/enable chip and PCI options */ |
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| 131 | uint16_t statreg; /* supported PCI features and error state */ |
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| 132 | |
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| 133 | uint8_t baseclass; /* chip PCI class */ |
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| 134 | uint8_t subclass; /* chip PCI subclass */ |
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| 135 | uint8_t progif; /* chip PCI programming interface */ |
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| 136 | uint8_t revid; /* chip revision ID */ |
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| 137 | |
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| 138 | uint8_t hdrtype; /* chip config header type */ |
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| 139 | uint8_t cachelnsz; /* cache line size in 4byte units */ |
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| 140 | uint8_t intpin; /* PCI interrupt pin */ |
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| 141 | uint8_t intline; /* interrupt line (IRQ for PC arch) */ |
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| 142 | |
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| 143 | uint8_t mingnt; /* min. useful bus grant time in 250ns units */ |
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| 144 | uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */ |
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| 145 | uint8_t lattimer; /* latency timer in units of 30ns bus cycles */ |
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| 146 | |
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| 147 | uint8_t mfdev; /* multi-function device (from hdrtype reg) */ |
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| 148 | uint8_t nummaps; /* actual number of PCI maps used */ |
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| 149 | |
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| 150 | uint32_t domain; /* PCI domain */ |
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| 151 | uint8_t bus; /* config space bus address */ |
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| 152 | uint8_t slot; /* config space slot address */ |
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| 153 | uint8_t func; /* config space function number */ |
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| 154 | |
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| 155 | struct pcicfg_pp pp; /* Power management */ |
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| 156 | struct pcicfg_vpd vpd; /* Vital product data */ |
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| 157 | struct pcicfg_msi msi; /* PCI MSI */ |
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| 158 | struct pcicfg_msix msix; /* PCI MSI-X */ |
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| 159 | struct pcicfg_ht ht; /* HyperTransport */ |
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| 160 | } pcicfgregs; |
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| 161 | |
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| 162 | /* additional type 1 device config header information (PCI to PCI bridge) */ |
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| 163 | |
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| 164 | #define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) |
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| 165 | #define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) |
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| 166 | #define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) |
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| 167 | #define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) |
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| 168 | |
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| 169 | typedef struct { |
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| 170 | pci_addr_t pmembase; /* base address of prefetchable memory */ |
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| 171 | pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ |
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| 172 | uint32_t membase; /* base address of memory window */ |
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| 173 | uint32_t memlimit; /* topmost address of memory window */ |
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| 174 | uint32_t iobase; /* base address of port window */ |
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| 175 | uint32_t iolimit; /* topmost address of port window */ |
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| 176 | uint16_t secstat; /* secondary bus status register */ |
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| 177 | uint16_t bridgectl; /* bridge control register */ |
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| 178 | uint8_t seclat; /* CardBus latency timer */ |
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| 179 | } pcih1cfgregs; |
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| 180 | |
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| 181 | /* additional type 2 device config header information (CardBus bridge) */ |
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| 182 | |
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| 183 | typedef struct { |
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| 184 | uint32_t membase0; /* base address of memory window */ |
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| 185 | uint32_t memlimit0; /* topmost address of memory window */ |
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| 186 | uint32_t membase1; /* base address of memory window */ |
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| 187 | uint32_t memlimit1; /* topmost address of memory window */ |
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| 188 | uint32_t iobase0; /* base address of port window */ |
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| 189 | uint32_t iolimit0; /* topmost address of port window */ |
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| 190 | uint32_t iobase1; /* base address of port window */ |
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| 191 | uint32_t iolimit1; /* topmost address of port window */ |
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| 192 | uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ |
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| 193 | uint16_t secstat; /* secondary bus status register */ |
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| 194 | uint16_t bridgectl; /* bridge control register */ |
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| 195 | uint8_t seclat; /* CardBus latency timer */ |
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| 196 | } pcih2cfgregs; |
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| 197 | |
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| 198 | extern uint32_t pci_numdevs; |
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| 199 | |
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| 200 | /* Only if the prerequisites are present */ |
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| 201 | #if defined(_SYS_BUS_HH_) && defined(_SYS_PCIIO_HH_) |
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| 202 | struct pci_devinfo { |
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| 203 | STAILQ_ENTRY(pci_devinfo) pci_links; |
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| 204 | struct resource_list resources; |
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| 205 | pcicfgregs cfg; |
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| 206 | struct pci_conf conf; |
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| 207 | }; |
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| 208 | #endif |
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| 209 | |
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| 210 | #ifdef _SYS_BUS_HH_ |
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| 211 | |
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| 212 | #include <freebsd/local/pci_if.h> |
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| 213 | |
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| 214 | enum pci_device_ivars { |
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| 215 | PCI_IVAR_SUBVENDOR, |
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| 216 | PCI_IVAR_SUBDEVICE, |
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| 217 | PCI_IVAR_VENDOR, |
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| 218 | PCI_IVAR_DEVICE, |
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| 219 | PCI_IVAR_DEVID, |
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| 220 | PCI_IVAR_CLASS, |
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| 221 | PCI_IVAR_SUBCLASS, |
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| 222 | PCI_IVAR_PROGIF, |
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| 223 | PCI_IVAR_REVID, |
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| 224 | PCI_IVAR_INTPIN, |
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| 225 | PCI_IVAR_IRQ, |
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| 226 | PCI_IVAR_DOMAIN, |
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| 227 | PCI_IVAR_BUS, |
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| 228 | PCI_IVAR_SLOT, |
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| 229 | PCI_IVAR_FUNCTION, |
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| 230 | PCI_IVAR_ETHADDR, |
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| 231 | PCI_IVAR_CMDREG, |
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| 232 | PCI_IVAR_CACHELNSZ, |
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| 233 | PCI_IVAR_MINGNT, |
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| 234 | PCI_IVAR_MAXLAT, |
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| 235 | PCI_IVAR_LATTIMER |
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| 236 | }; |
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| 237 | |
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| 238 | /* |
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| 239 | * Simplified accessors for pci devices |
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| 240 | */ |
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| 241 | #define PCI_ACCESSOR(var, ivar, type) \ |
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| 242 | __BUS_ACCESSOR(pci, var, PCI, ivar, type) |
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| 243 | |
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| 244 | PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t) |
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| 245 | PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t) |
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| 246 | PCI_ACCESSOR(vendor, VENDOR, uint16_t) |
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| 247 | PCI_ACCESSOR(device, DEVICE, uint16_t) |
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| 248 | PCI_ACCESSOR(devid, DEVID, uint32_t) |
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| 249 | PCI_ACCESSOR(class, CLASS, uint8_t) |
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| 250 | PCI_ACCESSOR(subclass, SUBCLASS, uint8_t) |
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| 251 | PCI_ACCESSOR(progif, PROGIF, uint8_t) |
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| 252 | PCI_ACCESSOR(revid, REVID, uint8_t) |
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| 253 | PCI_ACCESSOR(intpin, INTPIN, uint8_t) |
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| 254 | PCI_ACCESSOR(irq, IRQ, uint8_t) |
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| 255 | PCI_ACCESSOR(domain, DOMAIN, uint32_t) |
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| 256 | PCI_ACCESSOR(bus, BUS, uint8_t) |
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| 257 | PCI_ACCESSOR(slot, SLOT, uint8_t) |
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| 258 | PCI_ACCESSOR(function, FUNCTION, uint8_t) |
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| 259 | PCI_ACCESSOR(ether, ETHADDR, uint8_t *) |
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| 260 | PCI_ACCESSOR(cmdreg, CMDREG, uint8_t) |
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| 261 | PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t) |
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| 262 | PCI_ACCESSOR(mingnt, MINGNT, uint8_t) |
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| 263 | PCI_ACCESSOR(maxlat, MAXLAT, uint8_t) |
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| 264 | PCI_ACCESSOR(lattimer, LATTIMER, uint8_t) |
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| 265 | |
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| 266 | #undef PCI_ACCESSOR |
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| 267 | |
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| 268 | /* |
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| 269 | * Operations on configuration space. |
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| 270 | */ |
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| 271 | static __inline uint32_t |
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| 272 | pci_read_config(device_t dev, int reg, int width) |
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| 273 | { |
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| 274 | return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); |
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| 275 | } |
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| 276 | |
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| 277 | static __inline void |
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| 278 | pci_write_config(device_t dev, int reg, uint32_t val, int width) |
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| 279 | { |
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| 280 | PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); |
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| 281 | } |
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| 282 | |
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| 283 | /* |
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| 284 | * Ivars for pci bridges. |
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| 285 | */ |
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| 286 | |
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| 287 | /*typedef enum pci_device_ivars pcib_device_ivars;*/ |
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| 288 | enum pcib_device_ivars { |
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| 289 | PCIB_IVAR_DOMAIN, |
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| 290 | PCIB_IVAR_BUS |
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| 291 | }; |
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| 292 | |
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| 293 | #define PCIB_ACCESSOR(var, ivar, type) \ |
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| 294 | __BUS_ACCESSOR(pcib, var, PCIB, ivar, type) |
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| 295 | |
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| 296 | PCIB_ACCESSOR(domain, DOMAIN, uint32_t) |
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| 297 | PCIB_ACCESSOR(bus, BUS, uint32_t) |
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| 298 | |
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| 299 | #undef PCIB_ACCESSOR |
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| 300 | |
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| 301 | /* |
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| 302 | * PCI interrupt validation. Invalid interrupt values such as 0 or 128 |
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| 303 | * on i386 or other platforms should be mapped out in the MD pcireadconf |
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| 304 | * code and not here, since the only MI invalid IRQ is 255. |
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| 305 | */ |
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| 306 | #define PCI_INVALID_IRQ 255 |
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| 307 | #define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ) |
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| 308 | |
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| 309 | |
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| 310 | /* |
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| 311 | * Convenience functions. |
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| 312 | * |
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| 313 | * These should be used in preference to manually manipulating |
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| 314 | * configuration space. |
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| 315 | */ |
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| 316 | static __inline int |
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| 317 | pci_enable_busmaster(device_t dev) |
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| 318 | { |
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| 319 | return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev)); |
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| 320 | } |
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| 321 | |
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| 322 | #ifndef __rtems__ |
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| 323 | static __inline int |
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| 324 | pci_disable_busmaster(device_t dev) |
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| 325 | { |
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| 326 | return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev)); |
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| 327 | } |
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| 328 | |
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| 329 | static __inline int |
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| 330 | pci_enable_io(device_t dev, int space) |
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| 331 | { |
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| 332 | return(PCI_ENABLE_IO(device_get_parent(dev), dev, space)); |
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| 333 | } |
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| 334 | |
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| 335 | static __inline int |
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| 336 | pci_disable_io(device_t dev, int space) |
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| 337 | { |
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| 338 | return(PCI_DISABLE_IO(device_get_parent(dev), dev, space)); |
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| 339 | } |
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| 340 | |
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| 341 | static __inline int |
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| 342 | pci_get_vpd_ident(device_t dev, const char **identptr) |
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| 343 | { |
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| 344 | return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr)); |
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| 345 | } |
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| 346 | |
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| 347 | static __inline int |
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| 348 | pci_get_vpd_readonly(device_t dev, const char *kw, const char **identptr) |
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| 349 | { |
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| 350 | return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, identptr)); |
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| 351 | } |
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| 352 | #endif /* __rtems__ */ |
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| 353 | |
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| 354 | /* |
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| 355 | * Check if the address range falls within the VGA defined address range(s) |
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| 356 | */ |
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| 357 | static __inline int |
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| 358 | pci_is_vga_ioport_range(u_long start, u_long end) |
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| 359 | { |
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| 360 | |
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| 361 | return (((start >= 0x3b0 && end <= 0x3bb) || |
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| 362 | (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0); |
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| 363 | } |
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| 364 | |
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| 365 | static __inline int |
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| 366 | pci_is_vga_memory_range(u_long start, u_long end) |
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| 367 | { |
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| 368 | |
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| 369 | return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0); |
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| 370 | } |
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| 371 | |
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| 372 | /* |
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| 373 | * PCI power states are as defined by ACPI: |
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| 374 | * |
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| 375 | * D0 State in which device is on and running. It is receiving full |
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| 376 | * power from the system and delivering full functionality to the user. |
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| 377 | * D1 Class-specific low-power state in which device context may or may not |
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| 378 | * be lost. Buses in D1 cannot do anything to the bus that would force |
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| 379 | * devices on that bus to lose context. |
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| 380 | * D2 Class-specific low-power state in which device context may or may |
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| 381 | * not be lost. Attains greater power savings than D1. Buses in D2 |
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| 382 | * can cause devices on that bus to lose some context. Devices in D2 |
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| 383 | * must be prepared for the bus to be in D2 or higher. |
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| 384 | * D3 State in which the device is off and not running. Device context is |
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| 385 | * lost. Power can be removed from the device. |
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| 386 | */ |
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| 387 | #define PCI_POWERSTATE_D0 0 |
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| 388 | #define PCI_POWERSTATE_D1 1 |
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| 389 | #define PCI_POWERSTATE_D2 2 |
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| 390 | #define PCI_POWERSTATE_D3 3 |
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| 391 | #define PCI_POWERSTATE_UNKNOWN -1 |
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| 392 | |
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| 393 | static __inline int |
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| 394 | pci_set_powerstate(device_t dev, int state) |
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| 395 | { |
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| 396 | return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state); |
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| 397 | } |
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| 398 | |
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| 399 | static __inline int |
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| 400 | pci_get_powerstate(device_t dev) |
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| 401 | { |
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| 402 | return PCI_GET_POWERSTATE(device_get_parent(dev), dev); |
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| 403 | } |
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| 404 | |
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| 405 | static __inline int |
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| 406 | pci_find_extcap(device_t dev, int capability, int *capreg) |
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| 407 | { |
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| 408 | return PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg); |
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| 409 | } |
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| 410 | |
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| 411 | static __inline int |
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| 412 | pci_alloc_msi(device_t dev, int *count) |
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| 413 | { |
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| 414 | return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count)); |
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| 415 | } |
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| 416 | |
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| 417 | static __inline int |
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| 418 | pci_alloc_msix(device_t dev, int *count) |
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| 419 | { |
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| 420 | return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count)); |
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| 421 | } |
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| 422 | |
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| 423 | static __inline int |
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| 424 | pci_remap_msix(device_t dev, int count, const u_int *vectors) |
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| 425 | { |
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| 426 | return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors)); |
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| 427 | } |
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| 428 | |
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| 429 | static __inline int |
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| 430 | pci_release_msi(device_t dev) |
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| 431 | { |
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| 432 | return (PCI_RELEASE_MSI(device_get_parent(dev), dev)); |
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| 433 | } |
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| 434 | |
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| 435 | static __inline int |
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| 436 | pci_msi_count(device_t dev) |
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| 437 | { |
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| 438 | return (PCI_MSI_COUNT(device_get_parent(dev), dev)); |
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| 439 | } |
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| 440 | |
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| 441 | static __inline int |
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| 442 | pci_msix_count(device_t dev) |
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| 443 | { |
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| 444 | return (PCI_MSIX_COUNT(device_get_parent(dev), dev)); |
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| 445 | } |
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| 446 | |
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| 447 | device_t pci_find_bsf(uint8_t, uint8_t, uint8_t); |
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| 448 | device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t); |
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| 449 | #ifndef __rtems__ |
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| 450 | device_t pci_find_device(uint16_t, uint16_t); |
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| 451 | #endif /* __rtems__ */ |
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| 452 | |
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| 453 | /* Can be used by drivers to manage the MSI-X table. */ |
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| 454 | int pci_pending_msix(device_t dev, u_int index); |
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| 455 | |
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| 456 | int pci_msi_device_blacklisted(device_t dev); |
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| 457 | |
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| 458 | void pci_ht_map_msi(device_t dev, uint64_t addr); |
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| 459 | |
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| 460 | int pci_get_max_read_req(device_t dev); |
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| 461 | int pci_set_max_read_req(device_t dev, int size); |
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| 462 | |
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| 463 | #endif /* _SYS_BUS_HH_ */ |
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| 464 | |
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| 465 | /* |
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| 466 | * cdev switch for control device, initialised in generic PCI code |
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| 467 | */ |
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| 468 | extern struct cdevsw pcicdev; |
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| 469 | |
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| 470 | /* |
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| 471 | * List of all PCI devices, generation count for the list. |
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| 472 | */ |
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| 473 | STAILQ_HEAD(devlist, pci_devinfo); |
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| 474 | |
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| 475 | extern struct devlist pci_devq; |
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| 476 | extern uint32_t pci_generation; |
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| 477 | |
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| 478 | #endif /* _PCIVAR_HH_ */ |
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