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source: rtems-libbsd/freebsd/dev/fxp/if_fxp.c @ 4f8495e

4.1155-freebsd-126-freebsd-12freebsd-9.3

Last change on this file since 4f8495e was 4f8495e, checked in by Joel Sherrill <joel.sherrill@…>, on 07/09/12 at 19:32:34
FXP: Remove hack and use hint provided by application
Property mode set to `100644`
File size: 91.8 KB

Line
1	#include <freebsd/machine/rtems-bsd-config.h>
2
3	/*-
4	* Copyright (c) 1995, David Greenman
5	* Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
6	* All rights reserved.
7	*
8	* Redistribution and use in source and binary forms, with or without
9	* modification, are permitted provided that the following conditions
10	* are met:
11	* 1. Redistributions of source code must retain the above copyright
12	* notice unmodified, this list of conditions, and the following
13	* disclaimer.
14	* 2. Redistributions in binary form must reproduce the above copyright
15	* notice, this list of conditions and the following disclaimer in the
16	* documentation and/or other materials provided with the distribution.
17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28	* SUCH DAMAGE.
29	*
30	*/
31
32	#include <freebsd/sys/cdefs.h>
33	__FBSDID("$FreeBSD$");
34
35	/*
36	* Intel EtherExpress Pro/100B PCI Fast Ethernet driver
37	*/
38
39	#ifdef HAVE_KERNEL_OPTION_HEADERS
40	#include <freebsd/local/opt_device_polling.h>
41	#endif
42
43	#include <freebsd/sys/param.h>
44	#include <freebsd/sys/systm.h>
45	#include <freebsd/sys/bus.h>
46	#include <freebsd/sys/endian.h>
47	#include <freebsd/sys/kernel.h>
48	#include <freebsd/sys/mbuf.h>
49	#include <freebsd/sys/lock.h>
50	#include <freebsd/sys/module.h>
51	#include <freebsd/sys/mutex.h>
52	#include <freebsd/sys/rman.h>
53	#include <freebsd/sys/socket.h>
54	#include <freebsd/sys/sockio.h>
55	#include <freebsd/sys/sysctl.h>
56
57	#include <freebsd/net/bpf.h>
58	#include <freebsd/net/ethernet.h>
59	#include <freebsd/net/if.h>
60	#include <freebsd/net/if_arp.h>
61	#include <freebsd/net/if_dl.h>
62	#include <freebsd/net/if_media.h>
63	#include <freebsd/net/if_types.h>
64	#include <freebsd/net/if_vlan_var.h>
65
66	#include <freebsd/netinet/in.h>
67	#include <freebsd/netinet/in_systm.h>
68	#include <freebsd/netinet/ip.h>
69	#include <freebsd/netinet/tcp.h>
70	#include <freebsd/netinet/udp.h>
71
72	#include <freebsd/machine/bus.h>
73	#include <freebsd/machine/in_cksum.h>
74	#include <freebsd/machine/resource.h>
75
76	#include <freebsd/dev/pci/pcivar.h>
77	#include <freebsd/dev/pci/pcireg.h> /* for PCIM_CMD_xxx */
78
79	#include <freebsd/dev/mii/mii.h>
80	#include <freebsd/dev/mii/miivar.h>
81
82	#include <freebsd/dev/fxp/if_fxpreg.h>
83	#include <freebsd/dev/fxp/if_fxpvar.h>
84	#include <freebsd/dev/fxp/rcvbundl.h>
85
86	MODULE_DEPEND(fxp, pci, 1, 1, 1);
87	MODULE_DEPEND(fxp, ether, 1, 1, 1);
88	MODULE_DEPEND(fxp, miibus, 1, 1, 1);
89	#include <freebsd/local/miibus_if.h>
90
91	/*
92	* NOTE! On the Alpha, we have an alignment constraint. The
93	* card DMAs the packet immediately following the RFA. However,
94	* the first thing in the packet is a 14-byte Ethernet header.
95	* This means that the packet is misaligned. To compensate,
96	* we actually offset the RFA 2 bytes into the cluster. This
97	* alignes the packet after the Ethernet header at a 32-bit
98	* boundary. HOWEVER! This means that the RFA is misaligned!
99	*/
100	#define RFA_ALIGNMENT_FUDGE 2
101
102	/*
103	* Set initial transmit threshold at 64 (512 bytes). This is
104	* increased by 64 (512 bytes) at a time, to maximum of 192
105	* (1536 bytes), if an underrun occurs.
106	*/
107	static int tx_threshold = 64;
108
109	/*
110	* The configuration byte map has several undefined fields which
111	* must be one or must be zero. Set up a template for these bits.
112	* The actual configuration is performed in fxp_init_body.
113	*
114	* See struct fxp_cb_config for the bit definitions.
115	*/
116	static const u_char const fxp_cb_config_template[] = {
117	0x0, 0x0, /* cb_status */
118	0x0, 0x0, /* cb_command */
119	0x0, 0x0, 0x0, 0x0, /* link_addr */
120	0x0, /* 0 */
121	0x0, /* 1 */
122	0x0, /* 2 */
123	0x0, /* 3 */
124	0x0, /* 4 */
125	0x0, /* 5 */
126	0x32, /* 6 */
127	0x0, /* 7 */
128	0x0, /* 8 */
129	0x0, /* 9 */
130	0x6, /* 10 */
131	0x0, /* 11 */
132	0x0, /* 12 */
133	0x0, /* 13 */
134	0xf2, /* 14 */
135	0x48, /* 15 */
136	0x0, /* 16 */
137	0x40, /* 17 */
138	0xf0, /* 18 */
139	0x0, /* 19 */
140	0x3f, /* 20 */
141	0x5, /* 21 */
142	0x0, /* 22 */
143	0x0, /* 23 */
144	0x0, /* 24 */
145	0x0, /* 25 */
146	0x0, /* 26 */
147	0x0, /* 27 */
148	0x0, /* 28 */
149	0x0, /* 29 */
150	0x0, /* 30 */
151	0x0 /* 31 */
152	};
153
154	/*
155	* Claim various Intel PCI device identifiers for this driver. The
156	* sub-vendor and sub-device field are extensively used to identify
157	* particular variants, but we don't currently differentiate between
158	* them.
159	*/
160	static const struct fxp_ident const fxp_ident_table[] = {
161	{ 0x1029, -1, 0, "Intel 82559 PCI/CardBus Pro/100" },
162	{ 0x1030, -1, 0, "Intel 82559 Pro/100 Ethernet" },
163	{ 0x1031, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
164	{ 0x1032, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
165	{ 0x1033, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
166	{ 0x1034, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
167	{ 0x1035, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
168	{ 0x1036, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
169	{ 0x1037, -1, 3, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
170	{ 0x1038, -1, 3, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
171	{ 0x1039, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
172	{ 0x103A, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
173	{ 0x103B, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
174	{ 0x103C, -1, 4, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
175	{ 0x103D, -1, 4, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
176	{ 0x103E, -1, 4, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
177	{ 0x1050, -1, 5, "Intel 82801BA (D865) Pro/100 VE Ethernet" },
178	{ 0x1051, -1, 5, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" },
179	{ 0x1059, -1, 0, "Intel 82551QM Pro/100 M Mobile Connection" },
180	{ 0x1064, -1, 6, "Intel 82562EZ (ICH6)" },
181	{ 0x1065, -1, 6, "Intel 82562ET/EZ/GT/GZ PRO/100 VE Ethernet" },
182	{ 0x1068, -1, 6, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" },
183	{ 0x1069, -1, 6, "Intel 82562EM/EX/GX Pro/100 Ethernet" },
184	{ 0x1091, -1, 7, "Intel 82562GX Pro/100 Ethernet" },
185	{ 0x1092, -1, 7, "Intel Pro/100 VE Network Connection" },
186	{ 0x1093, -1, 7, "Intel Pro/100 VM Network Connection" },
187	{ 0x1094, -1, 7, "Intel Pro/100 946GZ (ICH7) Network Connection" },
188	{ 0x1209, -1, 0, "Intel 82559ER Embedded 10/100 Ethernet" },
189	{ 0x1229, 0x01, 0, "Intel 82557 Pro/100 Ethernet" },
190	{ 0x1229, 0x02, 0, "Intel 82557 Pro/100 Ethernet" },
191	{ 0x1229, 0x03, 0, "Intel 82557 Pro/100 Ethernet" },
192	{ 0x1229, 0x04, 0, "Intel 82558 Pro/100 Ethernet" },
193	{ 0x1229, 0x05, 0, "Intel 82558 Pro/100 Ethernet" },
194	{ 0x1229, 0x06, 0, "Intel 82559 Pro/100 Ethernet" },
195	{ 0x1229, 0x07, 0, "Intel 82559 Pro/100 Ethernet" },
196	{ 0x1229, 0x08, 0, "Intel 82559 Pro/100 Ethernet" },
197	{ 0x1229, 0x09, 0, "Intel 82559ER Pro/100 Ethernet" },
198	{ 0x1229, 0x0c, 0, "Intel 82550 Pro/100 Ethernet" },
199	{ 0x1229, 0x0d, 0, "Intel 82550 Pro/100 Ethernet" },
200	{ 0x1229, 0x0e, 0, "Intel 82550 Pro/100 Ethernet" },
201	{ 0x1229, 0x0f, 0, "Intel 82551 Pro/100 Ethernet" },
202	{ 0x1229, 0x10, 0, "Intel 82551 Pro/100 Ethernet" },
203	{ 0x1229, -1, 0, "Intel 82557/8/9 Pro/100 Ethernet" },
204	{ 0x2449, -1, 2, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" },
205	{ 0x27dc, -1, 7, "Intel 82801GB (ICH7) 10/100 Ethernet" },
206	{ 0, -1, 0, NULL },
207	};
208
209	#ifdef FXP_IP_CSUM_WAR
210	#define FXP_CSUM_FEATURES (CSUM_IP \| CSUM_TCP \| CSUM_UDP)
211	#else
212	#define FXP_CSUM_FEATURES (CSUM_TCP \| CSUM_UDP)
213	#endif
214
215	static int fxp_probe(device_t dev);
216	static int fxp_attach(device_t dev);
217	static int fxp_detach(device_t dev);
218	static int fxp_shutdown(device_t dev);
219	static int fxp_suspend(device_t dev);
220	static int fxp_resume(device_t dev);
221
222	static const struct fxp_ident *fxp_find_ident(device_t dev);
223	static void fxp_intr(void *xsc);
224	static void fxp_rxcsum(struct fxp_softc sc, struct ifnet ifp,
225	struct mbuf *m, uint16_t status, int pos);
226	static int fxp_intr_body(struct fxp_softc sc, struct ifnet ifp,
227	uint8_t statack, int count);
228	static void fxp_init(void *xsc);
229	static void fxp_init_body(struct fxp_softc *sc, int);
230	static void fxp_tick(void *xsc);
231	static void fxp_start(struct ifnet *ifp);
232	static void fxp_start_body(struct ifnet *ifp);
233	static int fxp_encap(struct fxp_softc sc, struct mbuf *m_head);
234	static void fxp_txeof(struct fxp_softc *sc);
235	static void fxp_stop(struct fxp_softc *sc);
236	static void fxp_release(struct fxp_softc *sc);
237	static int fxp_ioctl(struct ifnet *ifp, u_long command,
238	caddr_t data);
239	static void fxp_watchdog(struct fxp_softc *sc);
240	static void fxp_add_rfabuf(struct fxp_softc *sc,
241	struct fxp_rx *rxp);
242	static void fxp_discard_rfabuf(struct fxp_softc *sc,
243	struct fxp_rx *rxp);
244	static int fxp_new_rfabuf(struct fxp_softc *sc,
245	struct fxp_rx *rxp);
246	static int fxp_mc_addrs(struct fxp_softc *sc);
247	static void fxp_mc_setup(struct fxp_softc *sc);
248	static uint16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset,
249	int autosize);
250	static void fxp_eeprom_putword(struct fxp_softc *sc, int offset,
251	uint16_t data);
252	static void fxp_autosize_eeprom(struct fxp_softc *sc);
253	static void fxp_read_eeprom(struct fxp_softc sc, u_short data,
254	int offset, int words);
255	static void fxp_write_eeprom(struct fxp_softc sc, u_short data,
256	int offset, int words);
257	static int fxp_ifmedia_upd(struct ifnet *ifp);
258	static void fxp_ifmedia_sts(struct ifnet *ifp,
259	struct ifmediareq *ifmr);
260	static int fxp_serial_ifmedia_upd(struct ifnet *ifp);
261	static void fxp_serial_ifmedia_sts(struct ifnet *ifp,
262	struct ifmediareq *ifmr);
263	static int fxp_miibus_readreg(device_t dev, int phy, int reg);
264	static int fxp_miibus_writereg(device_t dev, int phy, int reg,
265	int value);
266	static void fxp_miibus_statchg(device_t dev);
267	static void fxp_load_ucode(struct fxp_softc *sc);
268	static void fxp_update_stats(struct fxp_softc *sc);
269	static void fxp_sysctl_node(struct fxp_softc *sc);
270	static int sysctl_int_range(SYSCTL_HANDLER_ARGS,
271	int low, int high);
272	static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS);
273	static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS);
274	static void fxp_scb_wait(struct fxp_softc *sc);
275	static void fxp_scb_cmd(struct fxp_softc *sc, int cmd);
276	static void fxp_dma_wait(struct fxp_softc *sc,
277	volatile uint16_t *status, bus_dma_tag_t dmat,
278	bus_dmamap_t map);
279
280	static device_method_t fxp_methods[] = {
281	/* Device interface */
282	DEVMETHOD(device_probe, fxp_probe),
283	DEVMETHOD(device_attach, fxp_attach),
284	DEVMETHOD(device_detach, fxp_detach),
285	DEVMETHOD(device_shutdown, fxp_shutdown),
286	DEVMETHOD(device_suspend, fxp_suspend),
287	DEVMETHOD(device_resume, fxp_resume),
288
289	/* MII interface */
290	DEVMETHOD(miibus_readreg, fxp_miibus_readreg),
291	DEVMETHOD(miibus_writereg, fxp_miibus_writereg),
292	DEVMETHOD(miibus_statchg, fxp_miibus_statchg),
293
294	{ 0, 0 }
295	};
296
297	static driver_t fxp_driver = {
298	"fxp",
299	fxp_methods,
300	sizeof(struct fxp_softc),
301	};
302
303	static devclass_t fxp_devclass;
304
305	DRIVER_MODULE(fxp, pci, fxp_driver, fxp_devclass, 0, 0);
306	DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0);
307
308	static struct resource_spec fxp_res_spec_mem[] = {
309	{ SYS_RES_MEMORY, FXP_PCI_MMBA, RF_ACTIVE },
310	{ SYS_RES_IRQ, 0, RF_ACTIVE \| RF_SHAREABLE },
311	{ -1, 0 }
312	};
313
314	static struct resource_spec fxp_res_spec_io[] = {
315	{ SYS_RES_IOPORT, FXP_PCI_IOBA, RF_ACTIVE },
316	{ SYS_RES_IRQ, 0, RF_ACTIVE \| RF_SHAREABLE },
317	{ -1, 0 }
318	};
319
320	/*
321	* Wait for the previous command to be accepted (but not necessarily
322	* completed).
323	*/
324	static void
325	fxp_scb_wait(struct fxp_softc *sc)
326	{
327	union {
328	uint16_t w;
329	uint8_t b[2];
330	} flowctl;
331	int i = 10000;
332
333	while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
334	DELAY(2);
335	if (i == 0) {
336	flowctl.b[0] = CSR_READ_1(sc, FXP_CSR_FC_THRESH);
337	flowctl.b[1] = CSR_READ_1(sc, FXP_CSR_FC_STATUS);
338	device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
339	CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
340	CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
341	CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), flowctl.w);
342	}
343	}
344
345	static void
346	fxp_scb_cmd(struct fxp_softc *sc, int cmd)
347	{
348
349	if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
350	CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
351	fxp_scb_wait(sc);
352	}
353	CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
354	}
355
356	static void
357	fxp_dma_wait(struct fxp_softc sc, volatile uint16_t status,
358	bus_dma_tag_t dmat, bus_dmamap_t map)
359	{
360	int i;
361
362	for (i = 10000; i > 0; i--) {
363	DELAY(2);
364	bus_dmamap_sync(dmat, map,
365	BUS_DMASYNC_POSTREAD \| BUS_DMASYNC_POSTWRITE);
366	if ((le16toh(*status) & FXP_CB_STATUS_C) != 0)
367	break;
368	}
369	if (i == 0)
370	device_printf(sc->dev, "DMA timeout\n");
371	}
372
373	static const struct fxp_ident *
374	fxp_find_ident(device_t dev)
375	{
376	uint16_t devid;
377	uint8_t revid;
378	const struct fxp_ident *ident;
379
380	if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) {
381	devid = pci_get_device(dev);
382	revid = pci_get_revid(dev);
383	for (ident = fxp_ident_table; ident->name != NULL; ident++) {
384	if (ident->devid == devid &&
385	(ident->revid == revid \|\| ident->revid == -1)) {
386	return (ident);
387	}
388	}
389	}
390	return (NULL);
391	}
392
393	/*
394	* Return identification string if this device is ours.
395	*/
396	static int
397	fxp_probe(device_t dev)
398	{
399	const struct fxp_ident *ident;
400
401	ident = fxp_find_ident(dev);
402	if (ident != NULL) {
403	device_set_desc(dev, ident->name);
404	return (BUS_PROBE_DEFAULT);
405	}
406	return (ENXIO);
407	}
408
409	static void
410	fxp_dma_map_addr(void arg, bus_dma_segment_t segs, int nseg, int error)
411	{
412	uint32_t *addr;
413
414	if (error)
415	return;
416
417	KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
418	addr = arg;
419	*addr = segs->ds_addr;
420	}
421
422	static int
423	fxp_attach(device_t dev)
424	{
425	struct fxp_softc *sc;
426	struct fxp_cb_tx *tcbp;
427	struct fxp_tx *txp;
428	struct fxp_rx *rxp;
429	struct ifnet *ifp;
430	uint32_t val;
431	uint16_t data, myea[ETHER_ADDR_LEN / 2];
432	u_char eaddr[ETHER_ADDR_LEN];
433	int error, flags, i, pmc, prefer_iomap;
434
435	error = 0;
436	sc = device_get_softc(dev);
437	sc->dev = dev;
438	mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
439	MTX_DEF);
440	callout_init_mtx(&sc->stat_ch, &sc->sc_mtx, 0);
441	ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
442	fxp_serial_ifmedia_sts);
443
444	ifp = sc->ifp = if_alloc(IFT_ETHER);
445	if (ifp == NULL) {
446	device_printf(dev, "can not if_alloc()\n");
447	error = ENOSPC;
448	goto fail;
449	}
450
451	/*
452	* Enable bus mastering.
453	*/
454	pci_enable_busmaster(dev);
455	val = pci_read_config(dev, PCIR_COMMAND, 2);
456
457	/*
458	* Figure out which we should try first - memory mapping or i/o mapping?
459	* We default to memory mapping. Then we accept an override from the
460	* command line. Then we check to see which one is enabled.
461	*/
462	prefer_iomap = 0;
463	resource_int_value(device_get_name(dev), device_get_unit(dev),
464	"prefer_iomap", &prefer_iomap);
465	if (prefer_iomap)
466	sc->fxp_spec = fxp_res_spec_io;
467	else
468	sc->fxp_spec = fxp_res_spec_mem;
469
470	error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res);
471	if (error) {
472	if (sc->fxp_spec == fxp_res_spec_mem)
473	sc->fxp_spec = fxp_res_spec_io;
474	else
475	sc->fxp_spec = fxp_res_spec_mem;
476	error = bus_alloc_resources(dev, sc->fxp_spec, sc->fxp_res);
477	}
478	if (error) {
479	device_printf(dev, "could not allocate resources\n");
480	error = ENXIO;
481	goto fail;
482	}
483
484	if (bootverbose) {
485	device_printf(dev, "using %s space register mapping\n",
486	sc->fxp_spec == fxp_res_spec_mem ? "memory" : "I/O");
487	}
488
489	/*
490	* Put CU/RU idle state and prepare full reset.
491	*/
492	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
493	DELAY(10);
494	/* Full reset and disable interrupts. */
495	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
496	DELAY(10);
497	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
498
499	/*
500	* Find out how large of an SEEPROM we have.
501	*/
502	fxp_autosize_eeprom(sc);
503
504	/*
505	* Find out the chip revision; lump all 82557 revs together.
506	*/
507	sc->ident = fxp_find_ident(dev);
508	if (sc->ident->ich > 0) {
509	/* Assume ICH controllers are 82559. */
510	sc->revision = FXP_REV_82559_A0;
511	} else {
512	fxp_read_eeprom(sc, &data, 5, 1);
513	if ((data >> 8) == 1)
514	sc->revision = FXP_REV_82557;
515	else
516	sc->revision = pci_get_revid(dev);
517	}
518
519	/*
520	* Check availability of WOL. 82559ER does not support WOL.
521	*/
522	if (sc->revision >= FXP_REV_82558_A4 &&
523	sc->revision != FXP_REV_82559S_A) {
524	fxp_read_eeprom(sc, &data, 10, 1);
525	if ((data & 0x20) != 0 &&
526	pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0)
527	sc->flags \|= FXP_FLAG_WOLCAP;
528	}
529
530	/* Receiver lock-up workaround detection. */
531	if (sc->revision < FXP_REV_82558_A4) {
532	fxp_read_eeprom(sc, &data, 3, 1);
533	if ((data & 0x03) != 0x03) {
534	sc->flags \|= FXP_FLAG_RXBUG;
535	device_printf(dev, "Enabling Rx lock-up workaround\n");
536	}
537	}
538
539	/*
540	* Determine whether we must use the 503 serial interface.
541	*/
542	fxp_read_eeprom(sc, &data, 6, 1);
543	if (sc->revision == FXP_REV_82557 && (data & FXP_PHY_DEVICE_MASK) != 0
544	&& (data & FXP_PHY_SERIAL_ONLY))
545	sc->flags \|= FXP_FLAG_SERIAL_MEDIA;
546
547	fxp_sysctl_node(sc);
548	/*
549	* Enable workarounds for certain chip revision deficiencies.
550	*
551	* Systems based on the ICH2/ICH2-M chip from Intel, and possibly
552	* some systems based a normal 82559 design, have a defect where
553	* the chip can cause a PCI protocol violation if it receives
554	* a CU_RESUME command when it is entering the IDLE state. The
555	* workaround is to disable Dynamic Standby Mode, so the chip never
556	* deasserts CLKRUN#, and always remains in an active state.
557	*
558	* See Intel 82801BA/82801BAM Specification Update, Errata #30.
559	*/
560	if ((sc->ident->ich >= 2 && sc->ident->ich <= 3) \|\|
561	(sc->ident->ich == 0 && sc->revision >= FXP_REV_82559_A0)) {
562	fxp_read_eeprom(sc, &data, 10, 1);
563	if (data & 0x02) { /* STB enable */
564	uint16_t cksum;
565	int i;
566
567	device_printf(dev,
568	"Disabling dynamic standby mode in EEPROM\n");
569	data &= ~0x02;
570	fxp_write_eeprom(sc, &data, 10, 1);
571	device_printf(dev, "New EEPROM ID: 0x%x\n", data);
572	cksum = 0;
573	for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) {
574	fxp_read_eeprom(sc, &data, i, 1);
575	cksum += data;
576	}
577	i = (1 << sc->eeprom_size) - 1;
578	cksum = 0xBABA - cksum;
579	fxp_read_eeprom(sc, &data, i, 1);
580	fxp_write_eeprom(sc, &cksum, i, 1);
581	device_printf(dev,
582	"EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
583	i, data, cksum);
584	#if 1
585	/*
586	* If the user elects to continue, try the software
587	* workaround, as it is better than nothing.
588	*/
589	sc->flags \|= FXP_FLAG_CU_RESUME_BUG;
590	#endif
591	}
592	}
593
594	/*
595	* If we are not a 82557 chip, we can enable extended features.
596	*/
597	if (sc->revision != FXP_REV_82557) {
598	/*
599	* If MWI is enabled in the PCI configuration, and there
600	* is a valid cacheline size (8 or 16 dwords), then tell
601	* the board to turn on MWI.
602	*/
603	if (val & PCIM_CMD_MWRICEN &&
604	pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
605	sc->flags \|= FXP_FLAG_MWI_ENABLE;
606
607	/* turn on the extended TxCB feature */
608	sc->flags \|= FXP_FLAG_EXT_TXCB;
609
610	/* enable reception of long frames for VLAN */
611	sc->flags \|= FXP_FLAG_LONG_PKT_EN;
612	} else {
613	/* a hack to get long VLAN frames on a 82557 */
614	sc->flags \|= FXP_FLAG_SAVE_BAD;
615	}
616
617	/* For 82559 or later chips, Rx checksum offload is supported. */
618	if (sc->revision >= FXP_REV_82559_A0) {
619	/* 82559ER does not support Rx checksum offloading. */
620	if (sc->ident->devid != 0x1209)
621	sc->flags \|= FXP_FLAG_82559_RXCSUM;
622	}
623	/*
624	* Enable use of extended RFDs and TCBs for 82550
625	* and later chips. Note: we need extended TXCB support
626	* too, but that's already enabled by the code above.
627	* Be careful to do this only on the right devices.
628	*/
629	if (sc->revision == FXP_REV_82550 \|\| sc->revision == FXP_REV_82550_C \|\|
630	sc->revision == FXP_REV_82551_E \|\| sc->revision == FXP_REV_82551_F
631	\|\| sc->revision == FXP_REV_82551_10) {
632	sc->rfa_size = sizeof (struct fxp_rfa);
633	sc->tx_cmd = FXP_CB_COMMAND_IPCBXMIT;
634	sc->flags \|= FXP_FLAG_EXT_RFA;
635	/* Use extended RFA instead of 82559 checksum mode. */
636	sc->flags &= ~FXP_FLAG_82559_RXCSUM;
637	} else {
638	sc->rfa_size = sizeof (struct fxp_rfa) - FXP_RFAX_LEN;
639	sc->tx_cmd = FXP_CB_COMMAND_XMIT;
640	}
641
642	/*
643	* Allocate DMA tags and DMA safe memory.
644	*/
645	sc->maxtxseg = FXP_NTXSEG;
646	sc->maxsegsize = MCLBYTES;
647	if (sc->flags & FXP_FLAG_EXT_RFA) {
648	sc->maxtxseg--;
649	sc->maxsegsize = FXP_TSO_SEGSIZE;
650	}
651	error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
652	BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
653	sc->maxsegsize * sc->maxtxseg + sizeof(struct ether_vlan_header),
654	sc->maxtxseg, sc->maxsegsize, 0,
655	busdma_lock_mutex, &Giant, &sc->fxp_txmtag);
656	if (error) {
657	device_printf(dev, "could not create TX DMA tag\n");
658	goto fail;
659	}
660
661	error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
662	BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
663	MCLBYTES, 1, MCLBYTES, 0,
664	busdma_lock_mutex, &Giant, &sc->fxp_rxmtag);
665	if (error) {
666	device_printf(dev, "could not create RX DMA tag\n");
667	goto fail;
668	}
669
670	error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
671	BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
672	sizeof(struct fxp_stats), 1, sizeof(struct fxp_stats), 0,
673	busdma_lock_mutex, &Giant, &sc->fxp_stag);
674	if (error) {
675	device_printf(dev, "could not create stats DMA tag\n");
676	goto fail;
677	}
678
679	error = bus_dmamem_alloc(sc->fxp_stag, (void **)&sc->fxp_stats,
680	BUS_DMA_NOWAIT \| BUS_DMA_ZERO, &sc->fxp_smap);
681	if (error) {
682	device_printf(dev, "could not allocate stats DMA memory\n");
683	goto fail;
684	}
685	error = bus_dmamap_load(sc->fxp_stag, sc->fxp_smap, sc->fxp_stats,
686	sizeof(struct fxp_stats), fxp_dma_map_addr, &sc->stats_addr, 0);
687	if (error) {
688	device_printf(dev, "could not load the stats DMA buffer\n");
689	goto fail;
690	}
691
692	error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
693	BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
694	FXP_TXCB_SZ, 1, FXP_TXCB_SZ, 0,
695	busdma_lock_mutex, &Giant, &sc->cbl_tag);
696	if (error) {
697	device_printf(dev, "could not create TxCB DMA tag\n");
698	goto fail;
699	}
700
701	error = bus_dmamem_alloc(sc->cbl_tag, (void **)&sc->fxp_desc.cbl_list,
702	BUS_DMA_NOWAIT \| BUS_DMA_ZERO, &sc->cbl_map);
703	if (error) {
704	device_printf(dev, "could not allocate TxCB DMA memory\n");
705	goto fail;
706	}
707
708	error = bus_dmamap_load(sc->cbl_tag, sc->cbl_map,
709	sc->fxp_desc.cbl_list, FXP_TXCB_SZ, fxp_dma_map_addr,
710	&sc->fxp_desc.cbl_addr, 0);
711	if (error) {
712	device_printf(dev, "could not load TxCB DMA buffer\n");
713	goto fail;
714	}
715
716	error = bus_dma_tag_create(bus_get_dma_tag(dev), 4, 0,
717	BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
718	sizeof(struct fxp_cb_mcs), 1, sizeof(struct fxp_cb_mcs), 0,
719	busdma_lock_mutex, &Giant, &sc->mcs_tag);
720	if (error) {
721	device_printf(dev,
722	"could not create multicast setup DMA tag\n");
723	goto fail;
724	}
725
726	error = bus_dmamem_alloc(sc->mcs_tag, (void **)&sc->mcsp,
727	BUS_DMA_NOWAIT \| BUS_DMA_ZERO, &sc->mcs_map);
728	if (error) {
729	device_printf(dev,
730	"could not allocate multicast setup DMA memory\n");
731	goto fail;
732	}
733	error = bus_dmamap_load(sc->mcs_tag, sc->mcs_map, sc->mcsp,
734	sizeof(struct fxp_cb_mcs), fxp_dma_map_addr, &sc->mcs_addr, 0);
735	if (error) {
736	device_printf(dev,
737	"can't load the multicast setup DMA buffer\n");
738	goto fail;
739	}
740
741	/*
742	* Pre-allocate the TX DMA maps and setup the pointers to
743	* the TX command blocks.
744	*/
745	txp = sc->fxp_desc.tx_list;
746	tcbp = sc->fxp_desc.cbl_list;
747	for (i = 0; i < FXP_NTXCB; i++) {
748	txp[i].tx_cb = tcbp + i;
749	error = bus_dmamap_create(sc->fxp_txmtag, 0, &txp[i].tx_map);
750	if (error) {
751	device_printf(dev, "can't create DMA map for TX\n");
752	goto fail;
753	}
754	}
755	error = bus_dmamap_create(sc->fxp_rxmtag, 0, &sc->spare_map);
756	if (error) {
757	device_printf(dev, "can't create spare DMA map\n");
758	goto fail;
759	}
760
761	/*
762	* Pre-allocate our receive buffers.
763	*/
764	sc->fxp_desc.rx_head = sc->fxp_desc.rx_tail = NULL;
765	for (i = 0; i < FXP_NRFABUFS; i++) {
766	rxp = &sc->fxp_desc.rx_list[i];
767	error = bus_dmamap_create(sc->fxp_rxmtag, 0, &rxp->rx_map);
768	if (error) {
769	device_printf(dev, "can't create DMA map for RX\n");
770	goto fail;
771	}
772	if (fxp_new_rfabuf(sc, rxp) != 0) {
773	error = ENOMEM;
774	goto fail;
775	}
776	fxp_add_rfabuf(sc, rxp);
777	}
778
779	/*
780	* Read MAC address.
781	*/
782	fxp_read_eeprom(sc, myea, 0, 3);
783	eaddr[0] = myea[0] & 0xff;
784	eaddr[1] = myea[0] >> 8;
785	eaddr[2] = myea[1] & 0xff;
786	eaddr[3] = myea[1] >> 8;
787	eaddr[4] = myea[2] & 0xff;
788	eaddr[5] = myea[2] >> 8;
789	if (bootverbose) {
790	device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n",
791	pci_get_vendor(dev), pci_get_device(dev),
792	pci_get_subvendor(dev), pci_get_subdevice(dev),
793	pci_get_revid(dev));
794	fxp_read_eeprom(sc, &data, 10, 1);
795	device_printf(dev, "Dynamic Standby mode is %s\n",
796	data & 0x02 ? "enabled" : "disabled");
797	}
798
799	/*
800	* If this is only a 10Mbps device, then there is no MII, and
801	* the PHY will use a serial interface instead.
802	*
803	* The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
804	* doesn't have a programming interface of any sort. The
805	* media is sensed automatically based on how the link partner
806	* is configured. This is, in essence, manual configuration.
807	*/
808	if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
809	ifmedia_add(&sc->sc_media, IFM_ETHER\|IFM_MANUAL, 0, NULL);
810	ifmedia_set(&sc->sc_media, IFM_ETHER\|IFM_MANUAL);
811	} else {
812	/*
813	* i82557 wedge when isolating all of their PHYs.
814	*/
815	flags = MIIF_NOISOLATE;
816	if (sc->revision >= FXP_REV_82558_A4)
817	flags \|= MIIF_DOPAUSE;
818	error = mii_attach(dev, &sc->miibus, ifp, fxp_ifmedia_upd,
819	fxp_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY,
820	MII_OFFSET_ANY, flags);
821	if (error != 0) {
822	device_printf(dev, "attaching PHYs failed\n");
823	goto fail;
824	}
825	}
826
827	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
828	ifp->if_init = fxp_init;
829	ifp->if_softc = sc;
830	ifp->if_flags = IFF_BROADCAST \| IFF_SIMPLEX \| IFF_MULTICAST;
831	ifp->if_ioctl = fxp_ioctl;
832	ifp->if_start = fxp_start;
833
834	ifp->if_capabilities = ifp->if_capenable = 0;
835
836	/* Enable checksum offload/TSO for 82550 or better chips */
837	if (sc->flags & FXP_FLAG_EXT_RFA) {
838	ifp->if_hwassist = FXP_CSUM_FEATURES \| CSUM_TSO;
839	ifp->if_capabilities \|= IFCAP_HWCSUM \| IFCAP_TSO4;
840	ifp->if_capenable \|= IFCAP_HWCSUM \| IFCAP_TSO4;
841	}
842
843	if (sc->flags & FXP_FLAG_82559_RXCSUM) {
844	ifp->if_capabilities \|= IFCAP_RXCSUM;
845	ifp->if_capenable \|= IFCAP_RXCSUM;
846	}
847
848	if (sc->flags & FXP_FLAG_WOLCAP) {
849	ifp->if_capabilities \|= IFCAP_WOL_MAGIC;
850	ifp->if_capenable \|= IFCAP_WOL_MAGIC;
851	}
852
853	#ifdef DEVICE_POLLING
854	/* Inform the world we support polling. */
855	ifp->if_capabilities \|= IFCAP_POLLING;
856	#endif
857
858	/*
859	* Attach the interface.
860	*/
861	ether_ifattach(ifp, eaddr);
862
863	/*
864	* Tell the upper layer(s) we support long frames.
865	* Must appear after the call to ether_ifattach() because
866	* ether_ifattach() sets ifi_hdrlen to the default value.
867	*/
868	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
869	ifp->if_capabilities \|= IFCAP_VLAN_MTU;
870	ifp->if_capenable \|= IFCAP_VLAN_MTU; /* the hw bits already set */
871	if ((sc->flags & FXP_FLAG_EXT_RFA) != 0) {
872	ifp->if_capabilities \|= IFCAP_VLAN_HWTAGGING \|
873	IFCAP_VLAN_HWCSUM \| IFCAP_VLAN_HWTSO;
874	ifp->if_capenable \|= IFCAP_VLAN_HWTAGGING \|
875	IFCAP_VLAN_HWCSUM \| IFCAP_VLAN_HWTSO;
876	}
877
878	/*
879	* Let the system queue as many packets as we have available
880	* TX descriptors.
881	*/
882	IFQ_SET_MAXLEN(&ifp->if_snd, FXP_NTXCB - 1);
883	ifp->if_snd.ifq_drv_maxlen = FXP_NTXCB - 1;
884	IFQ_SET_READY(&ifp->if_snd);
885
886	/*
887	* Hook our interrupt after all initialization is complete.
888	*/
889	error = bus_setup_intr(dev, sc->fxp_res[1], INTR_TYPE_NET \| INTR_MPSAFE,
890	NULL, fxp_intr, sc, &sc->ih);
891	if (error) {
892	device_printf(dev, "could not setup irq\n");
893	ether_ifdetach(sc->ifp);
894	goto fail;
895	}
896
897	/*
898	* Configure hardware to reject magic frames otherwise
899	* system will hang on recipt of magic frames.
900	*/
901	if ((sc->flags & FXP_FLAG_WOLCAP) != 0) {
902	FXP_LOCK(sc);
903	/* Clear wakeup events. */
904	CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR));
905	fxp_init_body(sc, 1);
906	fxp_stop(sc);
907	FXP_UNLOCK(sc);
908	}
909
910	fail:
911	if (error)
912	fxp_release(sc);
913	return (error);
914	}
915
916	/*
917	* Release all resources. The softc lock should not be held and the
918	* interrupt should already be torn down.
919	*/
920	static void
921	fxp_release(struct fxp_softc *sc)
922	{
923	struct fxp_rx *rxp;
924	struct fxp_tx *txp;
925	int i;
926
927	FXP_LOCK_ASSERT(sc, MA_NOTOWNED);
928	KASSERT(sc->ih == NULL,
929	("fxp_release() called with intr handle still active"));
930	if (sc->miibus)
931	device_delete_child(sc->dev, sc->miibus);
932	bus_generic_detach(sc->dev);
933	ifmedia_removeall(&sc->sc_media);
934	if (sc->fxp_desc.cbl_list) {
935	bus_dmamap_unload(sc->cbl_tag, sc->cbl_map);
936	bus_dmamem_free(sc->cbl_tag, sc->fxp_desc.cbl_list,
937	sc->cbl_map);
938	}
939	if (sc->fxp_stats) {
940	bus_dmamap_unload(sc->fxp_stag, sc->fxp_smap);
941	bus_dmamem_free(sc->fxp_stag, sc->fxp_stats, sc->fxp_smap);
942	}
943	if (sc->mcsp) {
944	bus_dmamap_unload(sc->mcs_tag, sc->mcs_map);
945	bus_dmamem_free(sc->mcs_tag, sc->mcsp, sc->mcs_map);
946	}
947	bus_release_resources(sc->dev, sc->fxp_spec, sc->fxp_res);
948	if (sc->fxp_rxmtag) {
949	for (i = 0; i < FXP_NRFABUFS; i++) {
950	rxp = &sc->fxp_desc.rx_list[i];
951	if (rxp->rx_mbuf != NULL) {
952	bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
953	BUS_DMASYNC_POSTREAD);
954	bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map);
955	m_freem(rxp->rx_mbuf);
956	}
957	bus_dmamap_destroy(sc->fxp_rxmtag, rxp->rx_map);
958	}
959	bus_dmamap_destroy(sc->fxp_rxmtag, sc->spare_map);
960	bus_dma_tag_destroy(sc->fxp_rxmtag);
961	}
962	if (sc->fxp_txmtag) {
963	for (i = 0; i < FXP_NTXCB; i++) {
964	txp = &sc->fxp_desc.tx_list[i];
965	if (txp->tx_mbuf != NULL) {
966	bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map,
967	BUS_DMASYNC_POSTWRITE);
968	bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map);
969	m_freem(txp->tx_mbuf);
970	}
971	bus_dmamap_destroy(sc->fxp_txmtag, txp->tx_map);
972	}
973	bus_dma_tag_destroy(sc->fxp_txmtag);
974	}
975	if (sc->fxp_stag)
976	bus_dma_tag_destroy(sc->fxp_stag);
977	if (sc->cbl_tag)
978	bus_dma_tag_destroy(sc->cbl_tag);
979	if (sc->mcs_tag)
980	bus_dma_tag_destroy(sc->mcs_tag);
981	if (sc->ifp)
982	if_free(sc->ifp);
983
984	mtx_destroy(&sc->sc_mtx);
985	}
986
987	/*
988	* Detach interface.
989	*/
990	static int
991	fxp_detach(device_t dev)
992	{
993	struct fxp_softc *sc = device_get_softc(dev);
994
995	#ifdef DEVICE_POLLING
996	if (sc->ifp->if_capenable & IFCAP_POLLING)
997	ether_poll_deregister(sc->ifp);
998	#endif
999
1000	FXP_LOCK(sc);
1001	/*
1002	* Stop DMA and drop transmit queue, but disable interrupts first.
1003	*/
1004	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1005	fxp_stop(sc);
1006	FXP_UNLOCK(sc);
1007	callout_drain(&sc->stat_ch);
1008
1009	/*
1010	* Close down routes etc.
1011	*/
1012	ether_ifdetach(sc->ifp);
1013
1014	/*
1015	* Unhook interrupt before dropping lock. This is to prevent
1016	* races with fxp_intr().
1017	*/
1018	bus_teardown_intr(sc->dev, sc->fxp_res[1], sc->ih);
1019	sc->ih = NULL;
1020
1021	/* Release our allocated resources. */
1022	fxp_release(sc);
1023	return (0);
1024	}
1025
1026	/*
1027	* Device shutdown routine. Called at system shutdown after sync. The
1028	* main purpose of this routine is to shut off receiver DMA so that
1029	* kernel memory doesn't get clobbered during warmboot.
1030	*/
1031	static int
1032	fxp_shutdown(device_t dev)
1033	{
1034
1035	/*
1036	* Make sure that DMA is disabled prior to reboot. Not doing
1037	* do could allow DMA to corrupt kernel memory during the
1038	* reboot before the driver initializes.
1039	*/
1040	return (fxp_suspend(dev));
1041	}
1042
1043	/*
1044	* Device suspend routine. Stop the interface and save some PCI
1045	* settings in case the BIOS doesn't restore them properly on
1046	* resume.
1047	*/
1048	static int
1049	fxp_suspend(device_t dev)
1050	{
1051	struct fxp_softc *sc = device_get_softc(dev);
1052	struct ifnet *ifp;
1053	int pmc;
1054	uint16_t pmstat;
1055
1056	FXP_LOCK(sc);
1057
1058	ifp = sc->ifp;
1059	if (pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) {
1060	pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
1061	pmstat &= ~(PCIM_PSTAT_PME \| PCIM_PSTAT_PMEENABLE);
1062	if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1063	/* Request PME. */
1064	pmstat \|= PCIM_PSTAT_PME \| PCIM_PSTAT_PMEENABLE;
1065	sc->flags \|= FXP_FLAG_WOL;
1066	/* Reconfigure hardware to accept magic frames. */
1067	fxp_init_body(sc, 1);
1068	}
1069	pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1070	}
1071	fxp_stop(sc);
1072
1073	sc->suspended = 1;
1074
1075	FXP_UNLOCK(sc);
1076	return (0);
1077	}
1078
1079	/*
1080	* Device resume routine. re-enable busmastering, and restart the interface if
1081	* appropriate.
1082	*/
1083	static int
1084	fxp_resume(device_t dev)
1085	{
1086	struct fxp_softc *sc = device_get_softc(dev);
1087	struct ifnet *ifp = sc->ifp;
1088	int pmc;
1089	uint16_t pmstat;
1090
1091	FXP_LOCK(sc);
1092
1093	if (pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) {
1094	sc->flags &= ~FXP_FLAG_WOL;
1095	pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
1096	/* Disable PME and clear PME status. */
1097	pmstat &= ~PCIM_PSTAT_PMEENABLE;
1098	pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1099	if ((sc->flags & FXP_FLAG_WOLCAP) != 0)
1100	CSR_WRITE_1(sc, FXP_CSR_PMDR,
1101	CSR_READ_1(sc, FXP_CSR_PMDR));
1102	}
1103
1104	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
1105	DELAY(10);
1106
1107	/* reinitialize interface if necessary */
1108	if (ifp->if_flags & IFF_UP)
1109	fxp_init_body(sc, 1);
1110
1111	sc->suspended = 0;
1112
1113	FXP_UNLOCK(sc);
1114	return (0);
1115	}
1116
1117	static void
1118	fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
1119	{
1120	uint16_t reg;
1121	int x;
1122
1123	/*
1124	* Shift in data.
1125	*/
1126	for (x = 1 << (length - 1); x; x >>= 1) {
1127	if (data & x)
1128	reg = FXP_EEPROM_EECS \| FXP_EEPROM_EEDI;
1129	else
1130	reg = FXP_EEPROM_EECS;
1131	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1132	DELAY(1);
1133	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg \| FXP_EEPROM_EESK);
1134	DELAY(1);
1135	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1136	DELAY(1);
1137	}
1138	}
1139
1140	/*
1141	* Read from the serial EEPROM. Basically, you manually shift in
1142	* the read opcode (one bit at a time) and then shift in the address,
1143	* and then you shift out the data (all of this one bit at a time).
1144	* The word size is 16 bits, so you have to provide the address for
1145	* every 16 bits of data.
1146	*/
1147	static uint16_t
1148	fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
1149	{
1150	uint16_t reg, data;
1151	int x;
1152
1153	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1154	/*
1155	* Shift in read opcode.
1156	*/
1157	fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
1158	/*
1159	* Shift in address.
1160	*/
1161	data = 0;
1162	for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
1163	if (offset & x)
1164	reg = FXP_EEPROM_EECS \| FXP_EEPROM_EEDI;
1165	else
1166	reg = FXP_EEPROM_EECS;
1167	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1168	DELAY(1);
1169	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg \| FXP_EEPROM_EESK);
1170	DELAY(1);
1171	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1172	DELAY(1);
1173	reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
1174	data++;
1175	if (autosize && reg == 0) {
1176	sc->eeprom_size = data;
1177	break;
1178	}
1179	}
1180	/*
1181	* Shift out data.
1182	*/
1183	data = 0;
1184	reg = FXP_EEPROM_EECS;
1185	for (x = 1 << 15; x; x >>= 1) {
1186	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg \| FXP_EEPROM_EESK);
1187	DELAY(1);
1188	if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1189	data \|= x;
1190	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1191	DELAY(1);
1192	}
1193	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1194	DELAY(1);
1195
1196	return (data);
1197	}
1198
1199	static void
1200	fxp_eeprom_putword(struct fxp_softc *sc, int offset, uint16_t data)
1201	{
1202	int i;
1203
1204	/*
1205	* Erase/write enable.
1206	*/
1207	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1208	fxp_eeprom_shiftin(sc, 0x4, 3);
1209	fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
1210	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1211	DELAY(1);
1212	/*
1213	* Shift in write opcode, address, data.
1214	*/
1215	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1216	fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
1217	fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
1218	fxp_eeprom_shiftin(sc, data, 16);
1219	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1220	DELAY(1);
1221	/*
1222	* Wait for EEPROM to finish up.
1223	*/
1224	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1225	DELAY(1);
1226	for (i = 0; i < 1000; i++) {
1227	if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
1228	break;
1229	DELAY(50);
1230	}
1231	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1232	DELAY(1);
1233	/*
1234	* Erase/write disable.
1235	*/
1236	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1237	fxp_eeprom_shiftin(sc, 0x4, 3);
1238	fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
1239	CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
1240	DELAY(1);
1241	}
1242
1243	/*
1244	* From NetBSD:
1245	*
1246	* Figure out EEPROM size.
1247	*
1248	* 559's can have either 64-word or 256-word EEPROMs, the 558
1249	* datasheet only talks about 64-word EEPROMs, and the 557 datasheet
1250	* talks about the existance of 16 to 256 word EEPROMs.
1251	*
1252	* The only known sizes are 64 and 256, where the 256 version is used
1253	* by CardBus cards to store CIS information.
1254	*
1255	* The address is shifted in msb-to-lsb, and after the last
1256	* address-bit the EEPROM is supposed to output a `dummy zero' bit,
1257	* after which follows the actual data. We try to detect this zero, by
1258	* probing the data-out bit in the EEPROM control register just after
1259	* having shifted in a bit. If the bit is zero, we assume we've
1260	* shifted enough address bits. The data-out should be tri-state,
1261	* before this, which should translate to a logical one.
1262	*/
1263	static void
1264	fxp_autosize_eeprom(struct fxp_softc *sc)
1265	{
1266
1267	/* guess maximum size of 256 words */
1268	sc->eeprom_size = 8;
1269
1270	/* autosize */
1271	(void) fxp_eeprom_getword(sc, 0, 1);
1272	}
1273
1274	static void
1275	fxp_read_eeprom(struct fxp_softc sc, u_short data, int offset, int words)
1276	{
1277	int i;
1278
1279	for (i = 0; i < words; i++)
1280	data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1281	}
1282
1283	static void
1284	fxp_write_eeprom(struct fxp_softc sc, u_short data, int offset, int words)
1285	{
1286	int i;
1287
1288	for (i = 0; i < words; i++)
1289	fxp_eeprom_putword(sc, offset + i, data[i]);
1290	}
1291
1292	/*
1293	* Grab the softc lock and call the real fxp_start_body() routine
1294	*/
1295	static void
1296	fxp_start(struct ifnet *ifp)
1297	{
1298	struct fxp_softc *sc = ifp->if_softc;
1299
1300	FXP_LOCK(sc);
1301	fxp_start_body(ifp);
1302	FXP_UNLOCK(sc);
1303	}
1304
1305	/*
1306	* Start packet transmission on the interface.
1307	* This routine must be called with the softc lock held, and is an
1308	* internal entry point only.
1309	*/
1310	static void
1311	fxp_start_body(struct ifnet *ifp)
1312	{
1313	struct fxp_softc *sc = ifp->if_softc;
1314	struct mbuf *mb_head;
1315	int txqueued;
1316
1317	FXP_LOCK_ASSERT(sc, MA_OWNED);
1318
1319	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING \| IFF_DRV_OACTIVE)) !=
1320	IFF_DRV_RUNNING)
1321	return;
1322
1323	if (sc->tx_queued > FXP_NTXCB_HIWAT)
1324	fxp_txeof(sc);
1325	/*
1326	* We're finished if there is nothing more to add to the list or if
1327	* we're all filled up with buffers to transmit.
1328	* NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1329	* a NOP command when needed.
1330	*/
1331	txqueued = 0;
1332	while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
1333	sc->tx_queued < FXP_NTXCB - 1) {
1334
1335	/*
1336	* Grab a packet to transmit.
1337	*/
1338	IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head);
1339	if (mb_head == NULL)
1340	break;
1341
1342	if (fxp_encap(sc, &mb_head)) {
1343	if (mb_head == NULL)
1344	break;
1345	IFQ_DRV_PREPEND(&ifp->if_snd, mb_head);
1346	ifp->if_drv_flags \|= IFF_DRV_OACTIVE;
1347	}
1348	txqueued++;
1349	/*
1350	* Pass packet to bpf if there is a listener.
1351	*/
1352	BPF_MTAP(ifp, mb_head);
1353	}
1354
1355	/*
1356	* We're finished. If we added to the list, issue a RESUME to get DMA
1357	* going again if suspended.
1358	*/
1359	if (txqueued > 0) {
1360	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1361	BUS_DMASYNC_PREREAD \| BUS_DMASYNC_PREWRITE);
1362	fxp_scb_wait(sc);
1363	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1364	/*
1365	* Set a 5 second timer just in case we don't hear
1366	* from the card again.
1367	*/
1368	sc->watchdog_timer = 5;
1369	}
1370	}
1371
1372	static int
1373	fxp_encap(struct fxp_softc sc, struct mbuf *m_head)
1374	{
1375	struct ifnet *ifp;
1376	struct mbuf *m;
1377	struct fxp_tx *txp;
1378	struct fxp_cb_tx *cbp;
1379	struct tcphdr *tcp;
1380	bus_dma_segment_t segs[FXP_NTXSEG];
1381	int error, i, nseg, tcp_payload;
1382
1383	FXP_LOCK_ASSERT(sc, MA_OWNED);
1384	ifp = sc->ifp;
1385
1386	tcp_payload = 0;
1387	tcp = NULL;
1388	/*
1389	* Get pointer to next available tx desc.
1390	*/
1391	txp = sc->fxp_desc.tx_last->tx_next;
1392
1393	/*
1394	* A note in Appendix B of the Intel 8255x 10/100 Mbps
1395	* Ethernet Controller Family Open Source Software
1396	* Developer Manual says:
1397	* Using software parsing is only allowed with legal
1398	* TCP/IP or UDP/IP packets.
1399	* ...
1400	* For all other datagrams, hardware parsing must
1401	* be used.
1402	* Software parsing appears to truncate ICMP and
1403	* fragmented UDP packets that contain one to three
1404	* bytes in the second (and final) mbuf of the packet.
1405	*/
1406	if (sc->flags & FXP_FLAG_EXT_RFA)
1407	txp->tx_cb->ipcb_ip_activation_high =
1408	FXP_IPCB_HARDWAREPARSING_ENABLE;
1409
1410	m = *m_head;
1411	if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1412	/*
1413	* 82550/82551 requires ethernet/IP/TCP headers must be
1414	* contained in the first active transmit buffer.
1415	*/
1416	struct ether_header *eh;
1417	struct ip *ip;
1418	uint32_t ip_off, poff;
1419
1420	if (M_WRITABLE(*m_head) == 0) {
1421	/* Get a writable copy. */
1422	m = m_dup(*m_head, M_DONTWAIT);
1423	m_freem(*m_head);
1424	if (m == NULL) {
1425	*m_head = NULL;
1426	return (ENOBUFS);
1427	}
1428	*m_head = m;
1429	}
1430	ip_off = sizeof(struct ether_header);
1431	m = m_pullup(*m_head, ip_off);
1432	if (m == NULL) {
1433	*m_head = NULL;
1434	return (ENOBUFS);
1435	}
1436	eh = mtod(m, struct ether_header *);
1437	/* Check the existence of VLAN tag. */
1438	if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1439	ip_off = sizeof(struct ether_vlan_header);
1440	m = m_pullup(m, ip_off);
1441	if (m == NULL) {
1442	*m_head = NULL;
1443	return (ENOBUFS);
1444	}
1445	}
1446	m = m_pullup(m, ip_off + sizeof(struct ip));
1447	if (m == NULL) {
1448	*m_head = NULL;
1449	return (ENOBUFS);
1450	}
1451	ip = (struct ip )(mtod(m, char ) + ip_off);
1452	poff = ip_off + (ip->ip_hl << 2);
1453	m = m_pullup(m, poff + sizeof(struct tcphdr));
1454	if (m == NULL) {
1455	*m_head = NULL;
1456	return (ENOBUFS);
1457	}
1458	tcp = (struct tcphdr )(mtod(m, char ) + poff);
1459	m = m_pullup(m, poff + sizeof(struct tcphdr) + tcp->th_off);
1460	if (m == NULL) {
1461	*m_head = NULL;
1462	return (ENOBUFS);
1463	}
1464
1465	/*
1466	* Since 82550/82551 doesn't modify IP length and pseudo
1467	* checksum in the first frame driver should compute it.
1468	*/
1469	ip = (struct ip )(mtod(m, char ) + ip_off);
1470	tcp = (struct tcphdr )(mtod(m, char ) + poff);
1471	ip->ip_sum = 0;
1472	ip->ip_len = htons(m->m_pkthdr.tso_segsz + (ip->ip_hl << 2) +
1473	(tcp->th_off << 2));
1474	tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr,
1475	htons(IPPROTO_TCP + (tcp->th_off << 2) +
1476	m->m_pkthdr.tso_segsz));
1477	/* Compute total TCP payload. */
1478	tcp_payload = m->m_pkthdr.len - ip_off - (ip->ip_hl << 2);
1479	tcp_payload -= tcp->th_off << 2;
1480	*m_head = m;
1481	} else if (m->m_pkthdr.csum_flags & FXP_CSUM_FEATURES) {
1482	/*
1483	* Deal with TCP/IP checksum offload. Note that
1484	* in order for TCP checksum offload to work,
1485	* the pseudo header checksum must have already
1486	* been computed and stored in the checksum field
1487	* in the TCP header. The stack should have
1488	* already done this for us.
1489	*/
1490	txp->tx_cb->ipcb_ip_schedule = FXP_IPCB_TCPUDP_CHECKSUM_ENABLE;
1491	if (m->m_pkthdr.csum_flags & CSUM_TCP)
1492	txp->tx_cb->ipcb_ip_schedule \|= FXP_IPCB_TCP_PACKET;
1493
1494	#ifdef FXP_IP_CSUM_WAR
1495	/*
1496	* XXX The 82550 chip appears to have trouble
1497	* dealing with IP header checksums in very small
1498	* datagrams, namely fragments from 1 to 3 bytes
1499	* in size. For example, say you want to transmit
1500	* a UDP packet of 1473 bytes. The packet will be
1501	* fragmented over two IP datagrams, the latter
1502	* containing only one byte of data. The 82550 will
1503	* botch the header checksum on the 1-byte fragment.
1504	* As long as the datagram contains 4 or more bytes
1505	* of data, you're ok.
1506	*
1507	* The following code attempts to work around this
1508	* problem: if the datagram is less than 38 bytes
1509	* in size (14 bytes ether header, 20 bytes IP header,
1510	* plus 4 bytes of data), we punt and compute the IP
1511	* header checksum by hand. This workaround doesn't
1512	* work very well, however, since it can be fooled
1513	* by things like VLAN tags and IP options that make
1514	* the header sizes/offsets vary.
1515	*/
1516
1517	if (m->m_pkthdr.csum_flags & CSUM_IP) {
1518	if (m->m_pkthdr.len < 38) {
1519	struct ip *ip;
1520	m->m_data += ETHER_HDR_LEN;
1521	ip = mtod(m, struct ip *);
1522	ip->ip_sum = in_cksum(m, ip->ip_hl << 2);
1523	m->m_data -= ETHER_HDR_LEN;
1524	m->m_pkthdr.csum_flags &= ~CSUM_IP;
1525	} else {
1526	txp->tx_cb->ipcb_ip_activation_high =
1527	FXP_IPCB_HARDWAREPARSING_ENABLE;
1528	txp->tx_cb->ipcb_ip_schedule \|=
1529	FXP_IPCB_IP_CHECKSUM_ENABLE;
1530	}
1531	}
1532	#endif
1533	}
1534
1535	error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map, *m_head,
1536	segs, &nseg, 0);
1537	if (error == EFBIG) {
1538	m = m_collapse(*m_head, M_DONTWAIT, sc->maxtxseg);
1539	if (m == NULL) {
1540	m_freem(*m_head);
1541	*m_head = NULL;
1542	return (ENOMEM);
1543	}
1544	*m_head = m;
1545	error = bus_dmamap_load_mbuf_sg(sc->fxp_txmtag, txp->tx_map,
1546	*m_head, segs, &nseg, 0);
1547	if (error != 0) {
1548	m_freem(*m_head);
1549	*m_head = NULL;
1550	return (ENOMEM);
1551	}
1552	} else if (error != 0)
1553	return (error);
1554	if (nseg == 0) {
1555	m_freem(*m_head);
1556	*m_head = NULL;
1557	return (EIO);
1558	}
1559
1560	KASSERT(nseg <= sc->maxtxseg, ("too many DMA segments"));
1561	bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map, BUS_DMASYNC_PREWRITE);
1562
1563	cbp = txp->tx_cb;
1564	for (i = 0; i < nseg; i++) {
1565	/*
1566	* If this is an 82550/82551, then we're using extended
1567	* TxCBs _and_ we're using checksum offload. This means
1568	* that the TxCB is really an IPCB. One major difference
1569	* between the two is that with plain extended TxCBs,
1570	* the bottom half of the TxCB contains two entries from
1571	* the TBD array, whereas IPCBs contain just one entry:
1572	* one entry (8 bytes) has been sacrificed for the TCP/IP
1573	* checksum offload control bits. So to make things work
1574	* right, we have to start filling in the TBD array
1575	* starting from a different place depending on whether
1576	* the chip is an 82550/82551 or not.
1577	*/
1578	if (sc->flags & FXP_FLAG_EXT_RFA) {
1579	cbp->tbd[i + 1].tb_addr = htole32(segs[i].ds_addr);
1580	cbp->tbd[i + 1].tb_size = htole32(segs[i].ds_len);
1581	} else {
1582	cbp->tbd[i].tb_addr = htole32(segs[i].ds_addr);
1583	cbp->tbd[i].tb_size = htole32(segs[i].ds_len);
1584	}
1585	}
1586	if (sc->flags & FXP_FLAG_EXT_RFA) {
1587	/* Configure dynamic TBD for 82550/82551. */
1588	cbp->tbd_number = 0xFF;
1589	cbp->tbd[nseg].tb_size \|= htole32(0x8000);
1590	} else
1591	cbp->tbd_number = nseg;
1592	/* Configure TSO. */
1593	if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1594	cbp->tbd[-1].tb_size = htole32(m->m_pkthdr.tso_segsz << 16);
1595	cbp->tbd[1].tb_size \|= htole32(tcp_payload << 16);
1596	cbp->ipcb_ip_schedule \|= FXP_IPCB_LARGESEND_ENABLE \|
1597	FXP_IPCB_IP_CHECKSUM_ENABLE \|
1598	FXP_IPCB_TCP_PACKET \|
1599	FXP_IPCB_TCPUDP_CHECKSUM_ENABLE;
1600	}
1601	/* Configure VLAN hardware tag insertion. */
1602	if ((m->m_flags & M_VLANTAG) != 0) {
1603	cbp->ipcb_vlan_id = htons(m->m_pkthdr.ether_vtag);
1604	txp->tx_cb->ipcb_ip_activation_high \|=
1605	FXP_IPCB_INSERTVLAN_ENABLE;
1606	}
1607
1608	txp->tx_mbuf = m;
1609	txp->tx_cb->cb_status = 0;
1610	txp->tx_cb->byte_count = 0;
1611	if (sc->tx_queued != FXP_CXINT_THRESH - 1)
1612	txp->tx_cb->cb_command =
1613	htole16(sc->tx_cmd \| FXP_CB_COMMAND_SF \|
1614	FXP_CB_COMMAND_S);
1615	else
1616	txp->tx_cb->cb_command =
1617	htole16(sc->tx_cmd \| FXP_CB_COMMAND_SF \|
1618	FXP_CB_COMMAND_S \| FXP_CB_COMMAND_I);
1619	if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0)
1620	txp->tx_cb->tx_threshold = tx_threshold;
1621
1622	/*
1623	* Advance the end of list forward.
1624	*/
1625	sc->fxp_desc.tx_last->tx_cb->cb_command &= htole16(~FXP_CB_COMMAND_S);
1626	sc->fxp_desc.tx_last = txp;
1627
1628	/*
1629	* Advance the beginning of the list forward if there are
1630	* no other packets queued (when nothing is queued, tx_first
1631	* sits on the last TxCB that was sent out).
1632	*/
1633	if (sc->tx_queued == 0)
1634	sc->fxp_desc.tx_first = txp;
1635
1636	sc->tx_queued++;
1637
1638	return (0);
1639	}
1640
1641	#ifdef DEVICE_POLLING
1642	static poll_handler_t fxp_poll;
1643
1644	static int
1645	fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1646	{
1647	struct fxp_softc *sc = ifp->if_softc;
1648	uint8_t statack;
1649	int rx_npkts = 0;
1650
1651	FXP_LOCK(sc);
1652	if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1653	FXP_UNLOCK(sc);
1654	return (rx_npkts);
1655	}
1656
1657	statack = FXP_SCB_STATACK_CXTNO \| FXP_SCB_STATACK_CNA \|
1658	FXP_SCB_STATACK_FR;
1659	if (cmd == POLL_AND_CHECK_STATUS) {
1660	uint8_t tmp;
1661
1662	tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1663	if (tmp == 0xff \|\| tmp == 0) {
1664	FXP_UNLOCK(sc);
1665	return (rx_npkts); /* nothing to do */
1666	}
1667	tmp &= ~statack;
1668	/* ack what we can */
1669	if (tmp != 0)
1670	CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);
1671	statack \|= tmp;
1672	}
1673	rx_npkts = fxp_intr_body(sc, ifp, statack, count);
1674	FXP_UNLOCK(sc);
1675	return (rx_npkts);
1676	}
1677	#endif /* DEVICE_POLLING */
1678
1679	/*
1680	* Process interface interrupts.
1681	*/
1682	static void
1683	fxp_intr(void *xsc)
1684	{
1685	struct fxp_softc *sc = xsc;
1686	struct ifnet *ifp = sc->ifp;
1687	uint8_t statack;
1688
1689	FXP_LOCK(sc);
1690	if (sc->suspended) {
1691	FXP_UNLOCK(sc);
1692	return;
1693	}
1694
1695	#ifdef DEVICE_POLLING
1696	if (ifp->if_capenable & IFCAP_POLLING) {
1697	FXP_UNLOCK(sc);
1698	return;
1699	}
1700	#endif
1701	while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1702	/*
1703	* It should not be possible to have all bits set; the
1704	* FXP_SCB_INTR_SWI bit always returns 0 on a read. If
1705	* all bits are set, this may indicate that the card has
1706	* been physically ejected, so ignore it.
1707	*/
1708	if (statack == 0xff) {
1709	FXP_UNLOCK(sc);
1710	return;
1711	}
1712
1713	/*
1714	* First ACK all the interrupts in this pass.
1715	*/
1716	CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1717	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1718	fxp_intr_body(sc, ifp, statack, -1);
1719	}
1720	FXP_UNLOCK(sc);
1721	}
1722
1723	static void
1724	fxp_txeof(struct fxp_softc *sc)
1725	{
1726	struct ifnet *ifp;
1727	struct fxp_tx *txp;
1728
1729	ifp = sc->ifp;
1730	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1731	BUS_DMASYNC_POSTREAD \| BUS_DMASYNC_POSTWRITE);
1732	for (txp = sc->fxp_desc.tx_first; sc->tx_queued &&
1733	(le16toh(txp->tx_cb->cb_status) & FXP_CB_STATUS_C) != 0;
1734	txp = txp->tx_next) {
1735	if (txp->tx_mbuf != NULL) {
1736	bus_dmamap_sync(sc->fxp_txmtag, txp->tx_map,
1737	BUS_DMASYNC_POSTWRITE);
1738	bus_dmamap_unload(sc->fxp_txmtag, txp->tx_map);
1739	m_freem(txp->tx_mbuf);
1740	txp->tx_mbuf = NULL;
1741	/* clear this to reset csum offload bits */
1742	txp->tx_cb->tbd[0].tb_addr = 0;
1743	}
1744	sc->tx_queued--;
1745	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1746	}
1747	sc->fxp_desc.tx_first = txp;
1748	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
1749	BUS_DMASYNC_PREREAD \| BUS_DMASYNC_PREWRITE);
1750	if (sc->tx_queued == 0)
1751	sc->watchdog_timer = 0;
1752	}
1753
1754	static void
1755	fxp_rxcsum(struct fxp_softc sc, struct ifnet ifp, struct mbuf *m,
1756	uint16_t status, int pos)
1757	{
1758	struct ether_header *eh;
1759	struct ip *ip;
1760	struct udphdr *uh;
1761	int32_t hlen, len, pktlen, temp32;
1762	uint16_t csum, *opts;
1763
1764	if ((sc->flags & FXP_FLAG_82559_RXCSUM) == 0) {
1765	if ((status & FXP_RFA_STATUS_PARSE) != 0) {
1766	if (status & FXP_RFDX_CS_IP_CSUM_BIT_VALID)
1767	m->m_pkthdr.csum_flags \|= CSUM_IP_CHECKED;
1768	if (status & FXP_RFDX_CS_IP_CSUM_VALID)
1769	m->m_pkthdr.csum_flags \|= CSUM_IP_VALID;
1770	if ((status & FXP_RFDX_CS_TCPUDP_CSUM_BIT_VALID) &&
1771	(status & FXP_RFDX_CS_TCPUDP_CSUM_VALID)) {
1772	m->m_pkthdr.csum_flags \|= CSUM_DATA_VALID \|
1773	CSUM_PSEUDO_HDR;
1774	m->m_pkthdr.csum_data = 0xffff;
1775	}
1776	}
1777	return;
1778	}
1779
1780	pktlen = m->m_pkthdr.len;
1781	if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
1782	return;
1783	eh = mtod(m, struct ether_header *);
1784	if (eh->ether_type != htons(ETHERTYPE_IP))
1785	return;
1786	ip = (struct ip *)(eh + 1);
1787	if (ip->ip_v != IPVERSION)
1788	return;
1789
1790	hlen = ip->ip_hl << 2;
1791	pktlen -= sizeof(struct ether_header);
1792	if (hlen < sizeof(struct ip))
1793	return;
1794	if (ntohs(ip->ip_len) < hlen)
1795	return;
1796	if (ntohs(ip->ip_len) != pktlen)
1797	return;
1798	if (ip->ip_off & htons(IP_MF \| IP_OFFMASK))
1799	return; /* can't handle fragmented packet */
1800
1801	switch (ip->ip_p) {
1802	case IPPROTO_TCP:
1803	if (pktlen < (hlen + sizeof(struct tcphdr)))
1804	return;
1805	break;
1806	case IPPROTO_UDP:
1807	if (pktlen < (hlen + sizeof(struct udphdr)))
1808	return;
1809	uh = (struct udphdr *)((caddr_t)ip + hlen);
1810	if (uh->uh_sum == 0)
1811	return; /* no checksum */
1812	break;
1813	default:
1814	return;
1815	}
1816	/* Extract computed checksum. */
1817	csum = be16dec(mtod(m, char *) + pos);
1818	/* checksum fixup for IP options */
1819	len = hlen - sizeof(struct ip);
1820	if (len > 0) {
1821	opts = (uint16_t *)(ip + 1);
1822	for (; len > 0; len -= sizeof(uint16_t), opts++) {
1823	temp32 = csum - *opts;
1824	temp32 = (temp32 >> 16) + (temp32 & 65535);
1825	csum = temp32 & 65535;
1826	}
1827	}
1828	m->m_pkthdr.csum_flags \|= CSUM_DATA_VALID;
1829	m->m_pkthdr.csum_data = csum;
1830	}
1831
1832	static int
1833	fxp_intr_body(struct fxp_softc sc, struct ifnet ifp, uint8_t statack,
1834	int count)
1835	{
1836	struct mbuf *m;
1837	struct fxp_rx *rxp;
1838	struct fxp_rfa *rfa;
1839	int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0;
1840	int rx_npkts;
1841	uint16_t status;
1842
1843	rx_npkts = 0;
1844	FXP_LOCK_ASSERT(sc, MA_OWNED);
1845
1846	if (rnr)
1847	sc->rnr++;
1848	#ifdef DEVICE_POLLING
1849	/* Pick up a deferred RNR condition if `count' ran out last time. */
1850	if (sc->flags & FXP_FLAG_DEFERRED_RNR) {
1851	sc->flags &= ~FXP_FLAG_DEFERRED_RNR;
1852	rnr = 1;
1853	}
1854	#endif
1855
1856	/*
1857	* Free any finished transmit mbuf chains.
1858	*
1859	* Handle the CNA event likt a CXTNO event. It used to
1860	* be that this event (control unit not ready) was not
1861	* encountered, but it is now with the SMPng modifications.
1862	* The exact sequence of events that occur when the interface
1863	* is brought up are different now, and if this event
1864	* goes unhandled, the configuration/rxfilter setup sequence
1865	* can stall for several seconds. The result is that no
1866	* packets go out onto the wire for about 5 to 10 seconds
1867	* after the interface is ifconfig'ed for the first time.
1868	*/
1869	if (statack & (FXP_SCB_STATACK_CXTNO \| FXP_SCB_STATACK_CNA))
1870	fxp_txeof(sc);
1871
1872	/*
1873	* Try to start more packets transmitting.
1874	*/
1875	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1876	fxp_start_body(ifp);
1877
1878	/*
1879	* Just return if nothing happened on the receive side.
1880	*/
1881	if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0)
1882	return (rx_npkts);
1883
1884	/*
1885	* Process receiver interrupts. If a no-resource (RNR)
1886	* condition exists, get whatever packets we can and
1887	* re-start the receiver.
1888	*
1889	* When using polling, we do not process the list to completion,
1890	* so when we get an RNR interrupt we must defer the restart
1891	* until we hit the last buffer with the C bit set.
1892	* If we run out of cycles and rfa_headm has the C bit set,
1893	* record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so
1894	* that the info will be used in the subsequent polling cycle.
1895	*/
1896	for (;;) {
1897	rxp = sc->fxp_desc.rx_head;
1898	m = rxp->rx_mbuf;
1899	rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1900	RFA_ALIGNMENT_FUDGE);
1901	bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
1902	BUS_DMASYNC_POSTREAD \| BUS_DMASYNC_POSTWRITE);
1903
1904	#ifdef DEVICE_POLLING /* loop at most count times if count >=0 */
1905	if (count >= 0 && count-- == 0) {
1906	if (rnr) {
1907	/* Defer RNR processing until the next time. */
1908	sc->flags \|= FXP_FLAG_DEFERRED_RNR;
1909	rnr = 0;
1910	}
1911	break;
1912	}
1913	#endif /* DEVICE_POLLING */
1914
1915	status = le16toh(rfa->rfa_status);
1916	if ((status & FXP_RFA_STATUS_C) == 0)
1917	break;
1918
1919	if ((status & FXP_RFA_STATUS_RNR) != 0)
1920	rnr++;
1921	/*
1922	* Advance head forward.
1923	*/
1924	sc->fxp_desc.rx_head = rxp->rx_next;
1925
1926	/*
1927	* Add a new buffer to the receive chain.
1928	* If this fails, the old buffer is recycled
1929	* instead.
1930	*/
1931	if (fxp_new_rfabuf(sc, rxp) == 0) {
1932	int total_len;
1933
1934	/*
1935	* Fetch packet length (the top 2 bits of
1936	* actual_size are flags set by the controller
1937	* upon completion), and drop the packet in case
1938	* of bogus length or CRC errors.
1939	*/
1940	total_len = le16toh(rfa->actual_size) & 0x3fff;
1941	if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 &&
1942	(ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1943	/* Adjust for appended checksum bytes. */
1944	total_len -= 2;
1945	}
1946	if (total_len < sizeof(struct ether_header) \|\|
1947	total_len > (MCLBYTES - RFA_ALIGNMENT_FUDGE -
1948	sc->rfa_size) \|\|
1949	status & (FXP_RFA_STATUS_CRC \|
1950	FXP_RFA_STATUS_ALIGN)) {
1951	m_freem(m);
1952	fxp_add_rfabuf(sc, rxp);
1953	continue;
1954	}
1955
1956	m->m_pkthdr.len = m->m_len = total_len;
1957	m->m_pkthdr.rcvif = ifp;
1958
1959	/* Do IP checksum checking. */
1960	if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1961	fxp_rxcsum(sc, ifp, m, status, total_len);
1962	if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
1963	(status & FXP_RFA_STATUS_VLAN) != 0) {
1964	m->m_pkthdr.ether_vtag =
1965	ntohs(rfa->rfax_vlan_id);
1966	m->m_flags \|= M_VLANTAG;
1967	}
1968	/*
1969	* Drop locks before calling if_input() since it
1970	* may re-enter fxp_start() in the netisr case.
1971	* This would result in a lock reversal. Better
1972	* performance might be obtained by chaining all
1973	* packets received, dropping the lock, and then
1974	* calling if_input() on each one.
1975	*/
1976	FXP_UNLOCK(sc);
1977	(*ifp->if_input)(ifp, m);
1978	FXP_LOCK(sc);
1979	rx_npkts++;
1980	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1981	return (rx_npkts);
1982	} else {
1983	/* Reuse RFA and loaded DMA map. */
1984	ifp->if_iqdrops++;
1985	fxp_discard_rfabuf(sc, rxp);
1986	}
1987	fxp_add_rfabuf(sc, rxp);
1988	}
1989	if (rnr) {
1990	fxp_scb_wait(sc);
1991	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1992	sc->fxp_desc.rx_head->rx_addr);
1993	fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1994	}
1995	return (rx_npkts);
1996	}
1997
1998	static void
1999	fxp_update_stats(struct fxp_softc *sc)
2000	{
2001	struct ifnet *ifp = sc->ifp;
2002	struct fxp_stats *sp = sc->fxp_stats;
2003	struct fxp_hwstats *hsp;
2004	uint32_t *status;
2005
2006	FXP_LOCK_ASSERT(sc, MA_OWNED);
2007
2008	bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2009	BUS_DMASYNC_POSTREAD \| BUS_DMASYNC_POSTWRITE);
2010	/* Update statistical counters. */
2011	if (sc->revision >= FXP_REV_82559_A0)
2012	status = &sp->completion_status;
2013	else if (sc->revision >= FXP_REV_82558_A4)
2014	status = (uint32_t *)&sp->tx_tco;
2015	else
2016	status = &sp->tx_pause;
2017	if (*status == htole32(FXP_STATS_DR_COMPLETE)) {
2018	hsp = &sc->fxp_hwstats;
2019	hsp->tx_good += le32toh(sp->tx_good);
2020	hsp->tx_maxcols += le32toh(sp->tx_maxcols);
2021	hsp->tx_latecols += le32toh(sp->tx_latecols);
2022	hsp->tx_underruns += le32toh(sp->tx_underruns);
2023	hsp->tx_lostcrs += le32toh(sp->tx_lostcrs);
2024	hsp->tx_deffered += le32toh(sp->tx_deffered);
2025	hsp->tx_single_collisions += le32toh(sp->tx_single_collisions);
2026	hsp->tx_multiple_collisions +=
2027	le32toh(sp->tx_multiple_collisions);
2028	hsp->tx_total_collisions += le32toh(sp->tx_total_collisions);
2029	hsp->rx_good += le32toh(sp->rx_good);
2030	hsp->rx_crc_errors += le32toh(sp->rx_crc_errors);
2031	hsp->rx_alignment_errors += le32toh(sp->rx_alignment_errors);
2032	hsp->rx_rnr_errors += le32toh(sp->rx_rnr_errors);
2033	hsp->rx_overrun_errors += le32toh(sp->rx_overrun_errors);
2034	hsp->rx_cdt_errors += le32toh(sp->rx_cdt_errors);
2035	hsp->rx_shortframes += le32toh(sp->rx_shortframes);
2036	hsp->tx_pause += le32toh(sp->tx_pause);
2037	hsp->rx_pause += le32toh(sp->rx_pause);
2038	hsp->rx_controls += le32toh(sp->rx_controls);
2039	hsp->tx_tco += le16toh(sp->tx_tco);
2040	hsp->rx_tco += le16toh(sp->rx_tco);
2041
2042	ifp->if_opackets += le32toh(sp->tx_good);
2043	ifp->if_collisions += le32toh(sp->tx_total_collisions);
2044	if (sp->rx_good) {
2045	ifp->if_ipackets += le32toh(sp->rx_good);
2046	sc->rx_idle_secs = 0;
2047	} else if (sc->flags & FXP_FLAG_RXBUG) {
2048	/*
2049	* Receiver's been idle for another second.
2050	*/
2051	sc->rx_idle_secs++;
2052	}
2053	ifp->if_ierrors +=
2054	le32toh(sp->rx_crc_errors) +
2055	le32toh(sp->rx_alignment_errors) +
2056	le32toh(sp->rx_rnr_errors) +
2057	le32toh(sp->rx_overrun_errors);
2058	/*
2059	* If any transmit underruns occured, bump up the transmit
2060	* threshold by another 512 bytes (64 * 8).
2061	*/
2062	if (sp->tx_underruns) {
2063	ifp->if_oerrors += le32toh(sp->tx_underruns);
2064	if (tx_threshold < 192)
2065	tx_threshold += 64;
2066	}
2067	*status = 0;
2068	bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2069	BUS_DMASYNC_PREREAD \| BUS_DMASYNC_PREWRITE);
2070	}
2071	}
2072
2073	/*
2074	* Update packet in/out/collision statistics. The i82557 doesn't
2075	* allow you to access these counters without doing a fairly
2076	* expensive DMA to get _all_ of the statistics it maintains, so
2077	* we do this operation here only once per second. The statistics
2078	* counters in the kernel are updated from the previous dump-stats
2079	* DMA and then a new dump-stats DMA is started. The on-chip
2080	* counters are zeroed when the DMA completes. If we can't start
2081	* the DMA immediately, we don't wait - we just prepare to read
2082	* them again next time.
2083	*/
2084	static void
2085	fxp_tick(void *xsc)
2086	{
2087	struct fxp_softc *sc = xsc;
2088	struct ifnet *ifp = sc->ifp;
2089
2090	FXP_LOCK_ASSERT(sc, MA_OWNED);
2091
2092	/* Update statistical counters. */
2093	fxp_update_stats(sc);
2094
2095	/*
2096	* Release any xmit buffers that have completed DMA. This isn't
2097	* strictly necessary to do here, but it's advantagous for mbufs
2098	* with external storage to be released in a timely manner rather
2099	* than being defered for a potentially long time. This limits
2100	* the delay to a maximum of one second.
2101	*/
2102	fxp_txeof(sc);
2103
2104	/*
2105	* If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
2106	* then assume the receiver has locked up and attempt to clear
2107	* the condition by reprogramming the multicast filter. This is
2108	* a work-around for a bug in the 82557 where the receiver locks
2109	* up if it gets certain types of garbage in the syncronization
2110	* bits prior to the packet header. This bug is supposed to only
2111	* occur in 10Mbps mode, but has been seen to occur in 100Mbps
2112	* mode as well (perhaps due to a 10/100 speed transition).
2113	*/
2114	if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
2115	sc->rx_idle_secs = 0;
2116	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2117	fxp_init_body(sc, 1);
2118	return;
2119	}
2120	/*
2121	* If there is no pending command, start another stats
2122	* dump. Otherwise punt for now.
2123	*/
2124	if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
2125	/*
2126	* Start another stats dump.
2127	*/
2128	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
2129	}
2130	if (sc->miibus != NULL)
2131	mii_tick(device_get_softc(sc->miibus));
2132
2133	/*
2134	* Check that chip hasn't hung.
2135	*/
2136	fxp_watchdog(sc);
2137
2138	/*
2139	* Schedule another timeout one second from now.
2140	*/
2141	callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
2142	}
2143
2144	/*
2145	* Stop the interface. Cancels the statistics updater and resets
2146	* the interface.
2147	*/
2148	static void
2149	fxp_stop(struct fxp_softc *sc)
2150	{
2151	struct ifnet *ifp = sc->ifp;
2152	struct fxp_tx *txp;
2153	int i;
2154
2155	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING \| IFF_DRV_OACTIVE);
2156	sc->watchdog_timer = 0;
2157
2158	/*
2159	* Cancel stats updater.
2160	*/
2161	callout_stop(&sc->stat_ch);
2162
2163	/*
2164	* Preserve PCI configuration, configure, IA/multicast
2165	* setup and put RU and CU into idle state.
2166	*/
2167	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
2168	DELAY(50);
2169	/* Disable interrupts. */
2170	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
2171
2172	fxp_update_stats(sc);
2173
2174	/*
2175	* Release any xmit buffers.
2176	*/
2177	txp = sc->fxp_desc.tx_list;
2178	if (txp != NULL) {
2179	for (i = 0; i < FXP_NTXCB; i++) {
2180	if (txp[i].tx_mbuf != NULL) {
2181	bus_dmamap_sync(sc->fxp_txmtag, txp[i].tx_map,
2182	BUS_DMASYNC_POSTWRITE);
2183	bus_dmamap_unload(sc->fxp_txmtag,
2184	txp[i].tx_map);
2185	m_freem(txp[i].tx_mbuf);
2186	txp[i].tx_mbuf = NULL;
2187	/* clear this to reset csum offload bits */
2188	txp[i].tx_cb->tbd[0].tb_addr = 0;
2189	}
2190	}
2191	}
2192	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2193	BUS_DMASYNC_PREREAD \| BUS_DMASYNC_PREWRITE);
2194	sc->tx_queued = 0;
2195	}
2196
2197	/*
2198	* Watchdog/transmission transmit timeout handler. Called when a
2199	* transmission is started on the interface, but no interrupt is
2200	* received before the timeout. This usually indicates that the
2201	* card has wedged for some reason.
2202	*/
2203	static void
2204	fxp_watchdog(struct fxp_softc *sc)
2205	{
2206
2207	FXP_LOCK_ASSERT(sc, MA_OWNED);
2208
2209	if (sc->watchdog_timer == 0 \|\| --sc->watchdog_timer)
2210	return;
2211
2212	device_printf(sc->dev, "device timeout\n");
2213	sc->ifp->if_oerrors++;
2214
2215	fxp_init_body(sc, 1);
2216	}
2217
2218	/*
2219	* Acquire locks and then call the real initialization function. This
2220	* is necessary because ether_ioctl() calls if_init() and this would
2221	* result in mutex recursion if the mutex was held.
2222	*/
2223	static void
2224	fxp_init(void *xsc)
2225	{
2226	struct fxp_softc *sc = xsc;
2227
2228	FXP_LOCK(sc);
2229	fxp_init_body(sc, 1);
2230	FXP_UNLOCK(sc);
2231	}
2232
2233	/*
2234	* Perform device initialization. This routine must be called with the
2235	* softc lock held.
2236	*/
2237	static void
2238	fxp_init_body(struct fxp_softc *sc, int setmedia)
2239	{
2240	struct ifnet *ifp = sc->ifp;
2241	struct mii_data *mii;
2242	struct fxp_cb_config *cbp;
2243	struct fxp_cb_ias *cb_ias;
2244	struct fxp_cb_tx *tcbp;
2245	struct fxp_tx *txp;
2246	int i, prm;
2247
2248	FXP_LOCK_ASSERT(sc, MA_OWNED);
2249	/*
2250	* Cancel any pending I/O
2251	*/
2252	fxp_stop(sc);
2253
2254	/*
2255	* Issue software reset, which also unloads the microcode.
2256	*/
2257	sc->flags &= ~FXP_FLAG_UCODE;
2258	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
2259	DELAY(50);
2260
2261	prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
2262
2263	/*
2264	* Initialize base of CBL and RFA memory. Loading with zero
2265	* sets it up for regular linear addressing.
2266	*/
2267	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
2268	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
2269
2270	fxp_scb_wait(sc);
2271	fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
2272
2273	/*
2274	* Initialize base of dump-stats buffer.
2275	*/
2276	fxp_scb_wait(sc);
2277	bzero(sc->fxp_stats, sizeof(struct fxp_stats));
2278	bus_dmamap_sync(sc->fxp_stag, sc->fxp_smap,
2279	BUS_DMASYNC_PREREAD \| BUS_DMASYNC_PREWRITE);
2280	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->stats_addr);
2281	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
2282
2283	/*
2284	* Attempt to load microcode if requested.
2285	* For ICH based controllers do not load microcode.
2286	*/
2287	if (sc->ident->ich == 0) {
2288	if (ifp->if_flags & IFF_LINK0 &&
2289	(sc->flags & FXP_FLAG_UCODE) == 0)
2290	fxp_load_ucode(sc);
2291	}
2292
2293	/*
2294	* Set IFF_ALLMULTI status. It's needed in configure action
2295	* command.
2296	*/
2297	fxp_mc_addrs(sc);
2298
2299	/*
2300	* We temporarily use memory that contains the TxCB list to
2301	* construct the config CB. The TxCB list memory is rebuilt
2302	* later.
2303	*/
2304	cbp = (struct fxp_cb_config *)sc->fxp_desc.cbl_list;
2305
2306	/*
2307	* This bcopy is kind of disgusting, but there are a bunch of must be
2308	* zero and must be one bits in this structure and this is the easiest
2309	* way to initialize them all to proper values.
2310	*/
2311	bcopy(fxp_cb_config_template, cbp, sizeof(fxp_cb_config_template));
2312
2313	cbp->cb_status = 0;
2314	cbp->cb_command = htole16(FXP_CB_COMMAND_CONFIG \|
2315	FXP_CB_COMMAND_EL);
2316	cbp->link_addr = 0xffffffff; /* (no) next command */
2317	cbp->byte_count = sc->flags & FXP_FLAG_EXT_RFA ? 32 : 22;
2318	cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
2319	cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
2320	cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
2321	cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
2322	cbp->type_enable = 0; /* actually reserved */
2323	cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
2324	cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
2325	cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
2326	cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
2327	cbp->dma_mbce = 0; /* (disable) dma max counters */
2328	cbp->late_scb = 0; /* (don't) defer SCB update */
2329	cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */
2330	cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */
2331	cbp->ci_int = 1; /* interrupt on CU idle */
2332	cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
2333	cbp->ext_stats_dis = 1; /* disable extended counters */
2334	cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */
2335	cbp->save_bf = sc->flags & FXP_FLAG_SAVE_BAD ? 1 : prm;
2336	cbp->disc_short_rx = !prm; /* discard short packets */
2337	cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */
2338	cbp->two_frames = 0; /* do not limit FIFO to 2 frames */
2339	cbp->dyn_tbd = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2340	cbp->ext_rfa = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2341	cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
2342	cbp->csma_dis = 0; /* (don't) disable link */
2343	cbp->tcp_udp_cksum = ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0 &&
2344	(ifp->if_capenable & IFCAP_RXCSUM) != 0) ? 1 : 0;
2345	cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */
2346	cbp->link_wake_en = 0; /* (don't) assert PME# on link change */
2347	cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */
2348	cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */
2349	cbp->nsai = 1; /* (don't) disable source addr insert */
2350	cbp->preamble_length = 2; /* (7 byte) preamble */
2351	cbp->loopback = 0; /* (don't) loopback */
2352	cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
2353	cbp->linear_pri_mode = 0; /* (wait after xmit only) */
2354	cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
2355	cbp->promiscuous = prm; /* promiscuous mode */
2356	cbp->bcast_disable = 0; /* (don't) disable broadcasts */
2357	cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/
2358	cbp->ignore_ul = 0; /* consider U/L bit in IA matching */
2359	cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */
2360	cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
2361
2362	cbp->stripping = !prm; /* truncate rx packet to byte count */
2363	cbp->padding = 1; /* (do) pad short tx packets */
2364	cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
2365	cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
2366	cbp->ia_wake_en = 0; /* (don't) wake up on address match */
2367	cbp->magic_pkt_dis = sc->flags & FXP_FLAG_WOL ? 0 : 1;
2368	cbp->force_fdx = 0; /* (don't) force full duplex */
2369	cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
2370	cbp->multi_ia = 0; /* (don't) accept multiple IAs */
2371	cbp->mc_all = ifp->if_flags & IFF_ALLMULTI ? 1 : prm;
2372	cbp->gamla_rx = sc->flags & FXP_FLAG_EXT_RFA ? 1 : 0;
2373	cbp->vlan_strip_en = ((sc->flags & FXP_FLAG_EXT_RFA) != 0 &&
2374	(ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) ? 1 : 0;
2375
2376	if (sc->revision == FXP_REV_82557) {
2377	/*
2378	* The 82557 has no hardware flow control, the values
2379	* below are the defaults for the chip.
2380	*/
2381	cbp->fc_delay_lsb = 0;
2382	cbp->fc_delay_msb = 0x40;
2383	cbp->pri_fc_thresh = 3;
2384	cbp->tx_fc_dis = 0;
2385	cbp->rx_fc_restop = 0;
2386	cbp->rx_fc_restart = 0;
2387	cbp->fc_filter = 0;
2388	cbp->pri_fc_loc = 1;
2389	} else {
2390	/* Set pause RX FIFO threshold to 1KB. */
2391	CSR_WRITE_1(sc, FXP_CSR_FC_THRESH, 1);
2392	/* Set pause time. */
2393	cbp->fc_delay_lsb = 0xff;
2394	cbp->fc_delay_msb = 0xff;
2395	cbp->pri_fc_thresh = 3;
2396	mii = device_get_softc(sc->miibus);
2397	if ((IFM_OPTIONS(mii->mii_media_active) &
2398	IFM_ETH_TXPAUSE) != 0)
2399	/* enable transmit FC */
2400	cbp->tx_fc_dis = 0;
2401	else
2402	/* disable transmit FC */
2403	cbp->tx_fc_dis = 1;
2404	if ((IFM_OPTIONS(mii->mii_media_active) &
2405	IFM_ETH_RXPAUSE) != 0) {
2406	/* enable FC restart/restop frames */
2407	cbp->rx_fc_restart = 1;
2408	cbp->rx_fc_restop = 1;
2409	} else {
2410	/* disable FC restart/restop frames */
2411	cbp->rx_fc_restart = 0;
2412	cbp->rx_fc_restop = 0;
2413	}
2414	cbp->fc_filter = !prm; /* drop FC frames to host */
2415	cbp->pri_fc_loc = 1; /* FC pri location (byte31) */
2416	}
2417
2418	/* Enable 82558 and 82559 extended statistics functionality. */
2419	if (sc->revision >= FXP_REV_82558_A4) {
2420	if (sc->revision >= FXP_REV_82559_A0) {
2421	/*
2422	* Extend configuration table size to 32
2423	* to include TCO configuration.
2424	*/
2425	cbp->byte_count = 32;
2426	cbp->ext_stats_dis = 1;
2427	/* Enable TCO stats. */
2428	cbp->tno_int_or_tco_en = 1;
2429	cbp->gamla_rx = 1;
2430	} else
2431	cbp->ext_stats_dis = 0;
2432	}
2433
2434	/*
2435	* Start the config command/DMA.
2436	*/
2437	fxp_scb_wait(sc);
2438	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2439	BUS_DMASYNC_PREREAD \| BUS_DMASYNC_PREWRITE);
2440	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2441	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2442	/* ...and wait for it to complete. */
2443	fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
2444
2445	/*
2446	* Now initialize the station address. Temporarily use the TxCB
2447	* memory area like we did above for the config CB.
2448	*/
2449	cb_ias = (struct fxp_cb_ias *)sc->fxp_desc.cbl_list;
2450	cb_ias->cb_status = 0;
2451	cb_ias->cb_command = htole16(FXP_CB_COMMAND_IAS \| FXP_CB_COMMAND_EL);
2452	cb_ias->link_addr = 0xffffffff;
2453	bcopy(IF_LLADDR(sc->ifp), cb_ias->macaddr, ETHER_ADDR_LEN);
2454
2455	/*
2456	* Start the IAS (Individual Address Setup) command/DMA.
2457	*/
2458	fxp_scb_wait(sc);
2459	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2460	BUS_DMASYNC_PREREAD \| BUS_DMASYNC_PREWRITE);
2461	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2462	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2463	/* ...and wait for it to complete. */
2464	fxp_dma_wait(sc, &cb_ias->cb_status, sc->cbl_tag, sc->cbl_map);
2465
2466	/*
2467	* Initialize the multicast address list.
2468	*/
2469	fxp_mc_setup(sc);
2470
2471	/*
2472	* Initialize transmit control block (TxCB) list.
2473	*/
2474	txp = sc->fxp_desc.tx_list;
2475	tcbp = sc->fxp_desc.cbl_list;
2476	bzero(tcbp, FXP_TXCB_SZ);
2477	for (i = 0; i < FXP_NTXCB; i++) {
2478	txp[i].tx_mbuf = NULL;
2479	tcbp[i].cb_status = htole16(FXP_CB_STATUS_C \| FXP_CB_STATUS_OK);
2480	tcbp[i].cb_command = htole16(FXP_CB_COMMAND_NOP);
2481	tcbp[i].link_addr = htole32(sc->fxp_desc.cbl_addr +
2482	(((i + 1) & FXP_TXCB_MASK) * sizeof(struct fxp_cb_tx)));
2483	if (sc->flags & FXP_FLAG_EXT_TXCB)
2484	tcbp[i].tbd_array_addr =
2485	htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[2]));
2486	else
2487	tcbp[i].tbd_array_addr =
2488	htole32(FXP_TXCB_DMA_ADDR(sc, &tcbp[i].tbd[0]));
2489	txp[i].tx_next = &txp[(i + 1) & FXP_TXCB_MASK];
2490	}
2491	/*
2492	* Set the suspend flag on the first TxCB and start the control
2493	* unit. It will execute the NOP and then suspend.
2494	*/
2495	tcbp->cb_command = htole16(FXP_CB_COMMAND_NOP \| FXP_CB_COMMAND_S);
2496	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
2497	BUS_DMASYNC_PREREAD \| BUS_DMASYNC_PREWRITE);
2498	sc->fxp_desc.tx_first = sc->fxp_desc.tx_last = txp;
2499	sc->tx_queued = 1;
2500
2501	fxp_scb_wait(sc);
2502	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
2503	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2504
2505	/*
2506	* Initialize receiver buffer area - RFA.
2507	*/
2508	fxp_scb_wait(sc);
2509	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.rx_head->rx_addr);
2510	fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
2511
2512	if (sc->miibus != NULL && setmedia != 0)
2513	mii_mediachg(device_get_softc(sc->miibus));
2514
2515	ifp->if_drv_flags \|= IFF_DRV_RUNNING;
2516	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2517
2518	/*
2519	* Enable interrupts.
2520	*/
2521	#ifdef DEVICE_POLLING
2522	/*
2523	* ... but only do that if we are not polling. And because (presumably)
2524	* the default is interrupts on, we need to disable them explicitly!
2525	*/
2526	if (ifp->if_capenable & IFCAP_POLLING )
2527	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
2528	else
2529	#endif /* DEVICE_POLLING */
2530	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2531
2532	/*
2533	* Start stats updater.
2534	*/
2535	callout_reset(&sc->stat_ch, hz, fxp_tick, sc);
2536	}
2537
2538	static int
2539	fxp_serial_ifmedia_upd(struct ifnet *ifp)
2540	{
2541
2542	return (0);
2543	}
2544
2545	static void
2546	fxp_serial_ifmedia_sts(struct ifnet ifp, struct ifmediareq ifmr)
2547	{
2548
2549	ifmr->ifm_active = IFM_ETHER\|IFM_MANUAL;
2550	}
2551
2552	/*
2553	* Change media according to request.
2554	*/
2555	static int
2556	fxp_ifmedia_upd(struct ifnet *ifp)
2557	{
2558	struct fxp_softc *sc = ifp->if_softc;
2559	struct mii_data *mii;
2560
2561	mii = device_get_softc(sc->miibus);
2562	FXP_LOCK(sc);
2563	if (mii->mii_instance) {
2564	struct mii_softc *miisc;
2565	LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2566	mii_phy_reset(miisc);
2567	}
2568	mii_mediachg(mii);
2569	FXP_UNLOCK(sc);
2570	return (0);
2571	}
2572
2573	/*
2574	* Notify the world which media we're using.
2575	*/
2576	static void
2577	fxp_ifmedia_sts(struct ifnet ifp, struct ifmediareq ifmr)
2578	{
2579	struct fxp_softc *sc = ifp->if_softc;
2580	struct mii_data *mii;
2581
2582	mii = device_get_softc(sc->miibus);
2583	FXP_LOCK(sc);
2584	mii_pollstat(mii);
2585	ifmr->ifm_active = mii->mii_media_active;
2586	ifmr->ifm_status = mii->mii_media_status;
2587
2588	if (IFM_SUBTYPE(ifmr->ifm_active) == IFM_10_T &&
2589	sc->flags & FXP_FLAG_CU_RESUME_BUG)
2590	sc->cu_resume_bug = 1;
2591	else
2592	sc->cu_resume_bug = 0;
2593	FXP_UNLOCK(sc);
2594	}
2595
2596	/*
2597	* Add a buffer to the end of the RFA buffer list.
2598	* Return 0 if successful, 1 for failure. A failure results in
2599	* reusing the RFA buffer.
2600	* The RFA struct is stuck at the beginning of mbuf cluster and the
2601	* data pointer is fixed up to point just past it.
2602	*/
2603	static int
2604	fxp_new_rfabuf(struct fxp_softc sc, struct fxp_rx rxp)
2605	{
2606	struct mbuf *m;
2607	struct fxp_rfa *rfa;
2608	bus_dmamap_t tmp_map;
2609	int error;
2610
2611	m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2612	if (m == NULL)
2613	return (ENOBUFS);
2614
2615	/*
2616	* Move the data pointer up so that the incoming data packet
2617	* will be 32-bit aligned.
2618	*/
2619	m->m_data += RFA_ALIGNMENT_FUDGE;
2620
2621	/*
2622	* Get a pointer to the base of the mbuf cluster and move
2623	* data start past it.
2624	*/
2625	rfa = mtod(m, struct fxp_rfa *);
2626	m->m_data += sc->rfa_size;
2627	rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE);
2628
2629	rfa->rfa_status = 0;
2630	rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL);
2631	rfa->actual_size = 0;
2632	m->m_len = m->m_pkthdr.len = MCLBYTES - RFA_ALIGNMENT_FUDGE -
2633	sc->rfa_size;
2634
2635	/*
2636	* Initialize the rest of the RFA. Note that since the RFA
2637	* is misaligned, we cannot store values directly. We're thus
2638	* using the le32enc() function which handles endianness and
2639	* is also alignment-safe.
2640	*/
2641	le32enc(&rfa->link_addr, 0xffffffff);
2642	le32enc(&rfa->rbd_addr, 0xffffffff);
2643
2644	/* Map the RFA into DMA memory. */
2645	error = bus_dmamap_load(sc->fxp_rxmtag, sc->spare_map, rfa,
2646	MCLBYTES - RFA_ALIGNMENT_FUDGE, fxp_dma_map_addr,
2647	&rxp->rx_addr, BUS_DMA_NOWAIT);
2648	if (error) {
2649	m_freem(m);
2650	return (error);
2651	}
2652
2653	if (rxp->rx_mbuf != NULL)
2654	bus_dmamap_unload(sc->fxp_rxmtag, rxp->rx_map);
2655	tmp_map = sc->spare_map;
2656	sc->spare_map = rxp->rx_map;
2657	rxp->rx_map = tmp_map;
2658	rxp->rx_mbuf = m;
2659
2660	bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
2661	BUS_DMASYNC_PREREAD \| BUS_DMASYNC_PREWRITE);
2662	return (0);
2663	}
2664
2665	static void
2666	fxp_add_rfabuf(struct fxp_softc sc, struct fxp_rx rxp)
2667	{
2668	struct fxp_rfa *p_rfa;
2669	struct fxp_rx *p_rx;
2670
2671	/*
2672	* If there are other buffers already on the list, attach this
2673	* one to the end by fixing up the tail to point to this one.
2674	*/
2675	if (sc->fxp_desc.rx_head != NULL) {
2676	p_rx = sc->fxp_desc.rx_tail;
2677	p_rfa = (struct fxp_rfa *)
2678	(p_rx->rx_mbuf->m_ext.ext_buf + RFA_ALIGNMENT_FUDGE);
2679	p_rx->rx_next = rxp;
2680	le32enc(&p_rfa->link_addr, rxp->rx_addr);
2681	p_rfa->rfa_control = 0;
2682	bus_dmamap_sync(sc->fxp_rxmtag, p_rx->rx_map,
2683	BUS_DMASYNC_PREREAD \| BUS_DMASYNC_PREWRITE);
2684	} else {
2685	rxp->rx_next = NULL;
2686	sc->fxp_desc.rx_head = rxp;
2687	}
2688	sc->fxp_desc.rx_tail = rxp;
2689	}
2690
2691	static void
2692	fxp_discard_rfabuf(struct fxp_softc sc, struct fxp_rx rxp)
2693	{
2694	struct mbuf *m;
2695	struct fxp_rfa *rfa;
2696
2697	m = rxp->rx_mbuf;
2698	m->m_data = m->m_ext.ext_buf;
2699	/*
2700	* Move the data pointer up so that the incoming data packet
2701	* will be 32-bit aligned.
2702	*/
2703	m->m_data += RFA_ALIGNMENT_FUDGE;
2704
2705	/*
2706	* Get a pointer to the base of the mbuf cluster and move
2707	* data start past it.
2708	*/
2709	rfa = mtod(m, struct fxp_rfa *);
2710	m->m_data += sc->rfa_size;
2711	rfa->size = htole16(MCLBYTES - sc->rfa_size - RFA_ALIGNMENT_FUDGE);
2712
2713	rfa->rfa_status = 0;
2714	rfa->rfa_control = htole16(FXP_RFA_CONTROL_EL);
2715	rfa->actual_size = 0;
2716
2717	/*
2718	* Initialize the rest of the RFA. Note that since the RFA
2719	* is misaligned, we cannot store values directly. We're thus
2720	* using the le32enc() function which handles endianness and
2721	* is also alignment-safe.
2722	*/
2723	le32enc(&rfa->link_addr, 0xffffffff);
2724	le32enc(&rfa->rbd_addr, 0xffffffff);
2725
2726	bus_dmamap_sync(sc->fxp_rxmtag, rxp->rx_map,
2727	BUS_DMASYNC_PREREAD \| BUS_DMASYNC_PREWRITE);
2728	}
2729
2730	static int
2731	fxp_miibus_readreg(device_t dev, int phy, int reg)
2732	{
2733	struct fxp_softc *sc = device_get_softc(dev);
2734	int count = 10000;
2735	int value;
2736
2737	CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2738	(FXP_MDI_READ << 26) \| (reg << 16) \| (phy << 21));
2739
2740	while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
2741	&& count--)
2742	DELAY(10);
2743
2744	if (count <= 0)
2745	device_printf(dev, "fxp_miibus_readreg: timed out\n");
2746
2747	return (value & 0xffff);
2748	}
2749
2750	static int
2751	fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
2752	{
2753	struct fxp_softc *sc = device_get_softc(dev);
2754	int count = 10000;
2755
2756	CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
2757	(FXP_MDI_WRITE << 26) \| (reg << 16) \| (phy << 21) \|
2758	(value & 0xffff));
2759
2760	while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
2761	count--)
2762	DELAY(10);
2763
2764	if (count <= 0)
2765	device_printf(dev, "fxp_miibus_writereg: timed out\n");
2766	return (0);
2767	}
2768
2769	static void
2770	fxp_miibus_statchg(device_t dev)
2771	{
2772	struct fxp_softc *sc;
2773	struct mii_data *mii;
2774	struct ifnet *ifp;
2775
2776	sc = device_get_softc(dev);
2777	mii = device_get_softc(sc->miibus);
2778	ifp = sc->ifp;
2779	if (mii == NULL \|\| ifp == NULL \|\|
2780	(ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 \|\|
2781	(mii->mii_media_status & (IFM_AVALID \| IFM_ACTIVE)) !=
2782	(IFM_AVALID \| IFM_ACTIVE))
2783	return;
2784
2785	/*
2786	* Call fxp_init_body in order to adjust the flow control settings.
2787	* Note that the 82557 doesn't support hardware flow control.
2788	*/
2789	if (sc->revision == FXP_REV_82557)
2790	return;
2791	fxp_init_body(sc, 0);
2792	}
2793
2794	static int
2795	fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2796	{
2797	struct fxp_softc *sc = ifp->if_softc;
2798	struct ifreq ifr = (struct ifreq )data;
2799	struct mii_data *mii;
2800	int flag, mask, error = 0, reinit;
2801
2802	switch (command) {
2803	case SIOCSIFFLAGS:
2804	FXP_LOCK(sc);
2805	/*
2806	* If interface is marked up and not running, then start it.
2807	* If it is marked down and running, stop it.
2808	* XXX If it's up then re-initialize it. This is so flags
2809	* such as IFF_PROMISC are handled.
2810	*/
2811	if (ifp->if_flags & IFF_UP) {
2812	if (((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) &&
2813	((ifp->if_flags ^ sc->if_flags) &
2814	(IFF_PROMISC \| IFF_ALLMULTI \| IFF_LINK0)) != 0)
2815	fxp_init_body(sc, 1);
2816	else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
2817	fxp_init_body(sc, 1);
2818	} else {
2819	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2820	fxp_stop(sc);
2821	}
2822	sc->if_flags = ifp->if_flags;
2823	FXP_UNLOCK(sc);
2824	break;
2825
2826	case SIOCADDMULTI:
2827	case SIOCDELMULTI:
2828	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2829	fxp_init(sc);
2830	break;
2831
2832	case SIOCSIFMEDIA:
2833	case SIOCGIFMEDIA:
2834	if (sc->miibus != NULL) {
2835	mii = device_get_softc(sc->miibus);
2836	error = ifmedia_ioctl(ifp, ifr,
2837	&mii->mii_media, command);
2838	} else {
2839	error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2840	}
2841	break;
2842
2843	case SIOCSIFCAP:
2844	reinit = 0;
2845	mask = ifp->if_capenable ^ ifr->ifr_reqcap;
2846	#ifdef DEVICE_POLLING
2847	if (mask & IFCAP_POLLING) {
2848	if (ifr->ifr_reqcap & IFCAP_POLLING) {
2849	error = ether_poll_register(fxp_poll, ifp);
2850	if (error)
2851	return(error);
2852	FXP_LOCK(sc);
2853	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL,
2854	FXP_SCB_INTR_DISABLE);
2855	ifp->if_capenable \|= IFCAP_POLLING;
2856	FXP_UNLOCK(sc);
2857	} else {
2858	error = ether_poll_deregister(ifp);
2859	/* Enable interrupts in any case */
2860	FXP_LOCK(sc);
2861	CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
2862	ifp->if_capenable &= ~IFCAP_POLLING;
2863	FXP_UNLOCK(sc);
2864	}
2865	}
2866	#endif
2867	FXP_LOCK(sc);
2868	if ((mask & IFCAP_TXCSUM) != 0 &&
2869	(ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
2870	ifp->if_capenable ^= IFCAP_TXCSUM;
2871	if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
2872	ifp->if_hwassist \|= FXP_CSUM_FEATURES;
2873	else
2874	ifp->if_hwassist &= ~FXP_CSUM_FEATURES;
2875	}
2876	if ((mask & IFCAP_RXCSUM) != 0 &&
2877	(ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
2878	ifp->if_capenable ^= IFCAP_RXCSUM;
2879	if ((sc->flags & FXP_FLAG_82559_RXCSUM) != 0)
2880	reinit++;
2881	}
2882	if ((mask & IFCAP_TSO4) != 0 &&
2883	(ifp->if_capabilities & IFCAP_TSO4) != 0) {
2884	ifp->if_capenable ^= IFCAP_TSO4;
2885	if ((ifp->if_capenable & IFCAP_TSO4) != 0)
2886	ifp->if_hwassist \|= CSUM_TSO;
2887	else
2888	ifp->if_hwassist &= ~CSUM_TSO;
2889	}
2890	if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2891	(ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
2892	ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2893	if ((mask & IFCAP_VLAN_MTU) != 0 &&
2894	(ifp->if_capabilities & IFCAP_VLAN_MTU) != 0) {
2895	ifp->if_capenable ^= IFCAP_VLAN_MTU;
2896	if (sc->revision != FXP_REV_82557)
2897	flag = FXP_FLAG_LONG_PKT_EN;
2898	else /* a hack to get long frames on the old chip */
2899	flag = FXP_FLAG_SAVE_BAD;
2900	sc->flags ^= flag;
2901	if (ifp->if_flags & IFF_UP)
2902	reinit++;
2903	}
2904	if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
2905	(ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
2906	ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
2907	if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
2908	(ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
2909	ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
2910	if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2911	(ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
2912	ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2913	if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
2914	ifp->if_capenable &=
2915	~(IFCAP_VLAN_HWTSO \| IFCAP_VLAN_HWCSUM);
2916	reinit++;
2917	}
2918	if (reinit > 0 && ifp->if_flags & IFF_UP)
2919	fxp_init_body(sc, 1);
2920	FXP_UNLOCK(sc);
2921	VLAN_CAPABILITIES(ifp);
2922	break;
2923
2924	default:
2925	error = ether_ioctl(ifp, command, data);
2926	}
2927	return (error);
2928	}
2929
2930	/*
2931	* Fill in the multicast address list and return number of entries.
2932	*/
2933	static int
2934	fxp_mc_addrs(struct fxp_softc *sc)
2935	{
2936	struct fxp_cb_mcs *mcsp = sc->mcsp;
2937	struct ifnet *ifp = sc->ifp;
2938	struct ifmultiaddr *ifma;
2939	int nmcasts;
2940
2941	nmcasts = 0;
2942	if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
2943	if_maddr_rlock(ifp);
2944	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2945	if (ifma->ifma_addr->sa_family != AF_LINK)
2946	continue;
2947	if (nmcasts >= MAXMCADDR) {
2948	ifp->if_flags \|= IFF_ALLMULTI;
2949	nmcasts = 0;
2950	break;
2951	}
2952	bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
2953	&sc->mcsp->mc_addr[nmcasts][0], ETHER_ADDR_LEN);
2954	nmcasts++;
2955	}
2956	if_maddr_runlock(ifp);
2957	}
2958	mcsp->mc_cnt = htole16(nmcasts * ETHER_ADDR_LEN);
2959	return (nmcasts);
2960	}
2961
2962	/*
2963	* Program the multicast filter.
2964	*
2965	* We have an artificial restriction that the multicast setup command
2966	* must be the first command in the chain, so we take steps to ensure
2967	* this. By requiring this, it allows us to keep up the performance of
2968	* the pre-initialized command ring (esp. link pointers) by not actually
2969	* inserting the mcsetup command in the ring - i.e. its link pointer
2970	* points to the TxCB ring, but the mcsetup descriptor itself is not part
2971	* of it. We then can do 'CU_START' on the mcsetup descriptor and have it
2972	* lead into the regular TxCB ring when it completes.
2973	*/
2974	static void
2975	fxp_mc_setup(struct fxp_softc *sc)
2976	{
2977	struct fxp_cb_mcs *mcsp;
2978	int count;
2979
2980	FXP_LOCK_ASSERT(sc, MA_OWNED);
2981
2982	mcsp = sc->mcsp;
2983	mcsp->cb_status = 0;
2984	mcsp->cb_command = htole16(FXP_CB_COMMAND_MCAS \| FXP_CB_COMMAND_EL);
2985	mcsp->link_addr = 0xffffffff;
2986	fxp_mc_addrs(sc);
2987
2988	/*
2989	* Wait until command unit is idle. This should never be the
2990	* case when nothing is queued, but make sure anyway.
2991	*/
2992	count = 100;
2993	while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) !=
2994	FXP_SCB_CUS_IDLE && --count)
2995	DELAY(10);
2996	if (count == 0) {
2997	device_printf(sc->dev, "command queue timeout\n");
2998	return;
2999	}
3000
3001	/*
3002	* Start the multicast setup command.
3003	*/
3004	fxp_scb_wait(sc);
3005	bus_dmamap_sync(sc->mcs_tag, sc->mcs_map,
3006	BUS_DMASYNC_PREREAD \| BUS_DMASYNC_PREWRITE);
3007	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->mcs_addr);
3008	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
3009	/* ...and wait for it to complete. */
3010	fxp_dma_wait(sc, &mcsp->cb_status, sc->mcs_tag, sc->mcs_map);
3011	}
3012
3013	static uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE;
3014	static uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE;
3015	static uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE;
3016	static uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE;
3017	static uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE;
3018	static uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE;
3019	static uint32_t fxp_ucode_d102e[] = D102_E_RCVBUNDLE_UCODE;
3020
3021	#define UCODE(x) x, sizeof(x)/sizeof(uint32_t)
3022
3023	static const struct ucode {
3024	uint32_t revision;
3025	uint32_t *ucode;
3026	int length;
3027	u_short int_delay_offset;
3028	u_short bundle_max_offset;
3029	} const ucode_table[] = {
3030	{ FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 },
3031	{ FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 },
3032	{ FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma),
3033	D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD },
3034	{ FXP_REV_82559S_A, UCODE(fxp_ucode_d101s),
3035	D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD },
3036	{ FXP_REV_82550, UCODE(fxp_ucode_d102),
3037	D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD },
3038	{ FXP_REV_82550_C, UCODE(fxp_ucode_d102c),
3039	D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD },
3040	{ FXP_REV_82551_F, UCODE(fxp_ucode_d102e),
3041	D102_E_CPUSAVER_DWORD, D102_E_CPUSAVER_BUNDLE_MAX_DWORD },
3042	{ 0, NULL, 0, 0, 0 }
3043	};
3044
3045	static void
3046	fxp_load_ucode(struct fxp_softc *sc)
3047	{
3048	const struct ucode *uc;
3049	struct fxp_cb_ucode *cbp;
3050	int i;
3051
3052	for (uc = ucode_table; uc->ucode != NULL; uc++)
3053	if (sc->revision == uc->revision)
3054	break;
3055	if (uc->ucode == NULL)
3056	return;
3057	cbp = (struct fxp_cb_ucode *)sc->fxp_desc.cbl_list;
3058	cbp->cb_status = 0;
3059	cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE \| FXP_CB_COMMAND_EL);
3060	cbp->link_addr = 0xffffffff; /* (no) next command */
3061	for (i = 0; i < uc->length; i++)
3062	cbp->ucode[i] = htole32(uc->ucode[i]);
3063	if (uc->int_delay_offset)
3064	(uint16_t )&cbp->ucode[uc->int_delay_offset] =
3065	htole16(sc->tunable_int_delay + sc->tunable_int_delay / 2);
3066	if (uc->bundle_max_offset)
3067	(uint16_t )&cbp->ucode[uc->bundle_max_offset] =
3068	htole16(sc->tunable_bundle_max);
3069	/*
3070	* Download the ucode to the chip.
3071	*/
3072	fxp_scb_wait(sc);
3073	bus_dmamap_sync(sc->cbl_tag, sc->cbl_map,
3074	BUS_DMASYNC_PREREAD \| BUS_DMASYNC_PREWRITE);
3075	CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->fxp_desc.cbl_addr);
3076	fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
3077	/* ...and wait for it to complete. */
3078	fxp_dma_wait(sc, &cbp->cb_status, sc->cbl_tag, sc->cbl_map);
3079	device_printf(sc->dev,
3080	"Microcode loaded, int_delay: %d usec bundle_max: %d\n",
3081	sc->tunable_int_delay,
3082	uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max);
3083	sc->flags \|= FXP_FLAG_UCODE;
3084	}
3085
3086	#define FXP_SYSCTL_STAT_ADD(c, h, n, p, d) \
3087	SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
3088
3089	static void
3090	fxp_sysctl_node(struct fxp_softc *sc)
3091	{
3092	struct sysctl_ctx_list *ctx;
3093	struct sysctl_oid_list child, parent;
3094	struct sysctl_oid *tree;
3095	struct fxp_hwstats *hsp;
3096
3097	ctx = device_get_sysctl_ctx(sc->dev);
3098	child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
3099
3100	SYSCTL_ADD_PROC(ctx, child,
3101	OID_AUTO, "int_delay", CTLTYPE_INT \| CTLFLAG_RW,
3102	&sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I",
3103	"FXP driver receive interrupt microcode bundling delay");
3104	SYSCTL_ADD_PROC(ctx, child,
3105	OID_AUTO, "bundle_max", CTLTYPE_INT \| CTLFLAG_RW,
3106	&sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I",
3107	"FXP driver receive interrupt microcode bundle size limit");
3108	SYSCTL_ADD_INT(ctx, child,OID_AUTO, "rnr", CTLFLAG_RD, &sc->rnr, 0,
3109	"FXP RNR events");
3110
3111	/*
3112	* Pull in device tunables.
3113	*/
3114	sc->tunable_int_delay = TUNABLE_INT_DELAY;
3115	sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX;
3116	(void) resource_int_value(device_get_name(sc->dev),
3117	device_get_unit(sc->dev), "int_delay", &sc->tunable_int_delay);
3118	(void) resource_int_value(device_get_name(sc->dev),
3119	device_get_unit(sc->dev), "bundle_max", &sc->tunable_bundle_max);
3120	sc->rnr = 0;
3121
3122	hsp = &sc->fxp_hwstats;
3123	tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
3124	NULL, "FXP statistics");
3125	parent = SYSCTL_CHILDREN(tree);
3126
3127	/* Rx MAC statistics. */
3128	tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
3129	NULL, "Rx MAC statistics");
3130	child = SYSCTL_CHILDREN(tree);
3131	FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames",
3132	&hsp->rx_good, "Good frames");
3133	FXP_SYSCTL_STAT_ADD(ctx, child, "crc_errors",
3134	&hsp->rx_crc_errors, "CRC errors");
3135	FXP_SYSCTL_STAT_ADD(ctx, child, "alignment_errors",
3136	&hsp->rx_alignment_errors, "Alignment errors");
3137	FXP_SYSCTL_STAT_ADD(ctx, child, "rnr_errors",
3138	&hsp->rx_rnr_errors, "RNR errors");
3139	FXP_SYSCTL_STAT_ADD(ctx, child, "overrun_errors",
3140	&hsp->rx_overrun_errors, "Overrun errors");
3141	FXP_SYSCTL_STAT_ADD(ctx, child, "cdt_errors",
3142	&hsp->rx_cdt_errors, "Collision detect errors");
3143	FXP_SYSCTL_STAT_ADD(ctx, child, "shortframes",
3144	&hsp->rx_shortframes, "Short frame errors");
3145	if (sc->revision >= FXP_REV_82558_A4) {
3146	FXP_SYSCTL_STAT_ADD(ctx, child, "pause",
3147	&hsp->rx_pause, "Pause frames");
3148	FXP_SYSCTL_STAT_ADD(ctx, child, "controls",
3149	&hsp->rx_controls, "Unsupported control frames");
3150	}
3151	if (sc->revision >= FXP_REV_82559_A0)
3152	FXP_SYSCTL_STAT_ADD(ctx, child, "tco",
3153	&hsp->rx_tco, "TCO frames");
3154
3155	/* Tx MAC statistics. */
3156	tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
3157	NULL, "Tx MAC statistics");
3158	child = SYSCTL_CHILDREN(tree);
3159	FXP_SYSCTL_STAT_ADD(ctx, child, "good_frames",
3160	&hsp->tx_good, "Good frames");
3161	FXP_SYSCTL_STAT_ADD(ctx, child, "maxcols",
3162	&hsp->tx_maxcols, "Maximum collisions errors");
3163	FXP_SYSCTL_STAT_ADD(ctx, child, "latecols",
3164	&hsp->tx_latecols, "Late collisions errors");
3165	FXP_SYSCTL_STAT_ADD(ctx, child, "underruns",
3166	&hsp->tx_underruns, "Underrun errors");
3167	FXP_SYSCTL_STAT_ADD(ctx, child, "lostcrs",
3168	&hsp->tx_lostcrs, "Lost carrier sense");
3169	FXP_SYSCTL_STAT_ADD(ctx, child, "deffered",
3170	&hsp->tx_deffered, "Deferred");
3171	FXP_SYSCTL_STAT_ADD(ctx, child, "single_collisions",
3172	&hsp->tx_single_collisions, "Single collisions");
3173	FXP_SYSCTL_STAT_ADD(ctx, child, "multiple_collisions",
3174	&hsp->tx_multiple_collisions, "Multiple collisions");
3175	FXP_SYSCTL_STAT_ADD(ctx, child, "total_collisions",
3176	&hsp->tx_total_collisions, "Total collisions");
3177	if (sc->revision >= FXP_REV_82558_A4)
3178	FXP_SYSCTL_STAT_ADD(ctx, child, "pause",
3179	&hsp->tx_pause, "Pause frames");
3180	if (sc->revision >= FXP_REV_82559_A0)
3181	FXP_SYSCTL_STAT_ADD(ctx, child, "tco",
3182	&hsp->tx_tco, "TCO frames");
3183	}
3184
3185	#undef FXP_SYSCTL_STAT_ADD
3186
3187	static int
3188	sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3189	{
3190	int error, value;
3191
3192	value = (int )arg1;
3193	error = sysctl_handle_int(oidp, &value, 0, req);
3194	if (error \|\| !req->newptr)
3195	return (error);
3196	if (value < low \|\| value > high)
3197	return (EINVAL);
3198	(int )arg1 = value;
3199	return (0);
3200	}
3201
3202	/*
3203	* Interrupt delay is expressed in microseconds, a multiplier is used
3204	* to convert this to the appropriate clock ticks before using.
3205	*/
3206	static int
3207	sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)
3208	{
3209
3210	return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000));
3211	}
3212
3213	static int
3214	sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)
3215	{
3216
3217	return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff));
3218	}

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