1 | .. SPDX-License-Identifier: CC-BY-SA-4.0 |
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2 | |
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3 | .. Copyright (C) 2018 embedded brains GmbH |
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4 | |
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5 | riscv (RISC-V) |
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6 | ************** |
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7 | |
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8 | riscv |
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9 | ===== |
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10 | |
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11 | This BSP offers 15 variants: |
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12 | |
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13 | * rv32i |
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14 | |
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15 | * rv32iac |
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16 | |
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17 | * rv32im |
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18 | |
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19 | * rv32imac |
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20 | |
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21 | * rv32imafc |
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22 | |
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23 | * rv32imafd |
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24 | |
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25 | * rv32imafdc |
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26 | |
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27 | * rv64imac |
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28 | |
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29 | * rv64imac_medany |
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30 | |
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31 | * rv64imafd |
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32 | |
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33 | * rv64imafd_medany |
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34 | |
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35 | * rv64imafdc |
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36 | |
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37 | * rv64imafdc_medany |
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38 | |
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39 | * frdme310arty |
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40 | |
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41 | * mpfs64imafdc |
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42 | |
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43 | Each variant corresponds to a GCC multilib. A particular variant reflects an |
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44 | ISA with ABI and code model choice. |
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45 | |
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46 | The BSP must be started im machine mode. |
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47 | |
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48 | The reference platform for this BSP is the QEMU `virt` machine. |
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49 | |
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50 | The reference platform for the mpfs64imafdc BSP variant is the Microchip |
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51 | PolarFire SoC Icicle Kit. |
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52 | |
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53 | Build Configuration Options |
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54 | --------------------------- |
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55 | |
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56 | The following options can be used in the BSP section of the ``waf`` |
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57 | configuration INI file. The ``waf`` defaults can be used to inspect the values. |
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58 | |
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59 | ``BSP_PRESS_KEY_FOR_RESET`` |
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60 | If defined to a non-zero value, then print a message and wait until pressed |
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61 | before resetting board when application terminates. |
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62 | |
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63 | ``BSP_RESET_BOARD_AT_EXIT`` |
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64 | If defined to a non-zero value, then reset the board when the application |
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65 | terminates. |
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66 | |
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67 | ``BSP_PRINT_EXCEPTION_CONTEXT`` |
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68 | If defined to a non-zero value, then print the exception context when an |
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69 | unexpected exception occurs. |
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70 | |
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71 | ``BSP_FDT_BLOB_SIZE_MAX`` |
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72 | The maximum size of the device tree blob in bytes (default is 65536). |
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73 | |
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74 | ``BSP_DTB_IS_SUPPORTED`` |
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75 | If defined to a non-zero value, then the device tree blob is embedded in |
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76 | the BSP. |
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77 | |
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78 | ``BSP_DTB_HEADER_PATH`` |
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79 | The path to the header file containing the device tree blob. |
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80 | |
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81 | ``BSP_CONSOLE_BAUD`` |
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82 | The default baud for console driver devices (default 115200). |
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83 | |
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84 | ``RISCV_MAXIMUM_EXTERNAL_INTERRUPTS`` |
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85 | The maximum number of external interrupts supported by the BSP (default |
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86 | 64). |
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87 | |
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88 | ``RISCV_ENABLE_HTIF_SUPPORT`` |
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89 | Enables the HTIF support if defined to a non-zero value, otherwise it is |
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90 | disabled (disabled by default). |
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91 | |
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92 | ``RISCV_CONSOLE_MAX_NS16550_DEVICES`` |
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93 | The maximum number of NS16550 devices supported by the console driver (2 |
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94 | by default). |
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95 | |
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96 | ``RISCV_RAM_REGION_BEGIN`` |
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97 | The begin of the RAM region for linker command file (default is 0x70000000 |
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98 | for 64-bit with -mcmodel=medlow and 0x80000000 for all other). |
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99 | |
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100 | ``RISCV_RAM_REGION_SIZE`` |
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101 | The size of the RAM region for linker command file (default 64MiB). |
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102 | |
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103 | ``RISCV_ENABLE_FRDME310ARTY_SUPPORT`` |
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104 | Enables support sifive Freedom E310 Arty board if defined to a non-zero |
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105 | value,otherwise it is disabled (disabled by default) |
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106 | |
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107 | ``RISCV_ENABLE_MPFS_SUPPORT`` |
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108 | Enables support Microchip PolarFire SoC if defined to a non-zero |
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109 | value, otherwise it is disabled (disabled by default). |
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110 | |
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111 | ``RISCV_BOOT_HARTID`` |
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112 | The boot hartid (processor number) of risc-v cpu by default 0. |
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113 | |
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114 | Interrupt Controller |
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115 | -------------------- |
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116 | |
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117 | Exactly one Core Local Interruptor (CLINT) and exactly one Platform-Level |
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118 | Interrupt Controller (PLIC) are supported. The maximum number of external |
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119 | interrupts supported by the BSP is defined by the |
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120 | ``RISCV_MAXIMUM_EXTERNAL_INTERRUPTS`` BSP option. |
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121 | |
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122 | Clock Driver |
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123 | ------------ |
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124 | |
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125 | The clock driver uses the CLINT timer. |
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126 | |
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127 | Console Driver |
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128 | -------------- |
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129 | |
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130 | The console driver supports devices compatible to |
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131 | |
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132 | * "ucb,htif0" (depending on the ``RISCV_ENABLE_HTIF_SUPPORT`` BSP option), |
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133 | |
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134 | * "ns16550a" (see ``RISCV_CONSOLE_MAX_NS16550_DEVICES`` BSP option), and |
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135 | |
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136 | * "ns16750" (see ``RISCV_CONSOLE_MAX_NS16550_DEVICES`` BSP option). |
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137 | |
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138 | * "sifive,uart0" (see ``RISCV_ENABLE_FRDME310ARTY_SUPPORT`` BSP option). |
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139 | |
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140 | They are initialized according to the device tree. The console driver does not |
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141 | configure the pins or peripheral clocks. The console device is selected |
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142 | according to the device tree "/chosen/stdout-path" property value. |
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143 | |
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144 | QEMU |
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145 | ---- |
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146 | |
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147 | All of the BSP variants that start with rv can be run on QEMU's virt machine. |
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148 | For instance, to run the ``rv64imafdc_medany`` BSP with the following |
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149 | "config.ini" file: |
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150 | |
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151 | .. code-block:: none |
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152 | [riscv/rv64imafdc_medany] |
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153 | |
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154 | Run the following QEMU command: |
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155 | |
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156 | .. code-block:: shell |
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157 | $ qemu-system-riscv64 -M virt -nographic -bios $RTEMS_EXE |
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158 | |
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159 | Microchip PolarFire SoC |
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160 | ----------------------- |
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161 | |
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162 | The PolarFire SoC is the 4x 64-bit RISC-V U54 cores and a 64-bit RISC-V |
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163 | E51 monitor core SoC from the Microchip. |
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164 | |
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165 | The ``mpfs64imafdc`` BSP variant supports the U54 cores but not the E51 because |
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166 | the E51 monitor core is reserved for the first stage bootloader |
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167 | (Hart Software Services). In order to boot from the first U54 core, |
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168 | ``RISCV_BOOT_HARTID`` is set to 1 by default. |
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169 | |
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170 | The device tree blob is embedded in the ``mpfs64imafdc`` BSP variant by default |
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171 | with the ``BSP_DTB_IS_SUPPORTED`` enabled and the DTB header path |
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172 | ``BSP_DTB_HEADER_PATH`` is set to bsp/mpfs-dtb.h. |
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173 | |
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174 | **SMP test procedure for the Microchip PolarFire Icicle Kit:** |
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175 | |
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176 | The "config.ini" file. |
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177 | |
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178 | .. code-block:: none |
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179 | |
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180 | [riscv/mpfs64imafdc] |
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181 | BUILD_TESTS = True |
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182 | RTEMS_POSIX_API=True |
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183 | RTEMS_SMP = True |
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184 | BSP_START_COPY_FDT_FROM_U_BOOT=False |
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185 | BSP_VERBOSE_FATAL_EXTENSION = False |
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186 | |
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187 | Build RTEMS. |
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188 | |
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189 | .. code-block:: shell |
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190 | |
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191 | $ ./waf configure --prefix=$HOME/rtems-start/rtems/6 |
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192 | $ ./waf |
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193 | |
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194 | Convert .exe to .elf file. |
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195 | |
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196 | .. code-block:: shell |
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197 | |
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198 | $ riscv-rtems6-objcopy build/riscv/mpfs64imafdc/testsuites/smptests/smp01.exe build/riscv/mpfs64imafdc/testsuites/smptests/smp01.elf |
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199 | |
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200 | Generate a payload for the `smp01.elf` using the `hss-payload-generator <https://github.com/polarfire-soc/hart-software-services/blob/master/tools/hss-payload-generator>`_. |
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201 | |
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202 | * Copy `smp01.elf` file to the HSS/tools/hss-payload-generator/test directory. |
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203 | |
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204 | * Go to hss-payload-generator source directory. |
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205 | |
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206 | .. code-block:: shell |
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207 | |
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208 | $ cd hart-software-services/tools/hss-payload-generator |
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209 | |
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210 | * Edit test/uboot.yaml file for the hart entry points and correct name of the |
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211 | binary file. |
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212 | |
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213 | .. code-block:: none |
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214 | |
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215 | set-name: 'PolarFire-SoC-HSS::RTEMS' |
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216 | hart-entry-points: {u54_1: '0x1000000000', u54_2: '0x1000000000', u54_3: '0x1000000000', u54_4: '0x1000000000'} |
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217 | payloads: |
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218 | test/smp01.elf: {exec-addr: '0x1000000000', owner-hart: u54_1, secondary-hart: u54_2, secondary-hart: u54_3, secondary-hart: u54_4, priv-mode: prv_m, skip-opensbi: true} |
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219 | |
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220 | * Generate payload |
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221 | |
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222 | .. code-block:: shell |
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223 | |
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224 | $ ./hss-payload-generator -c test/uboot.yaml payload.bin |
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225 | |
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226 | Once the payload binary is generated, it should be copied to the eMMC/SD. |
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227 | |
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228 | `FPGA design with HSS programming file <https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md>`_. |
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229 | |
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230 | Program the eMMC/SD with the payload binary. |
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231 | |
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232 | * Power Cycle the Microchip PolarFire Icicle Kit and stop at the HSS. |
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233 | |
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234 | * type "mmc" and then "usbdmsc" on the HSS terminal(UART0). |
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235 | |
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236 | * Load the payload.bin from the Host PC. |
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237 | |
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238 | .. code-block:: shell |
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239 | |
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240 | $ sudo dd if=payload.bin of=/dev/sdb bs=512 |
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241 | |
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242 | Reset the Microchip PolarFire SoC Icicle Kit. |
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243 | |
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244 | Serial terminal UART1 displays the SMP example messages |
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245 | |
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246 | .. code-block:: none |
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247 | |
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248 | *** BEGIN OF TEST SMP 1 *** |
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249 | *** TEST VERSION: 6.0.0.ef33f861e16de9bf4190a36e4d18062c7300986c |
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250 | *** TEST STATE: EXPECTED_PASS |
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251 | *** TEST BUILD: RTEMS_POSIX_API RTEMS_SMP |
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252 | *** TEST TOOLS: 12.1.1 20220622 (RTEMS 6, RSB 3cb78b0b815ba05d17f5c6 |
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253 | 5865d246a8333aa087, Newlib ea99f21) |
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254 | |
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255 | CPU 3 start task TA0 |
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256 | CPU 2 running Task TA0 |
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257 | CPU 3 start task TA1 |
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258 | CPU 1 running Task TA1 |
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259 | CPU 3 start task TA2 |
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260 | CPU 0 running Task TA2 |
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261 | |
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262 | *** END OF TEST SMP 1 *** |
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263 | |
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264 | griscv |
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265 | ====== |
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266 | |
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267 | This RISC-V BSP supports chips using the |
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268 | `GRLIB <https://www.gaisler.com/products/grlib/grlib.pdf>`_. |
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