1 | .. comment SPDX-License-Identifier: CC-BY-SA-4.0 |
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2 | |
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3 | SuperH Specific Information |
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4 | ########################### |
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5 | |
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6 | This chapter discusses the SuperH architecture dependencies |
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7 | in this port of RTEMS. The SuperH family has a wide variety |
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8 | of implementations by a wide range of vendors. Consequently, |
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9 | there are many, many CPU models within it. |
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10 | |
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11 | **Architecture Documents** |
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12 | |
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13 | For information on the SuperH architecture, |
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14 | refer to the following documents available from VENDOR |
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15 | (:file:`http//www.XXX.com/`): |
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16 | |
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17 | - *SuperH Family Reference, VENDOR, PART NUMBER*. |
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18 | |
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19 | CPU Model Dependent Features |
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20 | ============================ |
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21 | |
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22 | This chapter presents the set of features which vary |
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23 | across SuperH implementations and are of importance to RTEMS. |
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24 | The set of CPU model feature macros are defined in the file``cpukit/score/cpu/sh/sh.h`` based upon the particular CPU |
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25 | model specified on the compilation command line. |
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26 | |
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27 | Another Optional Feature |
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28 | ------------------------ |
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29 | |
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30 | The macro XXX |
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31 | |
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32 | Calling Conventions |
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33 | =================== |
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34 | |
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35 | Calling Mechanism |
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36 | ----------------- |
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37 | |
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38 | All RTEMS directives are invoked using a ``XXX`` |
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39 | instruction and return to the user application via the``XXX`` instruction. |
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40 | |
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41 | Register Usage |
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42 | -------------- |
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43 | |
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44 | The SH1 has 16 general registers (r0..r15). |
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45 | |
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46 | - r0..r3 used as general volatile registers |
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47 | |
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48 | - r4..r7 used to pass up to 4 arguments to functions, arguments |
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49 | above 4 are |
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50 | passed via the stack) |
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51 | |
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52 | - r8..13 caller saved registers (i.e. push them to the stack if you |
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53 | need them inside of a function) |
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54 | |
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55 | - r14 frame pointer |
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56 | |
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57 | - r15 stack pointer |
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58 | |
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59 | Parameter Passing |
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60 | ----------------- |
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61 | |
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62 | XXX |
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63 | |
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64 | Memory Model |
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65 | ============ |
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66 | |
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67 | Flat Memory Model |
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68 | ----------------- |
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69 | |
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70 | The SuperH family supports a flat 32-bit address |
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71 | space with addresses ranging from 0x00000000 to 0xFFFFFFFF (4 |
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72 | gigabytes). Each address is represented by a 32-bit value and |
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73 | is byte addressable. The address may be used to reference a |
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74 | single byte, word (2-bytes), or long word (4 bytes). Memory |
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75 | accesses within this address space are performed in big endian |
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76 | fashion by the processors in this family. |
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77 | |
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78 | Some of the SuperH family members support virtual memory and |
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79 | segmentation. RTEMS does not support virtual memory or |
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80 | segmentation on any of the SuperH family members. It is the |
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81 | responsibility of the BSP to initialize the mapping for |
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82 | a flat memory model. |
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83 | |
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84 | Interrupt Processing |
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85 | ==================== |
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86 | |
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87 | Although RTEMS hides many of the processor dependent |
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88 | details of interrupt processing, it is important to understand |
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89 | how the RTEMS interrupt manager is mapped onto the processor's |
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90 | unique architecture. Discussed in this chapter are the MIPS's |
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91 | interrupt response and control mechanisms as they pertain to |
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92 | RTEMS. |
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93 | |
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94 | Vectoring of an Interrupt Handler |
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95 | --------------------------------- |
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96 | |
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97 | Upon receipt of an interrupt the XXX family |
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98 | members with separate interrupt stacks automatically perform the |
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99 | following actions: |
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100 | |
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101 | - TBD |
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102 | |
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103 | A nested interrupt is processed similarly by these |
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104 | CPU models with the exception that only a single ISF is placed |
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105 | on the interrupt stack and the current stack need not be |
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106 | switched. |
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107 | |
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108 | Interrupt Levels |
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109 | ---------------- |
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110 | |
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111 | TBD |
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112 | |
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113 | Default Fatal Error Processing |
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114 | ============================== |
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115 | |
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116 | The default fatal error handler for this architecture disables processor |
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117 | interrupts, places the error code in *XXX*, and executes a ``XXX`` |
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118 | instruction to simulate a halt processor instruction. |
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119 | |
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120 | Symmetric Multiprocessing |
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121 | ========================= |
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122 | |
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123 | SMP is not supported. |
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124 | |
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125 | Thread-Local Storage |
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126 | ==================== |
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127 | |
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128 | Thread-local storage is not implemented. |
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129 | |
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130 | Board Support Packages |
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131 | ====================== |
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132 | |
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133 | System Reset |
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134 | ------------ |
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135 | |
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136 | An RTEMS based application is initiated or |
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137 | re-initiated when the processor is reset. When the |
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138 | processor is reset, it performs the following actions: |
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139 | |
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140 | - TBD |
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141 | |
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142 | Processor Initialization |
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143 | ------------------------ |
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144 | |
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145 | TBD |
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146 | |
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147 | .. COMMENT: COPYRIGHT (c) 1988-2002. |
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148 | |
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149 | .. COMMENT: On-Line Applications Research Corporation (OAR). |
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150 | |
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151 | .. COMMENT: All rights reserved. |
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152 | |
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