1 | SPARC-64 Specific Information |
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2 | ############################# |
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3 | |
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4 | This document discusses the SPARC Version 9 (aka SPARC-64, SPARC64 or SPARC V9) |
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5 | architecture dependencies in this port of RTEMS. |
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6 | |
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7 | The SPARC V9 architecture leaves a lot of undefined implemenation dependencies |
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8 | which are defined by the processor models. Consult the specific CPU model |
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9 | section in this document for additional documents covering the implementation |
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10 | dependent architectural features. |
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11 | |
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12 | **sun4u Specific Information** |
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13 | |
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14 | sun4u is the subset of the SPARC V9 implementations comprising the UltraSPARC I |
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15 | through UltraSPARC IV processors. |
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16 | |
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17 | The following documents were used in developing the SPARC-64 sun4u port: |
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18 | |
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19 | - UltraSPARC UserâÂÂs Manual |
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20 | (http://www.sun.com/microelectronics/manuals/ultrasparc/802-7220-02.pdf) |
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21 | |
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22 | - UltraSPARC IIIi Processor (datasheets.chipdb.org/Sun/UltraSparc-IIIi.pdf) |
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23 | |
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24 | **sun4v Specific Information** |
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25 | |
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26 | sun4v is the subset of the SPARC V9 implementations comprising the |
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27 | UltraSPARC T1 or T2 processors. |
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28 | |
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29 | The following documents were used in developing the SPARC-64 sun4v port: |
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30 | |
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31 | - UltraSPARC Architecture 2005 Specification |
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32 | (http://opensparc-t1.sunsource.net/specs/UA2005-current-draft-P-EXT.pdf) |
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33 | |
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34 | - UltraSPARC T1 supplement to UltraSPARC Architecture 2005 Specification |
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35 | (http://opensparc-t1.sunsource.net/specs/UST1-UASuppl-current-draft-P-EXT.pdf) |
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36 | |
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37 | The defining feature that separates the sun4v architecture from its |
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38 | predecessor is the existence of a super-privileged hypervisor that |
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39 | is responsible for providing virtualized execution environments. The impact |
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40 | of the hypervisor on the real-time guarantees available with sun4v has not |
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41 | yet been determined. |
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42 | |
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43 | CPU Model Dependent Features |
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44 | ============================ |
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45 | |
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46 | CPU Model Feature Flags |
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47 | ----------------------- |
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48 | |
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49 | This section presents the set of features which vary across |
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50 | SPARC-64 implementations and |
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51 | are of importance to RTEMS. The set of CPU model feature macros |
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52 | are defined in the file |
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53 | cpukit/score/cpu/sparc64/sparc64.h based upon the particular |
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54 | CPU model defined on the compilation command line. |
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55 | |
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56 | CPU Model Name |
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57 | ~~~~~~~~~~~~~~ |
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58 | |
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59 | The macro CPU MODEL NAME is a string which designates |
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60 | the name of this CPU model. |
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61 | For example, for the UltraSPARC T1 SPARC V9 model, |
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62 | this macro is set to the string "sun4v". |
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63 | |
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64 | Floating Point Unit |
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65 | ~~~~~~~~~~~~~~~~~~~ |
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66 | |
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67 | The macro SPARC_HAS_FPU is set to 1 to indicate that |
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68 | this CPU model has a hardware floating point unit and 0 |
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69 | otherwise. |
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70 | |
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71 | Number of Register Windows |
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72 | ~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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73 | |
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74 | The macro SPARC_NUMBER_OF_REGISTER_WINDOWS is set to |
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75 | indicate the number of register window sets implemented by this |
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76 | CPU model. The SPARC architecture allows for a maximum of |
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77 | thirty-two register window sets although most implementations |
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78 | only include eight. |
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79 | |
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80 | CPU Model Implementation Notes |
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81 | ------------------------------ |
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82 | |
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83 | This section describes the implemenation dependencies of the |
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84 | CPU Models sun4u and sun4v of the SPARC V9 architecture. |
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85 | |
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86 | sun4u Notes |
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87 | ~~~~~~~~~~~ |
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88 | |
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89 | XXX |
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90 | |
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91 | sun4v Notes |
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92 | ----------- |
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93 | |
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94 | XXX |
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95 | |
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96 | .. COMMENT: COPYRIGHT (c) 1988-2002. |
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97 | |
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98 | .. COMMENT: On-Line Applications Research Corporation (OAR). |
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99 | |
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100 | .. COMMENT: All rights reserved. |
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101 | |
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102 | Calling Conventions |
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103 | =================== |
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104 | |
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105 | Each high-level language compiler generates |
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106 | subroutine entry and exit code based upon a set of rules known |
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107 | as the compilerâs calling convention. These rules address the |
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108 | following issues: |
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109 | |
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110 | - register preservation and usage |
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111 | |
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112 | - parameter passing |
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113 | |
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114 | - call and return mechanism |
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115 | |
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116 | A compilerâs calling convention is of importance when |
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117 | interfacing to subroutines written in another language either |
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118 | assembly or high-level. Even when the high-level language and |
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119 | target processor are the same, different compilers may use |
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120 | different calling conventions. As a result, calling conventions |
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121 | are both processor and compiler dependent. |
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122 | |
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123 | The following document also provides some conventions on the |
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124 | global register usage in SPARC V9: |
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125 | http://developers.sun.com/solaris/articles/sparcv9abi.html |
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126 | |
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127 | Programming Model |
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128 | ----------------- |
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129 | |
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130 | This section discusses the programming model for the |
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131 | SPARC architecture. |
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132 | |
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133 | Non-Floating Point Registers |
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134 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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135 | |
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136 | The SPARC architecture defines thirty-two |
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137 | non-floating point registers directly visible to the programmer. |
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138 | These are divided into four sets: |
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139 | |
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140 | - input registers |
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141 | |
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142 | - local registers |
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143 | |
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144 | - output registers |
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145 | |
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146 | - global registers |
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147 | |
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148 | Each register is referred to by either two or three |
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149 | names in the SPARC reference manuals. First, the registers are |
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150 | referred to as r0 through r31 or with the alternate notation |
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151 | r[0] through r[31]. Second, each register is a member of one of |
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152 | the four sets listed above. Finally, some registers have an |
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153 | architecturally defined role in the programming model which |
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154 | provides an alternate name. The following table describes the |
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155 | mapping between the 32 registers and the register sets: |
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156 | |
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157 | .. code:: c |
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158 | |
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159 | +-----------------+----------------+------------------+ |
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160 | | Register Number | Register Names | Description | |
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161 | +-----------------+----------------+------------------+ |
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162 | | 0 - 7 | g0 - g7 | Global Registers | |
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163 | +-----------------+----------------+------------------+ |
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164 | | 8 - 15 | o0 - o7 | Output Registers | |
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165 | +-----------------+----------------+------------------+ |
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166 | | 16 - 23 | l0 - l7 | Local Registers | |
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167 | +-----------------+----------------+------------------+ |
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168 | | 24 - 31 | i0 - i7 | Input Registers | |
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169 | +-----------------+----------------+------------------+ |
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170 | |
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171 | As mentioned above, some of the registers serve |
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172 | defined roles in the programming model. The following table |
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173 | describes the role of each of these registers: |
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174 | |
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175 | .. code:: c |
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176 | |
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177 | +---------------+----------------+----------------------+ |
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178 | | Register Name | Alternate Name | Description | |
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179 | +---------------+----------------+----------------------+ |
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180 | | g0 | na | reads return 0 | |
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181 | | | | writes are ignored | |
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182 | +---------------+----------------+----------------------+ |
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183 | | o6 | sp | stack pointer | |
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184 | +---------------+----------------+----------------------+ |
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185 | | i6 | fp | frame pointer | |
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186 | +---------------+----------------+----------------------+ |
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187 | | i7 | na | return address | |
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188 | +---------------+----------------+----------------------+ |
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189 | |
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190 | Floating Point Registers |
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191 | ~~~~~~~~~~~~~~~~~~~~~~~~ |
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192 | |
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193 | The SPARC V9 architecture includes sixty-four, |
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194 | thirty-two bit registers. These registers may be viewed as |
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195 | follows: |
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196 | |
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197 | - 32 32-bit single precision floating point or integer registers |
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198 | (f0, f1, ... f31) |
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199 | |
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200 | - 32 64-bit double precision floating point registers (f0, f2, |
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201 | f4, ... f62) |
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202 | |
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203 | - 16 128-bit extended precision floating point registers (f0, f4, |
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204 | f8, ... f60) |
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205 | |
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206 | The floating point state register (fsr) specifies |
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207 | the behavior of the floating point unit for rounding, contains |
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208 | its condition codes, version specification, and trap information. |
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209 | |
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210 | Special Registers |
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211 | ~~~~~~~~~~~~~~~~~ |
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212 | |
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213 | The SPARC architecture includes a number of special registers: |
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214 | |
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215 | *``Ancillary State Registers (ASRs)``* |
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216 | The ancillary state registers (ASRs) are optional state registers that |
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217 | may be privileged or nonprivileged. ASRs 16-31 are implementation- |
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218 | dependent. The SPARC V9 ASRs include: y, ccr, asi, tick, pc, fprs. |
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219 | The sun4u ASRs include: pcr, pic, dcr, gsr, softint set, softint clr, |
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220 | softint, and tick cmpr. The sun4v ASRs include: pcr, pic, gsr, soft- |
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221 | int set, softint clr, softint, tick cmpr, stick, and stick cmpr. |
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222 | |
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223 | *``Processor State Register (pstate)``* |
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224 | The privileged pstate register contains control fields for the proces- |
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225 | sorâÂÂs current state. Its flag fields include the interrupt enable, privi- |
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226 | leged mode, and enable FPU. |
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227 | |
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228 | *``Processor Interrupt Level (pil)``* |
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229 | The PIL specifies the interrupt level above which interrupts will be |
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230 | accepted. |
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231 | |
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232 | *``Trap Registers``* |
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233 | The trap handling mechanism of the SPARC V9 includes a number of |
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234 | registers, including: trap program counter (tpc), trap next pc (tnpc), |
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235 | trap state (tstate), trap type (tt), trap base address (tba), and trap |
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236 | level (tl). |
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237 | |
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238 | *``Alternate Globals``* |
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239 | The AG bit of the pstate register provides access to an alternate set |
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240 | of global registers. On sun4v, the AG bit is replaced by the global |
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241 | level (gl) register, providing access to at least two and at most eight |
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242 | alternate sets of globals. |
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243 | |
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244 | *``Register Window registers``* |
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245 | A number of registers assist in register window management. |
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246 | These include the current window pointer (cwp), savable windows |
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247 | (cansave), restorable windows (canrestore), clean windows (clean- |
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248 | win), other windows (otherwin), and window state (wstate). |
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249 | |
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250 | Register Windows |
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251 | ---------------- |
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252 | |
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253 | The SPARC architecture includes the concept of |
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254 | register windows. An overly simplistic way to think of these |
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255 | windows is to imagine them as being an infinite supply of |
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256 | "fresh" register sets available for each subroutine to use. In |
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257 | reality, they are much more complicated. |
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258 | |
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259 | The save instruction is used to obtain a new register window. |
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260 | This instruction increments the current window pointer, thus |
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261 | providing a new set of registers for use. This register set |
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262 | includes eight fresh local registers for use exclusively by |
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263 | this subroutine. When done with a register set, the restore |
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264 | instruction decrements the current window pointer and the |
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265 | previous register set is once again available. |
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266 | |
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267 | The two primary issues complicating the use of register windows |
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268 | are that (1) the set of register windows is finite, and (2) some |
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269 | registers are shared between adjacent registers windows. |
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270 | |
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271 | Because the set of register windows is finite, it is |
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272 | possible to execute enough save instructions without |
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273 | corresponding restoreâs to consume all of the register windows. |
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274 | This is easily accomplished in a high level language because |
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275 | each subroutine typically performs a save instruction upon |
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276 | entry. Thus having a subroutine call depth greater than the |
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277 | number of register windows will result in a window overflow |
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278 | condition. The window overflow condition generates a trap which |
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279 | must be handled in software. The window overflow trap handler |
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280 | is responsible for saving the contents of the oldest register |
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281 | window on the program stack. |
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282 | |
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283 | Similarly, the subroutines will eventually complete |
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284 | and begin to perform restoreâs. If the restore results in the |
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285 | need for a register window which has previously been written to |
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286 | memory as part of an overflow, then a window underflow condition |
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287 | results. Just like the window overflow, the window underflow |
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288 | condition must be handled in software by a trap handler. The |
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289 | window underflow trap handler is responsible for reloading the |
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290 | contents of the register window requested by the restore |
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291 | instruction from the program stack. |
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292 | |
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293 | The cansave, canrestore, otherwin, and cwp are used in conjunction |
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294 | to manage the finite set of register windows and detect the window |
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295 | overflow and underflow conditions. The first three of these |
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296 | registers must satisfy the invariant cansave + canrestore + otherwin = |
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297 | nwindow - 2, where nwindow is the number of register windows. |
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298 | The cwp contains the index of the register window currently in use. |
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299 | RTEMS does not use the cleanwin and otherwin registers. |
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300 | |
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301 | The save instruction increments the cwp modulo the number of |
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302 | register windows, and if cansave is 0 then it also generates a |
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303 | window overflow. Similarly, the restore instruction decrements the |
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304 | cwp modulo the number of register windows, and if canrestore is 0 then it |
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305 | also generates a window underflow. |
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306 | |
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307 | Unlike with the SPARC model, the SPARC-64 port does not assume that |
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308 | a register window is available for a trap. The window overflow |
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309 | and underflow conditions are not detected without hardware generating |
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310 | the trap. (These conditions can be detected by reading the register window |
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311 | registers and doing some simple arithmetic.) |
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312 | |
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313 | The window overflow and window underflow trap |
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314 | handlers are a critical part of the run-time environment for a |
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315 | SPARC application. The SPARC architectural specification allows |
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316 | for the number of register windows to be any power of two less |
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317 | than or equal to 32. The most common choice for SPARC |
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318 | implementations appears to be 8 register windows. This results |
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319 | in the cwp ranging in value from 0 to 7 on most implementations. |
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320 | |
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321 | The second complicating factor is the sharing of |
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322 | registers between adjacent register windows. While each |
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323 | register window has its own set of local registers, the input |
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324 | and output registers are shared between adjacent windows. The |
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325 | output registers for register window N are the same as the input |
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326 | registers for register window ((N + 1) modulo RW) where RW is |
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327 | the number of register windows. An alternative way to think of |
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328 | this is to remember how parameters are passed to a subroutine on |
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329 | the SPARC. The caller loads values into what are its output |
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330 | registers. Then after the callee executes a save instruction, |
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331 | those parameters are available in its input registers. This is |
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332 | a very efficient way to pass parameters as no data is actually |
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333 | moved by the save or restore instructions. |
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334 | |
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335 | Call and Return Mechanism |
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336 | ------------------------- |
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337 | |
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338 | The SPARC architecture supports a simple yet |
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339 | effective call and return mechanism. A subroutine is invoked |
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340 | via the call (call) instruction. This instruction places the |
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341 | return address in the callerâs output register 7 (o7). After |
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342 | the callee executes a save instruction, this value is available |
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343 | in input register 7 (i7) until the corresponding restore |
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344 | instruction is executed. |
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345 | |
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346 | The callee returns to the caller via a jmp to the |
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347 | return address. There is a delay slot following this |
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348 | instruction which is commonly used to execute a restore |
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349 | instruction â if a register window was allocated by this |
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350 | subroutine. |
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351 | |
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352 | It is important to note that the SPARC subroutine |
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353 | call and return mechanism does not automatically save and |
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354 | restore any registers. This is accomplished via the save and |
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355 | restore instructions which manage the set of registers windows. |
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356 | This allows for the compiler to generate leaf-optimized functions |
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357 | that utilize the callerâÂÂs output registers without using save and restore. |
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358 | |
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359 | Calling Mechanism |
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360 | ----------------- |
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361 | |
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362 | All RTEMS directives are invoked using the regular |
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363 | SPARC calling convention via the call instruction. |
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364 | |
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365 | Register Usage |
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366 | -------------- |
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367 | |
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368 | As discussed above, the call instruction does not |
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369 | automatically save any registers. The save and restore |
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370 | instructions are used to allocate and deallocate register |
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371 | windows. When a register window is allocated, the new set of |
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372 | local registers are available for the exclusive use of the |
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373 | subroutine which allocated this register set. |
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374 | |
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375 | Parameter Passing |
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376 | ----------------- |
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377 | |
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378 | RTEMS assumes that arguments are placed in the |
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379 | callerâs output registers with the first argument in output |
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380 | register 0 (o0), the second argument in output register 1 (o1), |
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381 | and so forth. Until the callee executes a save instruction, the |
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382 | parameters are still visible in the output registers. After the |
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383 | callee executes a save instruction, the parameters are visible |
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384 | in the corresponding input registers. The following pseudo-code |
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385 | illustrates the typical sequence used to call a RTEMS directive |
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386 | with three (3) arguments: |
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387 | .. code:: c |
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388 | |
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389 | load third argument into o2 |
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390 | load second argument into o1 |
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391 | load first argument into o0 |
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392 | invoke directive |
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393 | |
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394 | User-Provided Routines |
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395 | ---------------------- |
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396 | |
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397 | All user-provided routines invoked by RTEMS, such as |
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398 | user extensions, device drivers, and MPCI routines, must also |
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399 | adhere to these calling conventions. |
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400 | |
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401 | .. COMMENT: COPYRIGHT (c) 1988-2002. |
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402 | |
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403 | .. COMMENT: On-Line Applications Research Corporation (OAR). |
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404 | |
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405 | .. COMMENT: All rights reserved. |
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406 | |
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407 | Memory Model |
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408 | ============ |
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409 | |
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410 | A processor may support any combination of memory |
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411 | models ranging from pure physical addressing to complex demand |
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412 | paged virtual memory systems. RTEMS supports a flat memory |
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413 | model which ranges contiguously over the processorâs allowable |
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414 | address space. RTEMS does not support segmentation or virtual |
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415 | memory of any kind. The appropriate memory model for RTEMS |
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416 | provided by the targeted processor and related characteristics |
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417 | of that model are described in this chapter. |
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418 | |
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419 | Flat Memory Model |
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420 | ----------------- |
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421 | |
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422 | The SPARC-64 architecture supports a flat 64-bit address space with |
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423 | addresses ranging from 0x0000000000000000 to 0xFFFFFFFFFFFFFFFF. |
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424 | Each address is represented by a 64-bit value (and an 8-bit address |
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425 | space identifider or ASI) and is byte addressable. The address |
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426 | may be used to reference a single byte, half-word (2-bytes), |
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427 | word (4 bytes), doubleword (8 bytes), or quad-word (16 bytes). |
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428 | Memory accesses within this address space are performed |
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429 | in big endian fashion by the SPARC. Memory accesses which are not |
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430 | properly aligned generate a "memory address not aligned" trap |
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431 | (type number 0x34). The following table lists the alignment |
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432 | requirements for a variety of data accesses: |
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433 | |
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434 | .. code:: c |
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435 | |
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436 | +--------------+-----------------------+ |
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437 | | Data Type | Alignment Requirement | |
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438 | +--------------+-----------------------+ |
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439 | | byte | 1 | |
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440 | | half-word | 2 | |
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441 | | word | 4 | |
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442 | | doubleword | 8 | |
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443 | | quadword | 16 | |
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444 | +--------------+-----------------------+ |
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445 | |
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446 | RTEMS currently does not support any SPARC Memory Management |
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447 | Units, therefore, virtual memory or segmentation systems |
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448 | involving the SPARC are not supported. |
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449 | |
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450 | .. COMMENT: COPYRIGHT (c) 1988-2002. |
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451 | |
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452 | .. COMMENT: On-Line Applications Research Corporation (OAR). |
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453 | |
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454 | .. COMMENT: All rights reserved. |
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455 | |
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456 | Interrupt Processing |
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457 | ==================== |
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458 | |
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459 | RTEMS and associated documentation uses the terms |
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460 | interrupt and vector. In the SPARC architecture, these terms |
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461 | correspond to traps and trap type, respectively. The terms will |
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462 | be used interchangeably in this manual. Note that in the SPARC manuals, |
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463 | interrupts are a subset of the traps that are delivered to software |
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464 | interrupt handlers. |
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465 | |
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466 | Synchronous Versus Asynchronous Traps |
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467 | ------------------------------------- |
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468 | |
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469 | The SPARC architecture includes two classes of traps: |
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470 | synchronous (precise) and asynchronous (deferred). |
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471 | Asynchronous traps occur when an |
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472 | external event interrupts the processor. These traps are not |
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473 | associated with any instruction executed by the processor and |
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474 | logically occur between instructions. The instruction currently |
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475 | in the execute stage of the processor is allowed to complete |
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476 | although subsequent instructions are annulled. The return |
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477 | address reported by the processor for asynchronous traps is the |
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478 | pair of instructions following the current instruction. |
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479 | |
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480 | Synchronous traps are caused by the actions of an |
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481 | instruction. The trap stimulus in this case either occurs |
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482 | internally to the processor or is from an external signal that |
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483 | was provoked by the instruction. These traps are taken |
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484 | immediately and the instruction that caused the trap is aborted |
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485 | before any state changes occur in the processor itself. The |
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486 | return address reported by the processor for synchronous traps |
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487 | is the instruction which caused the trap and the following |
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488 | instruction. |
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489 | |
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490 | Vectoring of Interrupt Handler |
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491 | ------------------------------ |
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492 | |
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493 | Upon receipt of an interrupt the SPARC automatically |
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494 | performs the following actions: |
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495 | |
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496 | - The trap level is set. This provides access to a fresh set of |
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497 | privileged trap-state registers used to save the current state, |
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498 | in effect, pushing a frame on the trap stack. |
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499 | TL <- TL + 1 |
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500 | |
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501 | - Existing state is preserved |
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502 | - TSTATE[TL].CCR <- CCR |
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503 | - TSTATE[TL].ASI <- ASI |
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504 | - TSTATE[TL].PSTATE <- PSTATE |
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505 | - TSTATE[TL].CWP <- CWP |
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506 | - TPC[TL] <- PC |
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507 | - TNPC[TL] <- nPC |
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508 | |
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509 | - The trap type is preserved. TT[TL] <- the trap type |
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510 | |
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511 | - The PSTATE register is updated to a predefined state |
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512 | - PSTATE.MM is unchanged |
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513 | - PSTATE.RED <- 0 |
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514 | - PSTATE.PEF <- 1 if FPU is present, 0 otherwise |
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515 | - PSTATE.AM <- 0 (address masking is turned off) |
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516 | - PSTATE.PRIV <- 1 (the processor enters privileged mode) |
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517 | - PSTATE.IE <- 0 (interrupts are disabled) |
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518 | - PSTATE.AG <- 1 (global regs are replaced with alternate globals) |
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519 | - PSTATE.CLE <- PSTATE.TLE (set endian mode for traps) |
---|
520 | |
---|
521 | - For a register-window trap only, CWP is set to point to the register |
---|
522 | window that must be accessed by the trap-handler software, that is: |
---|
523 | |
---|
524 | - If TT[TL] = 0x24 (a clean window trap), then CWP <- CWP + 1. |
---|
525 | - If (0x80 <= TT[TL] <= 0xBF) (window spill trap), then CWP <- CWP + |
---|
526 | CANSAVE + 2. |
---|
527 | - If (0xC0 <= TT[TL] <= 0xFF) (window fill trap), then CWP <- CWP1. |
---|
528 | - For non-register-window traps, CWP is not changed. |
---|
529 | |
---|
530 | - Control is transferred into the trap table: |
---|
531 | |
---|
532 | - PC <- TBA<63:15> (TL>0) TT[TL] 0 0000 |
---|
533 | - nPC <- TBA<63:15> (TL>0) TT[TL] 0 0100 |
---|
534 | - where (TL>0) is 0 if TL = 0, and 1 if TL > 0. |
---|
535 | |
---|
536 | In order to safely invoke a subroutine during trap handling, traps must be |
---|
537 | enabled to allow for the possibility of register window overflow and |
---|
538 | underflow traps. |
---|
539 | |
---|
540 | If the interrupt handler was installed as an RTEMS |
---|
541 | interrupt handler, then upon receipt of the interrupt, the |
---|
542 | processor passes control to the RTEMS interrupt handler which |
---|
543 | performs the following actions: |
---|
544 | |
---|
545 | - saves the state of the interrupted task on itâs stack, |
---|
546 | |
---|
547 | - switches the processor to trap level 0, |
---|
548 | |
---|
549 | - if this is the outermost (i.e. non-nested) interrupt, |
---|
550 | then the RTEMS interrupt handler switches from the current stack |
---|
551 | to the interrupt stack, |
---|
552 | |
---|
553 | - enables traps, |
---|
554 | |
---|
555 | - invokes the vectors to a user interrupt service routine (ISR). |
---|
556 | |
---|
557 | Asynchronous interrupts are ignored while traps are |
---|
558 | disabled. Synchronous traps which occur while traps are |
---|
559 | disabled may result in the CPU being forced into an error mode. |
---|
560 | |
---|
561 | A nested interrupt is processed similarly with the |
---|
562 | exception that the current stack need not be switched to the |
---|
563 | interrupt stack. |
---|
564 | |
---|
565 | Traps and Register Windows |
---|
566 | -------------------------- |
---|
567 | |
---|
568 | XXX |
---|
569 | |
---|
570 | Interrupt Levels |
---|
571 | ---------------- |
---|
572 | |
---|
573 | Sixteen levels (0-15) of interrupt priorities are |
---|
574 | supported by the SPARC architecture with level fifteen (15) |
---|
575 | being the highest priority. Level zero (0) indicates that |
---|
576 | interrupts are fully enabled. Interrupt requests for interrupts |
---|
577 | with priorities less than or equal to the current interrupt mask |
---|
578 | level are ignored. |
---|
579 | |
---|
580 | Although RTEMS supports 256 interrupt levels, the |
---|
581 | SPARC only supports sixteen. RTEMS interrupt levels 0 through |
---|
582 | 15 directly correspond to SPARC processor interrupt levels. All |
---|
583 | other RTEMS interrupt levels are undefined and their behavior is |
---|
584 | unpredictable. |
---|
585 | |
---|
586 | Disabling of Interrupts by RTEMS |
---|
587 | -------------------------------- |
---|
588 | |
---|
589 | XXX |
---|
590 | |
---|
591 | Interrupt Stack |
---|
592 | --------------- |
---|
593 | |
---|
594 | The SPARC architecture does not provide for a |
---|
595 | dedicated interrupt stack. Thus by default, trap handlers would |
---|
596 | execute on the stack of the RTEMS task which they interrupted. |
---|
597 | This artificially inflates the stack requirements for each task |
---|
598 | since EVERY task stack would have to include enough space to |
---|
599 | account for the worst case interrupt stack requirements in |
---|
600 | addition to itâs own worst case usage. RTEMS addresses this |
---|
601 | problem on the SPARC by providing a dedicated interrupt stack |
---|
602 | managed by software. |
---|
603 | |
---|
604 | During system initialization, RTEMS allocates the |
---|
605 | interrupt stack from the Workspace Area. The amount of memory |
---|
606 | allocated for the interrupt stack is determined by the |
---|
607 | interrupt_stack_size field in the CPU Configuration Table. As |
---|
608 | part of processing a non-nested interrupt, RTEMS will switch to |
---|
609 | the interrupt stack before invoking the installed handler. |
---|
610 | |
---|
611 | .. COMMENT: COPYRIGHT (c) 1988-2002. |
---|
612 | |
---|
613 | .. COMMENT: On-Line Applications Research Corporation (OAR). |
---|
614 | |
---|
615 | .. COMMENT: All rights reserved. |
---|
616 | |
---|
617 | Default Fatal Error Processing |
---|
618 | ============================== |
---|
619 | |
---|
620 | Upon detection of a fatal error by either the |
---|
621 | application or RTEMS the fatal error manager is invoked. The |
---|
622 | fatal error manager will invoke the user-supplied fatal error |
---|
623 | handlers. If no user-supplied handlers are configured, the |
---|
624 | RTEMS provided default fatal error handler is invoked. If the |
---|
625 | user-supplied fatal error handlers return to the executive the |
---|
626 | default fatal error handler is then invoked. This chapter |
---|
627 | describes the precise operations of the default fatal error |
---|
628 | handler. |
---|
629 | |
---|
630 | Default Fatal Error Handler Operations |
---|
631 | -------------------------------------- |
---|
632 | |
---|
633 | The default fatal error handler which is invoked by |
---|
634 | the fatal_error_occurred directive when there is no user handler |
---|
635 | configured or the user handler returns control to RTEMS. The |
---|
636 | default fatal error handler disables processor interrupts to |
---|
637 | level 15, places the error code in g1, and goes into an infinite |
---|
638 | loop to simulate a halt processor instruction. |
---|
639 | |
---|
640 | Symmetric Multiprocessing |
---|
641 | ========================= |
---|
642 | |
---|
643 | SMP is not supported. |
---|
644 | |
---|
645 | Thread-Local Storage |
---|
646 | ==================== |
---|
647 | |
---|
648 | Thread-local storage is supported. |
---|
649 | |
---|
650 | .. COMMENT: COPYRIGHT (c) 1988-2002. |
---|
651 | |
---|
652 | .. COMMENT: On-Line Applications Research Corporation (OAR). |
---|
653 | |
---|
654 | .. COMMENT: All rights reserved. |
---|
655 | |
---|
656 | Board Support Packages |
---|
657 | ====================== |
---|
658 | |
---|
659 | An RTEMS Board Support Package (BSP) must be designed |
---|
660 | to support a particular processor and target board combination. |
---|
661 | This chapter presents a discussion of SPARC specific BSP issues. |
---|
662 | For more information on developing a BSP, refer to the chapter |
---|
663 | titled Board Support Packages in the RTEMS |
---|
664 | Applications Userâs Guide. |
---|
665 | |
---|
666 | HelenOS and Open Firmware |
---|
667 | ------------------------- |
---|
668 | |
---|
669 | The provided BSPs make use of some bootstrap and low-level hardware code |
---|
670 | of the HelenOS operating system. These files can be found in the shared/helenos |
---|
671 | directory of the sparc64 bsp directory. Consult the sources for more |
---|
672 | detailed information. |
---|
673 | |
---|
674 | The shared BSP code also uses the Open Firmware interface to re-use firmware |
---|
675 | code, primarily for console support and default trap handlers. |
---|
676 | |
---|