1 | .. comment SPDX-License-Identifier: CC-BY-SA-4.0 |
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2 | |
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3 | SPARC Specific Information |
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4 | ########################## |
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5 | |
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6 | The Real Time Executive for Multiprocessor Systems |
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7 | (RTEMS) is designed to be portable across multiple processor |
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8 | architectures. However, the nature of real-time systems makes |
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9 | it essential that the application designer understand certain |
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10 | processor dependent implementation details. These processor |
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11 | dependencies include calling convention, board support package |
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12 | issues, interrupt processing, exact RTEMS memory requirements, |
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13 | performance data, header files, and the assembly language |
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14 | interface to the executive. |
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15 | |
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16 | This document discusses the SPARC architecture dependencies in this |
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17 | port of RTEMS. This architectural port is for SPARC Version 7 and |
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18 | 8. Implementations for SPARC V9 are in the sparc64 target. |
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19 | |
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20 | It is highly recommended that the SPARC RTEMS |
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21 | application developer obtain and become familiar with the |
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22 | documentation for the processor being used as well as the |
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23 | specification for the revision of the SPARC architecture which |
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24 | corresponds to that processor. |
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25 | |
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26 | **SPARC Architecture Documents** |
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27 | |
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28 | For information on the SPARC architecture, refer to |
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29 | the following documents available from SPARC International, Inc. |
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30 | (http://www.sparc.com): |
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31 | |
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32 | - SPARC Standard Version 7. |
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33 | |
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34 | - SPARC Standard Version 8. |
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35 | |
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36 | **ERC32 Specific Information** |
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37 | |
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38 | The European Space Agency's ERC32 is a three chip |
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39 | computing core implementing a SPARC V7 processor and associated |
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40 | support circuitry for embedded space applications. The integer |
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41 | and floating-point units (90C601E & 90C602E) are based on the |
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42 | Cypress 7C601 and 7C602, with additional error-detection and |
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43 | recovery functions. The memory controller (MEC) implements |
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44 | system support functions such as address decoding, memory |
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45 | interface, DMA interface, UARTs, timers, interrupt control, |
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46 | write-protection, memory reconfiguration and error-detection. |
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47 | The core is designed to work at 25MHz, but using space qualified |
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48 | memories limits the system frequency to around 15 MHz, resulting |
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49 | in a performance of 10 MIPS and 2 MFLOPS. |
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50 | |
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51 | Information on the ERC32 and a number of development |
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52 | support tools, such as the SPARC Instruction Simulator (SIS), |
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53 | are freely available on the Internet. The following documents |
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54 | and SIS are available via anonymous ftp or pointing your web |
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55 | browser at ftp://ftp.estec.esa.nl/pub/ws/wsd/erc32. |
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56 | |
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57 | - ERC32 System Design Document |
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58 | |
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59 | - MEC Device Specification |
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60 | |
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61 | Additionally, the SPARC RISC User's Guide from Matra |
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62 | MHS documents the functionality of the integer and floating |
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63 | point units including the instruction set information. To |
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64 | obtain this document as well as ERC32 components and VHDL models |
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65 | contact: |
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66 | .. code:: c |
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67 | |
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68 | Matra MHS SA |
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69 | 3 Avenue du Centre, BP 309, |
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70 | 78054 St-Quentin-en-Yvelines, |
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71 | Cedex, France |
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72 | VOICE: +31-1-30607087 |
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73 | FAX: +31-1-30640693 |
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74 | |
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75 | Amar Guennon (amar.guennon@matramhs.fr) is familiar with the ERC32. |
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76 | |
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77 | .. COMMENT: COPYRIGHT (c) 1988-2002. |
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78 | |
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79 | .. COMMENT: On-Line Applications Research Corporation (OAR). |
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80 | |
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81 | .. COMMENT: All rights reserved. |
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82 | |
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83 | CPU Model Dependent Features |
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84 | ============================ |
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85 | |
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86 | Microprocessors are generally classified into |
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87 | families with a variety of CPU models or implementations within |
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88 | that family. Within a processor family, there is a high level |
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89 | of binary compatibility. This family may be based on either an |
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90 | architectural specification or on maintaining compatibility with |
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91 | a popular processor. Recent microprocessor families such as the |
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92 | SPARC or PowerPC are based on an architectural specification |
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93 | which is independent or any particular CPU model or |
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94 | implementation. Older families such as the M68xxx and the iX86 |
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95 | evolved as the manufacturer strived to produce higher |
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96 | performance processor models which maintained binary |
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97 | compatibility with older models. |
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98 | |
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99 | RTEMS takes advantage of the similarity of the |
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100 | various models within a CPU family. Although the models do vary |
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101 | in significant ways, the high level of compatibility makes it |
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102 | possible to share the bulk of the CPU dependent executive code |
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103 | across the entire family. |
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104 | |
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105 | CPU Model Feature Flags |
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106 | ----------------------- |
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107 | |
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108 | Each processor family supported by RTEMS has a |
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109 | list of features which vary between CPU models |
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110 | within a family. For example, the most common model dependent |
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111 | feature regardless of CPU family is the presence or absence of a |
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112 | floating point unit or coprocessor. When defining the list of |
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113 | features present on a particular CPU model, one simply notes |
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114 | that floating point hardware is or is not present and defines a |
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115 | single constant appropriately. Conditional compilation is |
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116 | utilized to include the appropriate source code for this CPU |
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117 | model's feature set. It is important to note that this means |
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118 | that RTEMS is thus compiled using the appropriate feature set |
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119 | and compilation flags optimal for this CPU model used. The |
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120 | alternative would be to generate a binary which would execute on |
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121 | all family members using only the features which were always |
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122 | present. |
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123 | |
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124 | This section presents the set of features which vary |
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125 | across SPARC implementations and are of importance to RTEMS. |
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126 | The set of CPU model feature macros are defined in the file |
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127 | cpukit/score/cpu/sparc/sparc.h based upon the particular CPU |
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128 | model defined on the compilation command line. |
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129 | |
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130 | CPU Model Name |
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131 | ~~~~~~~~~~~~~~ |
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132 | |
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133 | The macro CPU_MODEL_NAME is a string which designates |
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134 | the name of this CPU model. For example, for the European Space |
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135 | Agency's ERC32 SPARC model, this macro is set to the string |
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136 | "erc32". |
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137 | |
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138 | Floating Point Unit |
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139 | ~~~~~~~~~~~~~~~~~~~ |
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140 | |
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141 | The macro SPARC_HAS_FPU is set to 1 to indicate that |
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142 | this CPU model has a hardware floating point unit and 0 |
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143 | otherwise. |
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144 | |
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145 | Bitscan Instruction |
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146 | ~~~~~~~~~~~~~~~~~~~ |
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147 | |
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148 | The macro SPARC_HAS_BITSCAN is set to 1 to indicate |
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149 | that this CPU model has the bitscan instruction. For example, |
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150 | this instruction is supported by the Fujitsu SPARClite family. |
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151 | |
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152 | Number of Register Windows |
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153 | ~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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154 | |
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155 | The macro SPARC_NUMBER_OF_REGISTER_WINDOWS is set to |
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156 | indicate the number of register window sets implemented by this |
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157 | CPU model. The SPARC architecture allows a for a maximum of |
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158 | thirty-two register window sets although most implementations |
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159 | only include eight. |
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160 | |
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161 | Low Power Mode |
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162 | ~~~~~~~~~~~~~~ |
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163 | |
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164 | The macro SPARC_HAS_LOW_POWER_MODE is set to one to |
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165 | indicate that this CPU model has a low power mode. If low power |
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166 | is enabled, then there must be CPU model specific implementation |
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167 | of the IDLE task in cpukit/score/cpu/sparc/cpu.c. The low |
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168 | power mode IDLE task should be of the form: |
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169 | .. code:: c |
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170 | |
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171 | while ( TRUE ) { |
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172 | enter low power mode |
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173 | } |
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174 | |
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175 | The code required to enter low power mode is CPU model specific. |
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176 | |
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177 | CPU Model Implementation Notes |
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178 | ------------------------------ |
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179 | |
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180 | The ERC32 is a custom SPARC V7 implementation based on the Cypress 601/602 |
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181 | chipset. This CPU has a number of on-board peripherals and was developed by |
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182 | the European Space Agency to target space applications. RTEMS currently |
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183 | provides support for the following peripherals: |
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184 | |
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185 | - UART Channels A and B |
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186 | |
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187 | - General Purpose Timer |
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188 | |
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189 | - Real Time Clock |
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190 | |
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191 | - Watchdog Timer (so it can be disabled) |
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192 | |
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193 | - Control Register (so powerdown mode can be enabled) |
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194 | |
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195 | - Memory Control Register |
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196 | |
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197 | - Interrupt Control |
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198 | |
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199 | The General Purpose Timer and Real Time Clock Timer provided with the ERC32 |
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200 | share the Timer Control Register. Because the Timer Control Register is write |
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201 | only, we must mirror it in software and insure that writes to one timer do not |
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202 | alter the current settings and status of the other timer. Routines are |
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203 | provided in erc32.h which promote the view that the two timers are completely |
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204 | independent. By exclusively using these routines to access the Timer Control |
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205 | Register, the application can view the system as having a General Purpose |
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206 | Timer Control Register and a Real Time Clock Timer Control Register |
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207 | rather than the single shared value. |
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208 | |
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209 | The RTEMS Idle thread take advantage of the low power mode provided by the |
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210 | ERC32. Low power mode is entered during idle loops and is enabled at |
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211 | initialization time. |
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212 | |
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213 | .. COMMENT: COPYRIGHT (c) 1988-2002. |
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214 | |
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215 | .. COMMENT: On-Line Applications Research Corporation (OAR). |
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216 | |
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217 | .. COMMENT: All rights reserved. |
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218 | |
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219 | Calling Conventions |
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220 | =================== |
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221 | |
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222 | Each high-level language compiler generates subroutine entry and exit code |
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223 | based upon a set of rules known as the application binary interface (ABI) |
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224 | calling convention. These rules address the following issues: |
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225 | |
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226 | - register preservation and usage |
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227 | |
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228 | - parameter passing |
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229 | |
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230 | - call and return mechanism |
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231 | |
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232 | An ABI calling convention is of importance when interfacing to subroutines |
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233 | written in another language either assembly or high-level. It determines also |
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234 | the set of registers to be saved or restored during a context switch and |
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235 | interrupt processing. |
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236 | |
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237 | The ABI relevant for RTEMS on SPARC is defined by SYSTEM V APPLICATION BINARY |
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238 | INTERFACE, SPARC Processor Supplement, Third Edition. |
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239 | |
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240 | Programming Model |
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241 | ----------------- |
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242 | |
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243 | This section discusses the programming model for the |
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244 | SPARC architecture. |
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245 | |
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246 | Non-Floating Point Registers |
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247 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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248 | |
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249 | The SPARC architecture defines thirty-two |
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250 | non-floating point registers directly visible to the programmer. |
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251 | These are divided into four sets: |
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252 | |
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253 | - input registers |
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254 | |
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255 | - local registers |
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256 | |
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257 | - output registers |
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258 | |
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259 | - global registers |
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260 | |
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261 | Each register is referred to by either two or three |
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262 | names in the SPARC reference manuals. First, the registers are |
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263 | referred to as r0 through r31 or with the alternate notation |
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264 | r[0] through r[31]. Second, each register is a member of one of |
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265 | the four sets listed above. Finally, some registers have an |
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266 | architecturally defined role in the programming model which |
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267 | provides an alternate name. The following table describes the |
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268 | mapping between the 32 registers and the register sets: |
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269 | |
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270 | .. code:: c |
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271 | |
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272 | +-----------------+----------------+------------------+ |
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273 | | Register Number | Register Names | Description | |
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274 | +-----------------+----------------+------------------+ |
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275 | | 0 - 7 | g0 - g7 | Global Registers | |
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276 | +-----------------+----------------+------------------+ |
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277 | | 8 - 15 | o0 - o7 | Output Registers | |
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278 | +-----------------+----------------+------------------+ |
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279 | | 16 - 23 | l0 - l7 | Local Registers | |
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280 | +-----------------+----------------+------------------+ |
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281 | | 24 - 31 | i0 - i7 | Input Registers | |
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282 | +-----------------+----------------+------------------+ |
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283 | |
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284 | As mentioned above, some of the registers serve |
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285 | defined roles in the programming model. The following table |
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286 | describes the role of each of these registers: |
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287 | |
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288 | .. code:: c |
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289 | |
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290 | +---------------+----------------+----------------------+ |
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291 | | Register Name | Alternate Name | Description | |
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292 | +---------------+----------------+----------------------+ |
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293 | | g0 | na | reads return 0 | |
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294 | | | | writes are ignored | |
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295 | +---------------+----------------+----------------------+ |
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296 | | o6 | sp | stack pointer | |
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297 | +---------------+----------------+----------------------+ |
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298 | | i6 | fp | frame pointer | |
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299 | +---------------+----------------+----------------------+ |
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300 | | i7 | na | return address | |
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301 | +---------------+----------------+----------------------+ |
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302 | |
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303 | The registers g2 through g4 are reserved for applications. GCC uses them as |
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304 | volatile registers by default. So they are treated like volatile registers in |
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305 | RTEMS as well. |
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306 | |
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307 | The register g6 is reserved for the operating system and contains the address |
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308 | of the per-CPU control block of the current processor. This register is |
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309 | initialized during system start and then remains unchanged. It is not |
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310 | saved/restored by the context switch or interrupt processing code. |
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311 | |
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312 | The register g7 is reserved for the operating system and contains the thread |
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313 | pointer used for thread-local storage (TLS) as mandated by the SPARC ABI. |
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314 | |
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315 | Floating Point Registers |
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316 | ~~~~~~~~~~~~~~~~~~~~~~~~ |
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317 | |
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318 | The SPARC V7 architecture includes thirty-two, |
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319 | thirty-two bit registers. These registers may be viewed as |
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320 | follows: |
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321 | |
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322 | - 32 single precision floating point or integer registers |
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323 | (f0, f1, ... f31) |
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324 | |
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325 | - 16 double precision floating point registers (f0, f2, |
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326 | f4, ... f30) |
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327 | |
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328 | - 8 extended precision floating point registers (f0, f4, |
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329 | f8, ... f28) |
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330 | |
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331 | The floating point status register (FSR) specifies |
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332 | the behavior of the floating point unit for rounding, contains |
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333 | its condition codes, version specification, and trap information. |
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334 | |
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335 | According to the ABI all floating point registers and the floating point status |
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336 | register (FSR) are volatile. Thus the floating point context of a thread is the |
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337 | empty set. The rounding direction is a system global state and must not be |
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338 | modified by threads. |
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339 | |
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340 | A queue of the floating point instructions which have |
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341 | started execution but not yet completed is maintained. This |
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342 | queue is needed to support the multiple cycle nature of floating |
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343 | point operations and to aid floating point exception trap |
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344 | handlers. Once a floating point exception has been encountered, |
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345 | the queue is frozen until it is emptied by the trap handler. |
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346 | The floating point queue is loaded by launching instructions. |
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347 | It is emptied normally when the floating point completes all |
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348 | outstanding instructions and by floating point exception |
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349 | handlers with the store double floating point queue (stdfq) |
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350 | instruction. |
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351 | |
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352 | Special Registers |
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353 | ~~~~~~~~~~~~~~~~~ |
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354 | |
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355 | The SPARC architecture includes two special registers |
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356 | which are critical to the programming model: the Processor State |
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357 | Register (psr) and the Window Invalid Mask (wim). The psr |
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358 | contains the condition codes, processor interrupt level, trap |
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359 | enable bit, supervisor mode and previous supervisor mode bits, |
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360 | version information, floating point unit and coprocessor enable |
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361 | bits, and the current window pointer (cwp). The cwp field of |
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362 | the psr and wim register are used to manage the register windows |
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363 | in the SPARC architecture. The register windows are discussed |
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364 | in more detail below. |
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365 | |
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366 | Register Windows |
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367 | ---------------- |
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368 | |
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369 | The SPARC architecture includes the concept of |
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370 | register windows. An overly simplistic way to think of these |
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371 | windows is to imagine them as being an infinite supply of |
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372 | "fresh" register sets available for each subroutine to use. In |
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373 | reality, they are much more complicated. |
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374 | |
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375 | The save instruction is used to obtain a new register |
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376 | window. This instruction decrements the current window pointer, |
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377 | thus providing a new set of registers for use. This register |
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378 | set includes eight fresh local registers for use exclusively by |
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379 | this subroutine. When done with a register set, the restore |
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380 | instruction increments the current window pointer and the |
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381 | previous register set is once again available. |
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382 | |
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383 | The two primary issues complicating the use of |
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384 | register windows are that (1) the set of register windows is |
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385 | finite, and (2) some registers are shared between adjacent |
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386 | registers windows. |
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387 | |
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388 | Because the set of register windows is finite, it is |
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389 | possible to execute enough save instructions without |
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390 | corresponding restore's to consume all of the register windows. |
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391 | This is easily accomplished in a high level language because |
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392 | each subroutine typically performs a save instruction upon |
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393 | entry. Thus having a subroutine call depth greater than the |
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394 | number of register windows will result in a window overflow |
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395 | condition. The window overflow condition generates a trap which |
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396 | must be handled in software. The window overflow trap handler |
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397 | is responsible for saving the contents of the oldest register |
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398 | window on the program stack. |
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399 | |
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400 | Similarly, the subroutines will eventually complete |
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401 | and begin to perform restore's. If the restore results in the |
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402 | need for a register window which has previously been written to |
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403 | memory as part of an overflow, then a window underflow condition |
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404 | results. Just like the window overflow, the window underflow |
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405 | condition must be handled in software by a trap handler. The |
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406 | window underflow trap handler is responsible for reloading the |
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407 | contents of the register window requested by the restore |
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408 | instruction from the program stack. |
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409 | |
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410 | The Window Invalid Mask (wim) and the Current Window |
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411 | Pointer (cwp) field in the psr are used in conjunction to manage |
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412 | the finite set of register windows and detect the window |
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413 | overflow and underflow conditions. The cwp contains the index |
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414 | of the register window currently in use. The save instruction |
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415 | decrements the cwp modulo the number of register windows. |
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416 | Similarly, the restore instruction increments the cwp modulo the |
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417 | number of register windows. Each bit in the wim represents |
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418 | represents whether a register window contains valid information. |
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419 | The value of 0 indicates the register window is valid and 1 |
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420 | indicates it is invalid. When a save instruction causes the cwp |
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421 | to point to a register window which is marked as invalid, a |
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422 | window overflow condition results. Conversely, the restore |
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423 | instruction may result in a window underflow condition. |
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424 | |
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425 | Other than the assumption that a register window is |
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426 | always available for trap (i.e. interrupt) handlers, the SPARC |
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427 | architecture places no limits on the number of register windows |
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428 | simultaneously marked as invalid (i.e. number of bits set in the |
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429 | wim). However, RTEMS assumes that only one register window is |
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430 | marked invalid at a time (i.e. only one bit set in the wim). |
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431 | This makes the maximum possible number of register windows |
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432 | available to the user while still meeting the requirement that |
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433 | window overflow and underflow conditions can be detected. |
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434 | |
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435 | The window overflow and window underflow trap |
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436 | handlers are a critical part of the run-time environment for a |
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437 | SPARC application. The SPARC architectural specification allows |
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438 | for the number of register windows to be any power of two less |
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439 | than or equal to 32. The most common choice for SPARC |
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440 | implementations appears to be 8 register windows. This results |
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441 | in the cwp ranging in value from 0 to 7 on most implementations. |
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442 | |
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443 | The second complicating factor is the sharing of |
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444 | registers between adjacent register windows. While each |
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445 | register window has its own set of local registers, the input |
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446 | and output registers are shared between adjacent windows. The |
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447 | output registers for register window N are the same as the input |
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448 | registers for register window ((N - 1) modulo RW) where RW is |
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449 | the number of register windows. An alternative way to think of |
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450 | this is to remember how parameters are passed to a subroutine on |
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451 | the SPARC. The caller loads values into what are its output |
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452 | registers. Then after the callee executes a save instruction, |
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453 | those parameters are available in its input registers. This is |
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454 | a very efficient way to pass parameters as no data is actually |
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455 | moved by the save or restore instructions. |
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456 | |
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457 | Call and Return Mechanism |
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458 | ------------------------- |
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459 | |
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460 | The SPARC architecture supports a simple yet |
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461 | effective call and return mechanism. A subroutine is invoked |
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462 | via the call (call) instruction. This instruction places the |
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463 | return address in the caller's output register 7 (o7). After |
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464 | the callee executes a save instruction, this value is available |
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465 | in input register 7 (i7) until the corresponding restore |
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466 | instruction is executed. |
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467 | |
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468 | The callee returns to the caller via a jmp to the |
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469 | return address. There is a delay slot following this |
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470 | instruction which is commonly used to execute a restore |
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471 | instruction - if a register window was allocated by this |
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472 | subroutine. |
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473 | |
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474 | It is important to note that the SPARC subroutine |
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475 | call and return mechanism does not automatically save and |
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476 | restore any registers. This is accomplished via the save and |
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477 | restore instructions which manage the set of registers windows. |
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478 | |
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479 | In case a floating-point unit is supported, then floating-point return values |
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480 | appear in the floating-point registers. Single-precision values occupy %f0; |
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481 | double-precision values occupy %f0 and %f1. Otherwise, these are scratch |
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482 | registers. Due to this the hardware and software floating-point ABIs are |
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483 | incompatible. |
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484 | |
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485 | Calling Mechanism |
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486 | ----------------- |
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487 | |
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488 | All RTEMS directives are invoked using the regular |
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489 | SPARC calling convention via the call instruction. |
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490 | |
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491 | Register Usage |
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492 | -------------- |
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493 | |
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494 | As discussed above, the call instruction does not |
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495 | automatically save any registers. The save and restore |
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496 | instructions are used to allocate and deallocate register |
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497 | windows. When a register window is allocated, the new set of |
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498 | local registers are available for the exclusive use of the |
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499 | subroutine which allocated this register set. |
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500 | |
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501 | Parameter Passing |
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502 | ----------------- |
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503 | |
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504 | RTEMS assumes that arguments are placed in the |
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505 | caller's output registers with the first argument in output |
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506 | register 0 (o0), the second argument in output register 1 (o1), |
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507 | and so forth. Until the callee executes a save instruction, the |
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508 | parameters are still visible in the output registers. After the |
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509 | callee executes a save instruction, the parameters are visible |
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510 | in the corresponding input registers. The following pseudo-code |
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511 | illustrates the typical sequence used to call a RTEMS directive |
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512 | with three (3) arguments: |
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513 | .. code:: c |
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514 | |
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515 | load third argument into o2 |
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516 | load second argument into o1 |
---|
517 | load first argument into o0 |
---|
518 | invoke directive |
---|
519 | |
---|
520 | User-Provided Routines |
---|
521 | ---------------------- |
---|
522 | |
---|
523 | All user-provided routines invoked by RTEMS, such as |
---|
524 | user extensions, device drivers, and MPCI routines, must also |
---|
525 | adhere to these calling conventions. |
---|
526 | |
---|
527 | .. COMMENT: COPYRIGHT (c) 1988-2002. |
---|
528 | |
---|
529 | .. COMMENT: On-Line Applications Research Corporation (OAR). |
---|
530 | |
---|
531 | .. COMMENT: All rights reserved. |
---|
532 | |
---|
533 | Memory Model |
---|
534 | ============ |
---|
535 | |
---|
536 | A processor may support any combination of memory |
---|
537 | models ranging from pure physical addressing to complex demand |
---|
538 | paged virtual memory systems. RTEMS supports a flat memory |
---|
539 | model which ranges contiguously over the processor's allowable |
---|
540 | address space. RTEMS does not support segmentation or virtual |
---|
541 | memory of any kind. The appropriate memory model for RTEMS |
---|
542 | provided by the targeted processor and related characteristics |
---|
543 | of that model are described in this chapter. |
---|
544 | |
---|
545 | Flat Memory Model |
---|
546 | ----------------- |
---|
547 | |
---|
548 | The SPARC architecture supports a flat 32-bit address |
---|
549 | space with addresses ranging from 0x00000000 to 0xFFFFFFFF (4 |
---|
550 | gigabytes). Each address is represented by a 32-bit value and |
---|
551 | is byte addressable. The address may be used to reference a |
---|
552 | single byte, half-word (2-bytes), word (4 bytes), or doubleword |
---|
553 | (8 bytes). Memory accesses within this address space are |
---|
554 | performed in big endian fashion by the SPARC. Memory accesses |
---|
555 | which are not properly aligned generate a "memory address not |
---|
556 | aligned" trap (type number 7). The following table lists the |
---|
557 | alignment requirements for a variety of data accesses: |
---|
558 | |
---|
559 | .. code:: c |
---|
560 | |
---|
561 | +--------------+-----------------------+ |
---|
562 | | Data Type | Alignment Requirement | |
---|
563 | +--------------+-----------------------+ |
---|
564 | | byte | 1 | |
---|
565 | | half-word | 2 | |
---|
566 | | word | 4 | |
---|
567 | | doubleword | 8 | |
---|
568 | +--------------+-----------------------+ |
---|
569 | |
---|
570 | Doubleword load and store operations must use a pair |
---|
571 | of registers as their source or destination. This pair of |
---|
572 | registers must be an adjacent pair of registers with the first |
---|
573 | of the pair being even numbered. For example, a valid |
---|
574 | destination for a doubleword load might be input registers 0 and |
---|
575 | 1 (i0 and i1). The pair i1 and i2 would be invalid. \[NOTE: |
---|
576 | Some assemblers for the SPARC do not generate an error if an odd |
---|
577 | numbered register is specified as the beginning register of the |
---|
578 | pair. In this case, the assembler assumes that what the |
---|
579 | programmer meant was to use the even-odd pair which ends at the |
---|
580 | specified register. This may or may not have been a correct |
---|
581 | assumption.] |
---|
582 | |
---|
583 | RTEMS does not support any SPARC Memory Management |
---|
584 | Units, therefore, virtual memory or segmentation systems |
---|
585 | involving the SPARC are not supported. |
---|
586 | |
---|
587 | .. COMMENT: COPYRIGHT (c) 1988-2002. |
---|
588 | |
---|
589 | .. COMMENT: On-Line Applications Research Corporation (OAR). |
---|
590 | |
---|
591 | .. COMMENT: All rights reserved. |
---|
592 | |
---|
593 | Interrupt Processing |
---|
594 | ==================== |
---|
595 | |
---|
596 | Different types of processors respond to the |
---|
597 | occurrence of an interrupt in its own unique fashion. In |
---|
598 | addition, each processor type provides a control mechanism to |
---|
599 | allow for the proper handling of an interrupt. The processor |
---|
600 | dependent response to the interrupt modifies the current |
---|
601 | execution state and results in a change in the execution stream. |
---|
602 | Most processors require that an interrupt handler utilize some |
---|
603 | special control mechanisms to return to the normal processing |
---|
604 | stream. Although RTEMS hides many of the processor dependent |
---|
605 | details of interrupt processing, it is important to understand |
---|
606 | how the RTEMS interrupt manager is mapped onto the processor's |
---|
607 | unique architecture. Discussed in this chapter are the SPARC's |
---|
608 | interrupt response and control mechanisms as they pertain to |
---|
609 | RTEMS. |
---|
610 | |
---|
611 | RTEMS and associated documentation uses the terms |
---|
612 | interrupt and vector. In the SPARC architecture, these terms |
---|
613 | correspond to traps and trap type, respectively. The terms will |
---|
614 | be used interchangeably in this manual. |
---|
615 | |
---|
616 | Synchronous Versus Asynchronous Traps |
---|
617 | ------------------------------------- |
---|
618 | |
---|
619 | The SPARC architecture includes two classes of traps: |
---|
620 | synchronous and asynchronous. Asynchronous traps occur when an |
---|
621 | external event interrupts the processor. These traps are not |
---|
622 | associated with any instruction executed by the processor and |
---|
623 | logically occur between instructions. The instruction currently |
---|
624 | in the execute stage of the processor is allowed to complete |
---|
625 | although subsequent instructions are annulled. The return |
---|
626 | address reported by the processor for asynchronous traps is the |
---|
627 | pair of instructions following the current instruction. |
---|
628 | |
---|
629 | Synchronous traps are caused by the actions of an |
---|
630 | instruction. The trap stimulus in this case either occurs |
---|
631 | internally to the processor or is from an external signal that |
---|
632 | was provoked by the instruction. These traps are taken |
---|
633 | immediately and the instruction that caused the trap is aborted |
---|
634 | before any state changes occur in the processor itself. The |
---|
635 | return address reported by the processor for synchronous traps |
---|
636 | is the instruction which caused the trap and the following |
---|
637 | instruction. |
---|
638 | |
---|
639 | Vectoring of Interrupt Handler |
---|
640 | ------------------------------ |
---|
641 | |
---|
642 | Upon receipt of an interrupt the SPARC automatically |
---|
643 | performs the following actions: |
---|
644 | |
---|
645 | - disables traps (sets the ET bit of the psr to 0), |
---|
646 | |
---|
647 | - the S bit of the psr is copied into the Previous |
---|
648 | Supervisor Mode (PS) bit of the psr, |
---|
649 | |
---|
650 | - the cwp is decremented by one (modulo the number of |
---|
651 | register windows) to activate a trap window, |
---|
652 | |
---|
653 | - the PC and nPC are loaded into local register 1 and 2 |
---|
654 | (l0 and l1), |
---|
655 | |
---|
656 | - the trap type (tt) field of the Trap Base Register (TBR) |
---|
657 | is set to the appropriate value, and |
---|
658 | |
---|
659 | - if the trap is not a reset, then the PC is written with |
---|
660 | the contents of the TBR and the nPC is written with TBR + 4. If |
---|
661 | the trap is a reset, then the PC is set to zero and the nPC is |
---|
662 | set to 4. |
---|
663 | |
---|
664 | Trap processing on the SPARC has two features which |
---|
665 | are noticeably different than interrupt processing on other |
---|
666 | architectures. First, the value of psr register in effect |
---|
667 | immediately before the trap occurred is not explicitly saved. |
---|
668 | Instead only reversible alterations are made to it. Second, the |
---|
669 | Processor Interrupt Level (pil) is not set to correspond to that |
---|
670 | of the interrupt being processed. When a trap occurs, ALL |
---|
671 | subsequent traps are disabled. In order to safely invoke a |
---|
672 | subroutine during trap handling, traps must be enabled to allow |
---|
673 | for the possibility of register window overflow and underflow |
---|
674 | traps. |
---|
675 | |
---|
676 | If the interrupt handler was installed as an RTEMS |
---|
677 | interrupt handler, then upon receipt of the interrupt, the |
---|
678 | processor passes control to the RTEMS interrupt handler which |
---|
679 | performs the following actions: |
---|
680 | |
---|
681 | - saves the state of the interrupted task on it's stack, |
---|
682 | |
---|
683 | - insures that a register window is available for |
---|
684 | subsequent traps, |
---|
685 | |
---|
686 | - if this is the outermost (i.e. non-nested) interrupt, |
---|
687 | then the RTEMS interrupt handler switches from the current stack |
---|
688 | to the interrupt stack, |
---|
689 | |
---|
690 | - enables traps, |
---|
691 | |
---|
692 | - invokes the vectors to a user interrupt service routine (ISR). |
---|
693 | |
---|
694 | Asynchronous interrupts are ignored while traps are |
---|
695 | disabled. Synchronous traps which occur while traps are |
---|
696 | disabled result in the CPU being forced into an error mode. |
---|
697 | |
---|
698 | A nested interrupt is processed similarly with the |
---|
699 | exception that the current stack need not be switched to the |
---|
700 | interrupt stack. |
---|
701 | |
---|
702 | Traps and Register Windows |
---|
703 | -------------------------- |
---|
704 | |
---|
705 | One of the register windows must be reserved at all |
---|
706 | times for trap processing. This is critical to the proper |
---|
707 | operation of the trap mechanism in the SPARC architecture. It |
---|
708 | is the responsibility of the trap handler to insure that there |
---|
709 | is a register window available for a subsequent trap before |
---|
710 | re-enabling traps. It is likely that any high level language |
---|
711 | routines invoked by the trap handler (such as a user-provided |
---|
712 | RTEMS interrupt handler) will allocate a new register window. |
---|
713 | The save operation could result in a window overflow trap. This |
---|
714 | trap cannot be correctly processed unless (1) traps are enabled |
---|
715 | and (2) a register window is reserved for traps. Thus, the |
---|
716 | RTEMS interrupt handler insures that a register window is |
---|
717 | available for subsequent traps before enabling traps and |
---|
718 | invoking the user's interrupt handler. |
---|
719 | |
---|
720 | Interrupt Levels |
---|
721 | ---------------- |
---|
722 | |
---|
723 | Sixteen levels (0-15) of interrupt priorities are |
---|
724 | supported by the SPARC architecture with level fifteen (15) |
---|
725 | being the highest priority. Level zero (0) indicates that |
---|
726 | interrupts are fully enabled. Interrupt requests for interrupts |
---|
727 | with priorities less than or equal to the current interrupt mask |
---|
728 | level are ignored. Level fifteen (15) is a non-maskable interrupt |
---|
729 | (NMI), which makes it unsuitable for standard usage since it can |
---|
730 | affect the real-time behaviour by interrupting critical sections |
---|
731 | and spinlocks. Disabling traps stops also the NMI interrupt from |
---|
732 | happening. It can however be used for power-down or other |
---|
733 | critical events. |
---|
734 | |
---|
735 | Although RTEMS supports 256 interrupt levels, the |
---|
736 | SPARC only supports sixteen. RTEMS interrupt levels 0 through |
---|
737 | 15 directly correspond to SPARC processor interrupt levels. All |
---|
738 | other RTEMS interrupt levels are undefined and their behavior is |
---|
739 | unpredictable. |
---|
740 | |
---|
741 | Many LEON SPARC v7/v8 systems features an extended interrupt controller |
---|
742 | which adds an extra step of interrupt decoding to allow handling of |
---|
743 | interrupt 16-31. When such an extended interrupt is generated the CPU |
---|
744 | traps into a specific interrupt trap level 1-14 and software reads out from |
---|
745 | the interrupt controller which extended interrupt source actually caused the |
---|
746 | interrupt. |
---|
747 | |
---|
748 | Disabling of Interrupts by RTEMS |
---|
749 | -------------------------------- |
---|
750 | |
---|
751 | During the execution of directive calls, critical |
---|
752 | sections of code may be executed. When these sections are |
---|
753 | encountered, RTEMS disables interrupts to level fifteen (15) |
---|
754 | before the execution of the section and restores them to the |
---|
755 | previous level upon completion of the section. RTEMS has been |
---|
756 | optimized to ensure that interrupts are disabled for less than |
---|
757 | RTEMS_MAXIMUM_DISABLE_PERIOD microseconds on a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ |
---|
758 | Mhz ERC32 with zero wait states. |
---|
759 | These numbers will vary based the number of wait states and |
---|
760 | processor speed present on the target board. |
---|
761 | \[NOTE: The maximum period with interrupts disabled is hand calculated. This |
---|
762 | calculation was last performed for Release |
---|
763 | RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.] |
---|
764 | |
---|
765 | [NOTE: It is thought that the length of time at which |
---|
766 | the processor interrupt level is elevated to fifteen by RTEMS is |
---|
767 | not anywhere near as long as the length of time ALL traps are |
---|
768 | disabled as part of the "flush all register windows" operation.] |
---|
769 | |
---|
770 | Non-maskable interrupts (NMI) cannot be disabled, and |
---|
771 | ISRs which execute at this level MUST NEVER issue RTEMS system |
---|
772 | calls. If a directive is invoked, unpredictable results may |
---|
773 | occur due to the inability of RTEMS to protect its critical |
---|
774 | sections. However, ISRs that make no system calls may safely |
---|
775 | execute as non-maskable interrupts. |
---|
776 | |
---|
777 | Interrupts are disabled or enabled by performing a system call |
---|
778 | to the Operating System reserved software traps 9 |
---|
779 | (SPARC_SWTRAP_IRQDIS) or 10 (SPARC_SWTRAP_IRQDIS). The trap is |
---|
780 | generated by the software trap (Ticc) instruction or indirectly |
---|
781 | by calling sparc_disable_interrupts() or sparc_enable_interrupts() |
---|
782 | functions. Disabling interrupts return the previous interrupt level |
---|
783 | (on trap entry) in register G1 and sets PSR.PIL to 15 to disable |
---|
784 | all maskable interrupts. The interrupt level can be restored by |
---|
785 | trapping into the enable interrupt handler with G1 containing the |
---|
786 | new interrupt level. |
---|
787 | |
---|
788 | Interrupt Stack |
---|
789 | --------------- |
---|
790 | |
---|
791 | The SPARC architecture does not provide for a |
---|
792 | dedicated interrupt stack. Thus by default, trap handlers would |
---|
793 | execute on the stack of the RTEMS task which they interrupted. |
---|
794 | This artificially inflates the stack requirements for each task |
---|
795 | since EVERY task stack would have to include enough space to |
---|
796 | account for the worst case interrupt stack requirements in |
---|
797 | addition to it's own worst case usage. RTEMS addresses this |
---|
798 | problem on the SPARC by providing a dedicated interrupt stack |
---|
799 | managed by software. |
---|
800 | |
---|
801 | During system initialization, RTEMS allocates the |
---|
802 | interrupt stack from the Workspace Area. The amount of memory |
---|
803 | allocated for the interrupt stack is determined by the |
---|
804 | interrupt_stack_size field in the CPU Configuration Table. As |
---|
805 | part of processing a non-nested interrupt, RTEMS will switch to |
---|
806 | the interrupt stack before invoking the installed handler. |
---|
807 | |
---|
808 | .. COMMENT: COPYRIGHT (c) 1988-2002. |
---|
809 | |
---|
810 | .. COMMENT: On-Line Applications Research Corporation (OAR). |
---|
811 | |
---|
812 | .. COMMENT: All rights reserved. |
---|
813 | |
---|
814 | Default Fatal Error Processing |
---|
815 | ============================== |
---|
816 | |
---|
817 | Upon detection of a fatal error by either the |
---|
818 | application or RTEMS the fatal error manager is invoked. The |
---|
819 | fatal error manager will invoke the user-supplied fatal error |
---|
820 | handlers. If no user-supplied handlers are configured, the |
---|
821 | RTEMS provided default fatal error handler is invoked. If the |
---|
822 | user-supplied fatal error handlers return to the executive the |
---|
823 | default fatal error handler is then invoked. This chapter |
---|
824 | describes the precise operations of the default fatal error |
---|
825 | handler. |
---|
826 | |
---|
827 | Default Fatal Error Handler Operations |
---|
828 | -------------------------------------- |
---|
829 | |
---|
830 | The default fatal error handler which is invoked by |
---|
831 | the fatal_error_occurred directive when there is no user handler |
---|
832 | configured or the user handler returns control to RTEMS. |
---|
833 | |
---|
834 | If the BSP has been configured with ``BSP_POWER_DOWN_AT_FATAL_HALT`` |
---|
835 | set to true, the default handler will disable interrupts |
---|
836 | and enter power down mode. If power down mode is not available, |
---|
837 | it goes into an infinite loop to simulate a halt processor instruction. |
---|
838 | |
---|
839 | If ``BSP_POWER_DOWN_AT_FATAL_HALT`` is set to false, the default |
---|
840 | handler will place the value ``1`` in register ``g1``, the |
---|
841 | error source in register ``g2``, and the error code in register``g3``. It will then generate a system error which will |
---|
842 | hand over control to the debugger, simulator, etc. |
---|
843 | |
---|
844 | Symmetric Multiprocessing |
---|
845 | ========================= |
---|
846 | |
---|
847 | SMP is supported. Available platforms are the Cobham Gaisler GR712RC and |
---|
848 | GR740. |
---|
849 | |
---|
850 | Thread-Local Storage |
---|
851 | ==================== |
---|
852 | |
---|
853 | Thread-local storage is supported. |
---|
854 | |
---|
855 | .. COMMENT: COPYRIGHT (c) 1988-2002. |
---|
856 | |
---|
857 | .. COMMENT: On-Line Applications Research Corporation (OAR). |
---|
858 | |
---|
859 | .. COMMENT: All rights reserved. |
---|
860 | |
---|
861 | Board Support Packages |
---|
862 | ====================== |
---|
863 | |
---|
864 | An RTEMS Board Support Package (BSP) must be designed |
---|
865 | to support a particular processor and target board combination. |
---|
866 | This chapter presents a discussion of SPARC specific BSP issues. |
---|
867 | For more information on developing a BSP, refer to the chapter |
---|
868 | titled Board Support Packages in the RTEMS |
---|
869 | Applications User's Guide. |
---|
870 | |
---|
871 | System Reset |
---|
872 | ------------ |
---|
873 | |
---|
874 | An RTEMS based application is initiated or |
---|
875 | re-initiated when the SPARC processor is reset. When the SPARC |
---|
876 | is reset, the processor performs the following actions: |
---|
877 | |
---|
878 | - the enable trap (ET) of the psr is set to 0 to disable |
---|
879 | traps, |
---|
880 | |
---|
881 | - the supervisor bit (S) of the psr is set to 1 to enter |
---|
882 | supervisor mode, and |
---|
883 | |
---|
884 | - the PC is set 0 and the nPC is set to 4. |
---|
885 | |
---|
886 | The processor then begins to execute the code at |
---|
887 | location 0. It is important to note that all fields in the psr |
---|
888 | are not explicitly set by the above steps and all other |
---|
889 | registers retain their value from the previous execution mode. |
---|
890 | This is true even of the Trap Base Register (TBR) whose contents |
---|
891 | reflect the last trap which occurred before the reset. |
---|
892 | |
---|
893 | Processor Initialization |
---|
894 | ------------------------ |
---|
895 | |
---|
896 | It is the responsibility of the application's |
---|
897 | initialization code to initialize the TBR and install trap |
---|
898 | handlers for at least the register window overflow and register |
---|
899 | window underflow conditions. Traps should be enabled before |
---|
900 | invoking any subroutines to allow for register window |
---|
901 | management. However, interrupts should be disabled by setting |
---|
902 | the Processor Interrupt Level (pil) field of the psr to 15. |
---|
903 | RTEMS installs it's own Trap Table as part of initialization |
---|
904 | which is initialized with the contents of the Trap Table in |
---|
905 | place when the ``rtems_initialize_executive`` directive was invoked. |
---|
906 | Upon completion of executive initialization, interrupts are |
---|
907 | enabled. |
---|
908 | |
---|
909 | If this SPARC implementation supports on-chip caching |
---|
910 | and this is to be utilized, then it should be enabled during the |
---|
911 | reset application initialization code. |
---|
912 | |
---|
913 | In addition to the requirements described in the |
---|
914 | Board Support Packages chapter of the C |
---|
915 | Applications Users Manual for the reset code |
---|
916 | which is executed before the call to``rtems_initialize_executive``, the SPARC version has the following |
---|
917 | specific requirements: |
---|
918 | |
---|
919 | - Must leave the S bit of the status register set so that |
---|
920 | the SPARC remains in the supervisor state. |
---|
921 | |
---|
922 | - Must set stack pointer (sp) such that a minimum stack |
---|
923 | size of MINIMUM_STACK_SIZE bytes is provided for the``rtems_initialize_executive`` directive. |
---|
924 | |
---|
925 | - Must disable all external interrupts (i.e. set the pil |
---|
926 | to 15). |
---|
927 | |
---|
928 | - Must enable traps so window overflow and underflow |
---|
929 | conditions can be properly handled. |
---|
930 | |
---|
931 | - Must initialize the SPARC's initial trap table with at |
---|
932 | least trap handlers for register window overflow and register |
---|
933 | window underflow. |
---|
934 | |
---|
935 | .. COMMENT: COPYRIGHT (c) 1988-2002. |
---|
936 | |
---|
937 | .. COMMENT: On-Line Applications Research Corporation (OAR). |
---|
938 | |
---|
939 | .. COMMENT: All rights reserved. |
---|
940 | |
---|