1 | PowerPC Specific Information |
---|
2 | ############################ |
---|
3 | |
---|
4 | This chapter discusses the PowerPC architecture dependencies |
---|
5 | in this port of RTEMS. The PowerPC family has a wide variety |
---|
6 | of implementations by a range of vendors. Consequently, |
---|
7 | there are many, many CPU models within it. |
---|
8 | |
---|
9 | It is highly recommended that the PowerPC RTEMS |
---|
10 | application developer obtain and become familiar with the |
---|
11 | documentation for the processor being used as well as the |
---|
12 | specification for the revision of the PowerPC architecture which |
---|
13 | corresponds to that processor. |
---|
14 | |
---|
15 | **PowerPC Architecture Documents** |
---|
16 | |
---|
17 | For information on the PowerPC architecture, refer to |
---|
18 | the following documents available from Motorola and IBM: |
---|
19 | |
---|
20 | - *PowerPC Microprocessor Family: The Programming Environment* |
---|
21 | (Motorola Document MPRPPCFPE-01). |
---|
22 | |
---|
23 | - *IBM PPC403GB Embedded Controller User's Manual*. |
---|
24 | |
---|
25 | - *PoweRisControl MPC500 Family RCPU RISC Central Processing |
---|
26 | Unit Reference Manual* (Motorola Document RCPUURM/AD). |
---|
27 | |
---|
28 | - *PowerPC 601 RISC Microprocessor User's Manual* |
---|
29 | (Motorola Document MPR601UM/AD). |
---|
30 | |
---|
31 | - *PowerPC 603 RISC Microprocessor User's Manual* |
---|
32 | (Motorola Document MPR603UM/AD). |
---|
33 | |
---|
34 | - *PowerPC 603e RISC Microprocessor User's Manual* |
---|
35 | (Motorola Document MPR603EUM/AD). |
---|
36 | |
---|
37 | - *PowerPC 604 RISC Microprocessor User's Manual* |
---|
38 | (Motorola Document MPR604UM/AD). |
---|
39 | |
---|
40 | - *PowerPC MPC821 Portable Systems Microprocessor User's Manual* |
---|
41 | (Motorola Document MPC821UM/AD). |
---|
42 | |
---|
43 | - *PowerQUICC MPC860 User's Manual* (Motorola Document MPC860UM/AD). |
---|
44 | |
---|
45 | Motorola maintains an on-line electronic library for the PowerPC |
---|
46 | at the following URL: |
---|
47 | |
---|
48 | - http://www.mot.com/powerpc/library/library.html |
---|
49 | |
---|
50 | This site has a a wealth of information and examples. Many of the |
---|
51 | manuals are available from that site in electronic format. |
---|
52 | |
---|
53 | **PowerPC Processor Simulator Information** |
---|
54 | |
---|
55 | PSIM is a program which emulates the Instruction Set Architecture |
---|
56 | of the PowerPC microprocessor family. It is reely available in source |
---|
57 | code form under the terms of the GNU General Public License (version |
---|
58 | 2 or later). PSIM can be integrated with the GNU Debugger (gdb) to |
---|
59 | execute and debug PowerPC executables on non-PowerPC hosts. PSIM |
---|
60 | supports the addition of user provided device models which can be |
---|
61 | used to allow one to develop and debug embedded applications using |
---|
62 | the simulator. |
---|
63 | |
---|
64 | The latest version of PSIM is included in GDB and enabled on pre-built |
---|
65 | binaries provided by the RTEMS Project. |
---|
66 | |
---|
67 | CPU Model Dependent Features |
---|
68 | ============================ |
---|
69 | |
---|
70 | This section presents the set of features which vary |
---|
71 | across PowerPC implementations and are of importance to RTEMS. |
---|
72 | The set of CPU model feature macros are defined in the file``cpukit/score/cpu/powerpc/powerpc.h`` based upon the particular CPU |
---|
73 | model specified on the compilation command line. |
---|
74 | |
---|
75 | Alignment |
---|
76 | --------- |
---|
77 | |
---|
78 | The macro PPC_ALIGNMENT is set to the PowerPC model's worst case alignment |
---|
79 | requirement for data types on a byte boundary. This value is used |
---|
80 | to derive the alignment restrictions for memory allocated from |
---|
81 | regions and partitions. |
---|
82 | |
---|
83 | Cache Alignment |
---|
84 | --------------- |
---|
85 | |
---|
86 | The macro PPC_CACHE_ALIGNMENT is set to the line size of the cache. It is |
---|
87 | used to align the entry point of critical routines so that as much code |
---|
88 | as possible can be retrieved with the initial read into cache. This |
---|
89 | is done for the interrupt handler as well as the context switch routines. |
---|
90 | |
---|
91 | In addition, the "shortcut" data structure used by the PowerPC implementation |
---|
92 | to ease access to data elements frequently accessed by RTEMS routines |
---|
93 | implemented in assembly language is aligned using this value. |
---|
94 | |
---|
95 | Maximum Interrupts |
---|
96 | ------------------ |
---|
97 | |
---|
98 | The macro PPC_INTERRUPT_MAX is set to the number of exception sources |
---|
99 | supported by this PowerPC model. |
---|
100 | |
---|
101 | Has Double Precision Floating Point |
---|
102 | ----------------------------------- |
---|
103 | |
---|
104 | The macro PPC_HAS_DOUBLE is set to 1 to indicate that the PowerPC model |
---|
105 | has support for double precision floating point numbers. This is |
---|
106 | important because the floating point registers need only be four bytes |
---|
107 | wide (not eight) if double precision is not supported. |
---|
108 | |
---|
109 | Critical Interrupts |
---|
110 | ------------------- |
---|
111 | |
---|
112 | The macro PPC_HAS_RFCI is set to 1 to indicate that the PowerPC model |
---|
113 | has the Critical Interrupt capability as defined by the IBM 403 models. |
---|
114 | |
---|
115 | Use Multiword Load/Store Instructions |
---|
116 | ------------------------------------- |
---|
117 | |
---|
118 | The macro PPC_USE_MULTIPLE is set to 1 to indicate that multiword load and |
---|
119 | store instructions should be used to perform context switch operations. |
---|
120 | The relative efficiency of multiword load and store instructions versus |
---|
121 | an equivalent set of single word load and store instructions varies based |
---|
122 | upon the PowerPC model. |
---|
123 | |
---|
124 | Instruction Cache Size |
---|
125 | ---------------------- |
---|
126 | |
---|
127 | The macro PPC_I_CACHE is set to the size in bytes of the instruction cache. |
---|
128 | |
---|
129 | Data Cache Size |
---|
130 | --------------- |
---|
131 | |
---|
132 | The macro PPC_D_CACHE is set to the size in bytes of the data cache. |
---|
133 | |
---|
134 | Debug Model |
---|
135 | ----------- |
---|
136 | |
---|
137 | The macro PPC_DEBUG_MODEL is set to indicate the debug support features |
---|
138 | present in this CPU model. The following debug support feature sets |
---|
139 | are currently supported: |
---|
140 | |
---|
141 | *``PPC_DEBUG_MODEL_STANDARD``* |
---|
142 | indicates that the single-step trace enable (SE) and branch trace |
---|
143 | enable (BE) bits in the MSR are supported by this CPU model. |
---|
144 | |
---|
145 | *``PPC_DEBUG_MODEL_SINGLE_STEP_ONLY``* |
---|
146 | indicates that only the single-step trace enable (SE) bit in the MSR |
---|
147 | is supported by this CPU model. |
---|
148 | |
---|
149 | *``PPC_DEBUG_MODEL_IBM4xx``* |
---|
150 | indicates that the debug exception enable (DE) bit in the MSR is supported |
---|
151 | by this CPU model. At this time, this particular debug feature set |
---|
152 | has only been seen in the IBM 4xx series. |
---|
153 | |
---|
154 | Low Power Model |
---|
155 | ~~~~~~~~~~~~~~~ |
---|
156 | |
---|
157 | The macro PPC_LOW_POWER_MODE is set to indicate the low power model |
---|
158 | supported by this CPU model. The following low power modes are currently |
---|
159 | supported. |
---|
160 | |
---|
161 | *``PPC_LOW_POWER_MODE_NONE``* |
---|
162 | indicates that this CPU model has no low power mode support. |
---|
163 | |
---|
164 | *``PPC_LOW_POWER_MODE_STANDARD``* |
---|
165 | indicates that this CPU model follows the low power model defined for |
---|
166 | the PPC603e. |
---|
167 | |
---|
168 | Multilibs |
---|
169 | ========= |
---|
170 | |
---|
171 | The following multilibs are available: |
---|
172 | |
---|
173 | # ``.``: 32-bit PowerPC with FPU |
---|
174 | |
---|
175 | # ``nof``: 32-bit PowerPC with software floating point support |
---|
176 | |
---|
177 | # ``m403``: Instruction set for PPC403 with FPU |
---|
178 | |
---|
179 | # ``m505``: Instruction set for MPC505 with FPU |
---|
180 | |
---|
181 | # ``m603e``: Instruction set for MPC603e with FPU |
---|
182 | |
---|
183 | # ``m603e/nof``: Instruction set for MPC603e with software floating |
---|
184 | point support |
---|
185 | |
---|
186 | # ``m604``: Instruction set for MPC604 with FPU |
---|
187 | |
---|
188 | # ``m604/nof``: Instruction set for MPC604 with software floating point |
---|
189 | support |
---|
190 | |
---|
191 | # ``m860``: Instruction set for MPC860 with FPU |
---|
192 | |
---|
193 | # ``m7400``: Instruction set for MPC7500 with FPU |
---|
194 | |
---|
195 | # ``m7400/nof``: Instruction set for MPC7500 with software floating |
---|
196 | point support |
---|
197 | |
---|
198 | # ``m8540``: Instruction set for e200, e500 and e500v2 cores with |
---|
199 | single-precision FPU and SPE |
---|
200 | |
---|
201 | # ``m8540/gprsdouble``: Instruction set for e200, e500 and e500v2 cores |
---|
202 | with double-precision FPU and SPE |
---|
203 | |
---|
204 | # ``m8540/nof/nospe``: Instruction set for e200, e500 and e500v2 cores |
---|
205 | with software floating point support and no SPE |
---|
206 | |
---|
207 | # ``me6500/m32``: 32-bit instruction set for e6500 core with FPU and |
---|
208 | AltiVec |
---|
209 | |
---|
210 | # ``me6500/m32/nof/noaltivec``: 32-bit instruction set for e6500 core |
---|
211 | with software floating point support and no AltiVec |
---|
212 | |
---|
213 | Calling Conventions |
---|
214 | =================== |
---|
215 | |
---|
216 | RTEMS supports the Embedded Application Binary Interface (EABI) |
---|
217 | calling convention. Documentation for EABI is available by sending |
---|
218 | a message with a subject line of "EABI" to eabi@goth.sis.mot.com. |
---|
219 | |
---|
220 | Programming Model |
---|
221 | ----------------- |
---|
222 | |
---|
223 | This section discusses the programming model for the |
---|
224 | PowerPC architecture. |
---|
225 | |
---|
226 | Non-Floating Point Registers |
---|
227 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
---|
228 | |
---|
229 | The PowerPC architecture defines thirty-two non-floating point registers |
---|
230 | directly visible to the programmer. In thirty-two bit implementations, each |
---|
231 | register is thirty-two bits wide. In sixty-four bit implementations, each |
---|
232 | register is sixty-four bits wide. |
---|
233 | |
---|
234 | These registers are referred to as ``gpr0`` to ``gpr31``. |
---|
235 | |
---|
236 | Some of the registers serve defined roles in the EABI programming model. |
---|
237 | The following table describes the role of each of these registers: |
---|
238 | .. code:: c |
---|
239 | |
---|
240 | +---------------+----------------+------------------------------+ |
---|
241 | | Register Name | Alternate Name | Description | |
---|
242 | +---------------+----------------+------------------------------+ |
---|
243 | | r1 | sp | stack pointer | |
---|
244 | +---------------+----------------+------------------------------+ |
---|
245 | | | | global pointer to the Small | |
---|
246 | | r2 | na | Constant Area (SDA2) | |
---|
247 | +---------------+----------------+------------------------------+ |
---|
248 | | r3 - r12 | na | parameter and result passing | |
---|
249 | +---------------+----------------+------------------------------+ |
---|
250 | | | | global pointer to the Small | |
---|
251 | | r13 | na | Data Area (SDA) | |
---|
252 | +---------------+----------------+------------------------------+ |
---|
253 | |
---|
254 | Floating Point Registers |
---|
255 | ~~~~~~~~~~~~~~~~~~~~~~~~ |
---|
256 | |
---|
257 | The PowerPC architecture includes thirty-two, sixty-four bit |
---|
258 | floating point registers. All PowerPC floating point instructions |
---|
259 | interpret these registers as 32 double precision floating point registers, |
---|
260 | regardless of whether the processor has 64-bit or 32-bit implementation. |
---|
261 | |
---|
262 | The floating point status and control register (fpscr) records exceptions |
---|
263 | and the type of result generated by floating-point operations. |
---|
264 | Additionally, it controls the rounding mode of operations and allows the |
---|
265 | reporting of floating exceptions to be enabled or disabled. |
---|
266 | |
---|
267 | Special Registers |
---|
268 | ~~~~~~~~~~~~~~~~~ |
---|
269 | |
---|
270 | The PowerPC architecture includes a number of special registers |
---|
271 | which are critical to the programming model: |
---|
272 | |
---|
273 | *Machine State Register* |
---|
274 | The MSR contains the processor mode, power management mode, endian mode, |
---|
275 | exception information, privilege level, floating point available and |
---|
276 | floating point excepiton mode, address translation information and |
---|
277 | the exception prefix. |
---|
278 | |
---|
279 | *Link Register* |
---|
280 | The LR contains the return address after a function call. This register |
---|
281 | must be saved before a subsequent subroutine call can be made. The |
---|
282 | use of this register is discussed further in the *Call and Return |
---|
283 | Mechanism* section below. |
---|
284 | |
---|
285 | *Count Register* |
---|
286 | The CTR contains the iteration variable for some loops. It may also be used |
---|
287 | for indirect function calls and jumps. |
---|
288 | |
---|
289 | Call and Return Mechanism |
---|
290 | ------------------------- |
---|
291 | |
---|
292 | The PowerPC architecture supports a simple yet effective call |
---|
293 | and return mechanism. A subroutine is invoked |
---|
294 | via the "branch and link" (``bl``) and |
---|
295 | "brank and link absolute" (``bla``) |
---|
296 | instructions. This instructions place the return address |
---|
297 | in the Link Register (LR). The callee returns to the caller by |
---|
298 | executing a "branch unconditional to the link register" (``blr``) |
---|
299 | instruction. Thus the callee returns to the caller via a jump |
---|
300 | to the return address which is stored in the LR. |
---|
301 | |
---|
302 | The previous contents of the LR are not automatically saved |
---|
303 | by either the ``bl`` or ``bla``. It is the responsibility |
---|
304 | of the callee to save the contents of the LR before invoking |
---|
305 | another subroutine. If the callee invokes another subroutine, |
---|
306 | it must restore the LR before executing the ``blr`` instruction |
---|
307 | to return to the caller. |
---|
308 | |
---|
309 | It is important to note that the PowerPC subroutine |
---|
310 | call and return mechanism does not automatically save and |
---|
311 | restore any registers. |
---|
312 | |
---|
313 | The LR may be accessed as special purpose register 8 (``SPR8``) using the |
---|
314 | "move from special register" (``mfspr``) and |
---|
315 | "move to special register" (``mtspr``) instructions. |
---|
316 | |
---|
317 | Calling Mechanism |
---|
318 | ----------------- |
---|
319 | |
---|
320 | All RTEMS directives are invoked using the regular |
---|
321 | PowerPC EABI calling convention via the ``bl`` or``bla`` instructions. |
---|
322 | |
---|
323 | Register Usage |
---|
324 | -------------- |
---|
325 | |
---|
326 | As discussed above, the call instruction does not |
---|
327 | automatically save any registers. It is the responsibility |
---|
328 | of the callee to save and restore any registers which must be preserved |
---|
329 | across subroutine calls. The callee is responsible for saving |
---|
330 | callee-preserved registers to the program stack and restoring them |
---|
331 | before returning to the caller. |
---|
332 | |
---|
333 | Parameter Passing |
---|
334 | ----------------- |
---|
335 | |
---|
336 | RTEMS assumes that arguments are placed in the |
---|
337 | general purpose registers with the first argument in |
---|
338 | register 3 (``r3``), the second argument in general purpose |
---|
339 | register 4 (``r4``), and so forth until the seventh |
---|
340 | argument is in general purpose register 10 (``r10``). |
---|
341 | If there are more than seven arguments, then subsequent arguments |
---|
342 | are placed on the program stack. The following pseudo-code |
---|
343 | illustrates the typical sequence used to call a RTEMS directive |
---|
344 | with three (3) arguments: |
---|
345 | .. code:: c |
---|
346 | |
---|
347 | load third argument into r5 |
---|
348 | load second argument into r4 |
---|
349 | load first argument into r3 |
---|
350 | invoke directive |
---|
351 | |
---|
352 | Memory Model |
---|
353 | ============ |
---|
354 | |
---|
355 | Flat Memory Model |
---|
356 | ----------------- |
---|
357 | |
---|
358 | The PowerPC architecture supports a variety of memory models. |
---|
359 | RTEMS supports the PowerPC using a flat memory model with |
---|
360 | paging disabled. In this mode, the PowerPC automatically |
---|
361 | converts every address from a logical to a physical address |
---|
362 | each time it is used. The PowerPC uses information provided |
---|
363 | in the Block Address Translation (BAT) to convert these addresses. |
---|
364 | |
---|
365 | Implementations of the PowerPC architecture may be thirty-two or sixty-four bit. |
---|
366 | The PowerPC architecture supports a flat thirty-two or sixty-four bit address |
---|
367 | space with addresses ranging from 0x00000000 to 0xFFFFFFFF (4 |
---|
368 | gigabytes) in thirty-two bit implementations or to 0xFFFFFFFFFFFFFFFF |
---|
369 | in sixty-four bit implementations. Each address is represented |
---|
370 | by either a thirty-two bit or sixty-four bit value and is byte addressable. |
---|
371 | The address may be used to reference a single byte, half-word |
---|
372 | (2-bytes), word (4 bytes), or in sixty-four bit implementations a |
---|
373 | doubleword (8 bytes). Memory accesses within the address space are |
---|
374 | performed in big or little endian fashion by the PowerPC based |
---|
375 | upon the current setting of the Little-endian mode enable bit (LE) |
---|
376 | in the Machine State Register (MSR). While the processor is in |
---|
377 | big endian mode, memory accesses which are not properly aligned |
---|
378 | generate an "alignment exception" (vector offset 0x00600). In |
---|
379 | little endian mode, the PowerPC architecture does not require |
---|
380 | the processor to generate alignment exceptions. |
---|
381 | |
---|
382 | The following table lists the alignment requirements for a variety |
---|
383 | of data accesses: |
---|
384 | |
---|
385 | .. code:: c |
---|
386 | |
---|
387 | +--------------+-----------------------+ |
---|
388 | | Data Type | Alignment Requirement | |
---|
389 | +--------------+-----------------------+ |
---|
390 | | byte | 1 | |
---|
391 | | half-word | 2 | |
---|
392 | | word | 4 | |
---|
393 | | doubleword | 8 | |
---|
394 | +--------------+-----------------------+ |
---|
395 | |
---|
396 | Doubleword load and store operations are only available in |
---|
397 | PowerPC CPU models which are sixty-four bit implementations. |
---|
398 | |
---|
399 | RTEMS does not directly support any PowerPC Memory Management |
---|
400 | Units, therefore, virtual memory or segmentation systems |
---|
401 | involving the PowerPC are not supported. |
---|
402 | |
---|
403 | .. COMMENT: COPYRIGHT (c) 1989-2007. |
---|
404 | |
---|
405 | .. COMMENT: On-Line Applications Research Corporation (OAR). |
---|
406 | |
---|
407 | .. COMMENT: All rights reserved. |
---|
408 | |
---|
409 | Interrupt Processing |
---|
410 | ==================== |
---|
411 | |
---|
412 | Although RTEMS hides many of the processor dependent |
---|
413 | details of interrupt processing, it is important to understand |
---|
414 | how the RTEMS interrupt manager is mapped onto the processor's |
---|
415 | unique architecture. Discussed in this chapter are the PowerPC's |
---|
416 | interrupt response and control mechanisms as they pertain to |
---|
417 | RTEMS. |
---|
418 | |
---|
419 | RTEMS and associated documentation uses the terms interrupt and vector. |
---|
420 | In the PowerPC architecture, these terms correspond to exception and |
---|
421 | exception handler, respectively. The terms will be used interchangeably |
---|
422 | in this manual. |
---|
423 | |
---|
424 | Synchronous Versus Asynchronous Exceptions |
---|
425 | ------------------------------------------ |
---|
426 | |
---|
427 | In the PowerPC architecture exceptions can be either precise or |
---|
428 | imprecise and either synchronous or asynchronous. Asynchronous |
---|
429 | exceptions occur when an external event interrupts the processor. |
---|
430 | Synchronous exceptions are caused by the actions of an |
---|
431 | instruction. During an exception SRR0 is used to calculate where |
---|
432 | instruction processing should resume. All instructions prior to |
---|
433 | the resume instruction will have completed execution. SRR1 is used to |
---|
434 | store the machine status. |
---|
435 | |
---|
436 | There are two asynchronous nonmaskable, highest-priority exceptions |
---|
437 | system reset and machine check. There are two asynchrononous maskable |
---|
438 | low-priority exceptions external interrupt and decrementer. Nonmaskable |
---|
439 | execptions are never delayed, therefore if two nonmaskable, asynchronous |
---|
440 | exceptions occur in immediate succession, the state information saved by |
---|
441 | the first exception may be overwritten when the subsequent exception occurs. |
---|
442 | |
---|
443 | The PowerPC arcitecure defines one imprecise exception, the imprecise |
---|
444 | floating point enabled exception. All other synchronous exceptions are |
---|
445 | precise. The synchronization occuring during asynchronous precise |
---|
446 | exceptions conforms to the requirements for context synchronization. |
---|
447 | |
---|
448 | Vectoring of Interrupt Handler |
---|
449 | ------------------------------ |
---|
450 | |
---|
451 | Upon determining that an exception can be taken the PowerPC automatically |
---|
452 | performs the following actions: |
---|
453 | |
---|
454 | - an instruction address is loaded into SRR0 |
---|
455 | |
---|
456 | - bits 33-36 and 42-47 of SRR1 are loaded with information |
---|
457 | specific to the exception. |
---|
458 | |
---|
459 | - bits 0-32, 37-41, and 48-63 of SRR1 are loaded with corresponding |
---|
460 | bits from the MSR. |
---|
461 | |
---|
462 | - the MSR is set based upon the exception type. |
---|
463 | |
---|
464 | - instruction fetch and execution resumes, using the new MSR value, at a location specific to the execption type. |
---|
465 | |
---|
466 | If the interrupt handler was installed as an RTEMS |
---|
467 | interrupt handler, then upon receipt of the interrupt, the |
---|
468 | processor passes control to the RTEMS interrupt handler which |
---|
469 | performs the following actions: |
---|
470 | |
---|
471 | - saves the state of the interrupted task on it's stack, |
---|
472 | |
---|
473 | - saves all registers which are not normally preserved |
---|
474 | by the calling sequence so the user's interrupt service |
---|
475 | routine can be written in a high-level language. |
---|
476 | |
---|
477 | - if this is the outermost (i.e. non-nested) interrupt, |
---|
478 | then the RTEMS interrupt handler switches from the current stack |
---|
479 | to the interrupt stack, |
---|
480 | |
---|
481 | - enables exceptions, |
---|
482 | |
---|
483 | - invokes the vectors to a user interrupt service routine (ISR). |
---|
484 | |
---|
485 | Asynchronous interrupts are ignored while exceptions are |
---|
486 | disabled. Synchronous interrupts which occur while are |
---|
487 | disabled result in the CPU being forced into an error mode. |
---|
488 | |
---|
489 | A nested interrupt is processed similarly with the |
---|
490 | exception that the current stack need not be switched to the |
---|
491 | interrupt stack. |
---|
492 | |
---|
493 | Interrupt Levels |
---|
494 | ---------------- |
---|
495 | |
---|
496 | The PowerPC architecture supports only a single external |
---|
497 | asynchronous interrupt source. This interrupt source |
---|
498 | may be enabled and disabled via the External Interrupt Enable (EE) |
---|
499 | bit in the Machine State Register (MSR). Thus only two level (enabled |
---|
500 | and disabled) of external device interrupt priorities are |
---|
501 | directly supported by the PowerPC architecture. |
---|
502 | |
---|
503 | Some PowerPC implementations include a Critical Interrupt capability |
---|
504 | which is often used to receive interrupts from high priority external |
---|
505 | devices. |
---|
506 | |
---|
507 | The RTEMS interrupt level mapping scheme for the PowerPC is not |
---|
508 | a numeric level as on most RTEMS ports. It is a bit mapping in |
---|
509 | which the least three significiant bits of the interrupt level |
---|
510 | are mapped directly to the enabling of specific interrupt |
---|
511 | sources as follows: |
---|
512 | |
---|
513 | *Critical Interrupt* |
---|
514 | Setting bit 0 (the least significant bit) of the interrupt level |
---|
515 | enables the Critical Interrupt source, if it is available on this |
---|
516 | CPU model. |
---|
517 | |
---|
518 | *Machine Check* |
---|
519 | Setting bit 1 of the interrupt level enables Machine Check execptions. |
---|
520 | |
---|
521 | *External Interrupt* |
---|
522 | Setting bit 2 of the interrupt level enables External Interrupt execptions. |
---|
523 | |
---|
524 | All other bits in the RTEMS task interrupt level are ignored. |
---|
525 | |
---|
526 | Default Fatal Error Processing |
---|
527 | ============================== |
---|
528 | |
---|
529 | The default fatal error handler for this architecture performs the |
---|
530 | following actions: |
---|
531 | |
---|
532 | - places the error code in r3, and |
---|
533 | |
---|
534 | - executes a trap instruction which results in a Program Exception. |
---|
535 | |
---|
536 | If the Program Exception returns, then the following actions are performed: |
---|
537 | |
---|
538 | - disables all processor exceptions by loading a 0 into the MSR, and |
---|
539 | |
---|
540 | - goes into an infinite loop to simulate a halt processor instruction. |
---|
541 | |
---|
542 | Symmetric Multiprocessing |
---|
543 | ========================= |
---|
544 | |
---|
545 | SMP is supported. Available platforms are the Freescale QorIQ P series (e.g. |
---|
546 | P1020) and T series (e.g. T2080, T4240). |
---|
547 | |
---|
548 | Thread-Local Storage |
---|
549 | ==================== |
---|
550 | |
---|
551 | Thread-local storage is supported. |
---|
552 | |
---|
553 | Board Support Packages |
---|
554 | ====================== |
---|
555 | |
---|
556 | System Reset |
---|
557 | ------------ |
---|
558 | |
---|
559 | An RTEMS based application is initiated or |
---|
560 | re-initiated when the PowerPC processor is reset. The PowerPC |
---|
561 | architecture defines a Reset Exception, but leaves the |
---|
562 | details of the CPU state as implementation specific. Please |
---|
563 | refer to the User's Manual for the CPU model in question. |
---|
564 | |
---|
565 | In general, at power-up the PowerPC begin execution at address |
---|
566 | 0xFFF00100 in supervisor mode with all exceptions disabled. For |
---|
567 | soft resets, the CPU will vector to either 0xFFF00100 or 0x00000100 |
---|
568 | depending upon the setting of the Exception Prefix bit in the MSR. |
---|
569 | If during a soft reset, a Machine Check Exception occurs, then the |
---|
570 | CPU may execute a hard reset. |
---|
571 | |
---|
572 | Processor Initialization |
---|
573 | ------------------------ |
---|
574 | |
---|
575 | If this PowerPC implementation supports on-chip caching |
---|
576 | and this is to be utilized, then it should be enabled during the |
---|
577 | reset application initialization code. On-chip caching has been |
---|
578 | observed to prevent some emulators from working properly, so it |
---|
579 | may be necessary to run with caching disabled to use these emulators. |
---|
580 | |
---|
581 | In addition to the requirements described in the*Board Support Packages* chapter of the RTEMS C |
---|
582 | Applications User's Manual for the reset code |
---|
583 | which is executed before the call to ``rtems_initialize_executive``, |
---|
584 | the PowrePC version has the following specific requirements: |
---|
585 | |
---|
586 | - Must leave the PR bit of the Machine State Register (MSR) set |
---|
587 | to 0 so the PowerPC remains in the supervisor state. |
---|
588 | |
---|
589 | - Must set stack pointer (sp or r1) such that a minimum stack |
---|
590 | size of MINIMUM_STACK_SIZE bytes is provided for the RTEMS initialization |
---|
591 | sequence. |
---|
592 | |
---|
593 | - Must disable all external interrupts (i.e. clear the EI (EE) |
---|
594 | bit of the machine state register). |
---|
595 | |
---|
596 | - Must enable traps so window overflow and underflow |
---|
597 | conditions can be properly handled. |
---|
598 | |
---|
599 | - Must initialize the PowerPC's initial Exception Table with default |
---|
600 | handlers. |
---|
601 | |
---|
602 | .. COMMENT: COPYRIGHT (c) 1988-2002. |
---|
603 | |
---|
604 | .. COMMENT: On-Line Applications Research Corporation (OAR). |
---|
605 | |
---|
606 | .. COMMENT: All rights reserved. |
---|
607 | |
---|