1 | M68xxx and Coldfire Specific Information |
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2 | ######################################## |
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3 | |
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4 | This chapter discusses the Freescale (formerly Motorola) MC68xxx |
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5 | and Coldfire architectural dependencies. The MC68xxx family has a |
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6 | wide variety of CPU models within it based upon different CPU core |
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7 | implementations. Ignoring the Coldfire parts, the part numbers for |
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8 | these models are generally divided into MC680xx and MC683xx. The MC680xx |
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9 | models are more general purpose processors with no integrated peripherals. |
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10 | The MC683xx models, on the other hand, are more specialized and have a |
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11 | variety of peripherals on chip including sophisticated timers and serial |
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12 | communications controllers. |
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13 | |
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14 | **Architecture Documents** |
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15 | |
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16 | For information on the MC68xxx and Coldfire architecture, refer to the following documents available from Freescale website (:file:`http//www.freescale.com/`): |
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17 | |
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18 | - *M68000 Family Reference, Motorola, FR68K/D*. |
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19 | |
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20 | - *MC68020 User's Manual, Motorola, MC68020UM/AD*. |
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21 | |
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22 | - *MC68881/MC68882 Floating-Point Coprocessor User's Manual, |
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23 | Motorola, MC68881UM/AD*. |
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24 | |
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25 | CPU Model Dependent Features |
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26 | ============================ |
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27 | |
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28 | This section presents the set of features which vary |
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29 | across m68k/Coldfire implementations that are of importance to RTEMS. |
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30 | The set of CPU model feature macros are defined in the file``cpukit/score/cpu/m68k/m68k.h`` based upon the particular CPU |
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31 | model selected on the compilation command line. |
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32 | |
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33 | BFFFO Instruction |
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34 | ----------------- |
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35 | |
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36 | The macro ``M68K_HAS_BFFFO`` is set to 1 to indicate that |
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37 | this CPU model has the bfffo instruction. |
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38 | |
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39 | Vector Base Register |
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40 | -------------------- |
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41 | |
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42 | The macro ``M68K_HAS_VBR`` is set to 1 to indicate that |
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43 | this CPU model has a vector base register (vbr). |
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44 | |
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45 | Separate Stacks |
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46 | --------------- |
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47 | |
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48 | The macro ``M68K_HAS_SEPARATE_STACKS`` is set to 1 to |
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49 | indicate that this CPU model has separate interrupt, user, and |
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50 | supervisor mode stacks. |
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51 | |
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52 | Pre-Indexing Address Mode |
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53 | ------------------------- |
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54 | |
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55 | The macro ``M68K_HAS_PREINDEXING`` is set to 1 to indicate that |
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56 | this CPU model has the pre-indexing address mode. |
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57 | |
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58 | Extend Byte to Long Instruction |
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59 | ------------------------------- |
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60 | |
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61 | The macro ``M68K_HAS_EXTB_L`` is set to 1 to indicate that this CPU model |
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62 | has the extb.l instruction. This instruction is supposed to be available |
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63 | in all models based on the cpu32 core as well as mc68020 and up models. |
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64 | |
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65 | Calling Conventions |
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66 | =================== |
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67 | |
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68 | The MC68xxx architecture supports a simple yet effective call and |
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69 | return mechanism. A subroutine is invoked via the branch to subroutine |
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70 | (``bsr``) or the jump to subroutine (``jsr``) instructions. |
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71 | These instructions push the return address on the current stack. |
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72 | The return from subroutine (``rts``) instruction pops the return |
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73 | address off the current stack and transfers control to that instruction. |
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74 | It is is important to note that the MC68xxx call and return mechanism does |
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75 | not automatically save or restore any registers. It is the responsibility |
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76 | of the high-level language compiler to define the register preservation |
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77 | and usage convention. |
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78 | |
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79 | Calling Mechanism |
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80 | ----------------- |
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81 | |
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82 | All RTEMS directives are invoked using either a ``bsr`` or ``jsr`` |
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83 | instruction and return to the user application via the rts instruction. |
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84 | |
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85 | Register Usage |
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86 | -------------- |
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87 | |
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88 | As discussed above, the ``bsr`` and ``jsr`` instructions do not |
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89 | automatically save any registers. RTEMS uses the registers D0, D1, |
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90 | A0, and A1 as scratch registers. These registers are not preserved by |
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91 | RTEMS directives therefore, the contents of these registers should not |
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92 | be assumed upon return from any RTEMS directive. |
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93 | |
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94 | Parameter Passing |
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95 | ----------------- |
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96 | |
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97 | RTEMS assumes that arguments are placed on the current stack before |
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98 | the directive is invoked via the bsr or jsr instruction. The first |
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99 | argument is assumed to be closest to the return address on the stack. |
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100 | This means that the first argument of the C calling sequence is pushed |
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101 | last. The following pseudo-code illustrates the typical sequence used |
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102 | to call a RTEMS directive with three (3) arguments: |
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103 | .. code:: c |
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104 | |
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105 | push third argument |
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106 | push second argument |
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107 | push first argument |
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108 | invoke directive |
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109 | remove arguments from the stack |
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110 | |
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111 | The arguments to RTEMS are typically pushed onto the stack using a move |
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112 | instruction with a pre-decremented stack pointer as the destination. |
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113 | These arguments must be removed from the stack after control is returned |
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114 | to the caller. This removal is typically accomplished by adding the |
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115 | size of the argument list in bytes to the current stack pointer. |
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116 | |
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117 | Memory Model |
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118 | ============ |
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119 | |
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120 | The MC68xxx family supports a flat 32-bit address |
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121 | space with addresses ranging from 0x00000000 to 0xFFFFFFFF (4 |
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122 | gigabytes). Each address is represented by a 32-bit value and |
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123 | is byte addressable. The address may be used to reference a |
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124 | single byte, word (2-bytes), or long word (4 bytes). Memory |
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125 | accesses within this address space are performed in big endian |
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126 | fashion by the processors in this family. |
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127 | |
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128 | Some of the MC68xxx family members such as the |
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129 | MC68020, MC68030, and MC68040 support virtual memory and |
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130 | segmentation. The MC68020 requires external hardware support |
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131 | such as the MC68851 Paged Memory Management Unit coprocessor |
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132 | which is typically used to perform address translations for |
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133 | these systems. RTEMS does not support virtual memory or |
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134 | segmentation on any of the MC68xxx family members. |
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135 | |
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136 | Interrupt Processing |
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137 | ==================== |
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138 | |
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139 | Discussed in this section are the MC68xxx's interrupt response and |
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140 | control mechanisms as they pertain to RTEMS. |
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141 | |
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142 | Vectoring of an Interrupt Handler |
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143 | --------------------------------- |
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144 | |
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145 | Depending on whether or not the particular CPU supports a separate |
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146 | interrupt stack, the MC68xxx family has two different interrupt handling |
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147 | models. |
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148 | |
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149 | Models Without Separate Interrupt Stacks |
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150 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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151 | |
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152 | Upon receipt of an interrupt the MC68xxx family members without separate |
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153 | interrupt stacks automatically perform the following actions: |
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154 | |
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155 | - To Be Written |
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156 | |
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157 | Models With Separate Interrupt Stacks |
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158 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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159 | |
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160 | Upon receipt of an interrupt the MC68xxx family members with separate |
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161 | interrupt stacks automatically perform the following actions: |
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162 | |
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163 | - saves the current status register (SR), |
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164 | |
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165 | - clears the master/interrupt (M) bit of the SR to |
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166 | indicate the switch from master state to interrupt state, |
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167 | |
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168 | - sets the privilege mode to supervisor, |
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169 | |
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170 | - suppresses tracing, |
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171 | |
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172 | - sets the interrupt mask level equal to the level of the |
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173 | interrupt being serviced, |
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174 | |
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175 | - pushes an interrupt stack frame (ISF), which includes |
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176 | the program counter (PC), the status register (SR), and the |
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177 | format/exception vector offset (FVO) word, onto the supervisor |
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178 | and interrupt stacks, |
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179 | |
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180 | - switches the current stack to the interrupt stack and |
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181 | vectors to an interrupt service routine (ISR). If the ISR was |
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182 | installed with the interrupt_catch directive, then the RTEMS |
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183 | interrupt handler will begin execution. The RTEMS interrupt |
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184 | handler saves all registers which are not preserved according to |
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185 | the calling conventions and invokes the application's ISR. |
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186 | |
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187 | A nested interrupt is processed similarly by these |
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188 | CPU models with the exception that only a single ISF is placed |
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189 | on the interrupt stack and the current stack need not be |
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190 | switched. |
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191 | |
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192 | The FVO word in the Interrupt Stack Frame is examined |
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193 | by RTEMS to determine when an outer most interrupt is being |
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194 | exited. Since the FVO is used by RTEMS for this purpose, the |
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195 | user application code MUST NOT modify this field. |
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196 | |
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197 | The following shows the Interrupt Stack Frame for |
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198 | MC68xxx CPU models with separate interrupt stacks: |
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199 | |
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200 | +----------------------+-----+ |
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201 | | Status Register | 0x0 | |
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202 | +----------------------+-----+ |
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203 | | Program Counter High | 0x2 | |
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204 | +----------------------+-----+ |
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205 | | Program Counter Low | 0x4 | |
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206 | +----------------------+-----+ |
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207 | | Format/Vector Offset | 0x6 | |
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208 | +----------------------+-----+ |
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209 | |
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210 | |
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211 | CPU Models Without VBR and RAM at 0 |
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212 | ----------------------------------- |
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213 | |
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214 | This is from a post by Zoltan Kocsi <zoltan@bendor.com.au> and is |
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215 | a nice trick in certain situations. In his words: |
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216 | |
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217 | I think somebody on this list asked about the interupt vector handling |
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218 | w/o VBR and RAM at 0. The usual trick is to initialise the vector table |
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219 | (except the first 2 two entries, of course) to point to the same location |
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220 | BUT you also add the vector number times 0x1000000 to them. That is, |
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221 | bits 31-24 contain the vector number and 23-0 the address of the common |
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222 | handler. Since the PC is 32 bit wide but the actual address bus is only |
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223 | 24, the top byte will be in the PC but will be ignored when jumping onto |
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224 | your routine. |
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225 | |
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226 | Then your common interrupt routine gets this info by loading the PC |
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227 | into some register and based on that info, you can jump to a vector in |
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228 | a vector table pointed by a virtual VBR: |
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229 | .. code:: c |
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230 | |
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231 | // |
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232 | // Real vector table at 0 |
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233 | // |
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234 | .long initial_sp |
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235 | .long initial_pc |
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236 | .long myhandler+0x02000000 |
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237 | .long myhandler+0x03000000 |
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238 | .long myhandler+0x04000000 |
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239 | ... |
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240 | .long myhandler+0xff000000 |
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241 | // |
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242 | // This handler will jump to the interrupt routine of which |
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243 | // the address is stored at VBR[ vector_no ] |
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244 | // The registers and stackframe will be intact, the interrupt |
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245 | // routine will see exactly what it would see if it was called |
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246 | // directly from the HW vector table at 0. |
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247 | // |
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248 | .comm VBR,4,2 // This defines the 'virtual' VBR |
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249 | // From C: extern void \*VBR; |
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250 | myhandler: // At entry, PC contains the full vector |
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251 | move.l %d0,-(%sp) // Save d0 |
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252 | move.l %a0,-(%sp) // Save a0 |
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253 | lea 0(%pc),%a0 // Get the value of the PC |
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254 | move.l %a0,%d0 // Copy it to a data reg, d0 is VV?????? |
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255 | swap %d0 // Now d0 is ????VV?? |
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256 | and.w #0xff00,%d0 // Now d0 is ????VV00 (1) |
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257 | lsr.w #6,%d0 // Now d0.w contains the VBR table offset |
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258 | move.l VBR,%a0 // Get the address from VBR to a0 |
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259 | move.l (%a0,%d0.w),%a0 // Fetch the vector |
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260 | move.l 4(%sp),%d0 // Restore d0 |
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261 | move.l %a0,4(%sp) // Place target address to the stack |
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262 | move.l (%sp)+,%a0 // Restore a0, target address is on TOS |
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263 | ret // This will jump to the handler and |
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264 | // restore the stack |
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265 | (1) If 'myhandler' is guaranteed to be in the first 64K, e.g. just |
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266 | after the vector table then that insn is not needed. |
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267 | |
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268 | There are probably shorter ways to do this, but it I believe is enough |
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269 | to illustrate the trick. Optimisation is left as an exercise to the |
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270 | reader :-) |
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271 | |
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272 | Interrupt Levels |
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273 | ---------------- |
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274 | |
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275 | Eight levels (0-7) of interrupt priorities are |
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276 | supported by MC68xxx family members with level seven (7) being |
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277 | the highest priority. Level zero (0) indicates that interrupts |
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278 | are fully enabled. Interrupt requests for interrupts with |
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279 | priorities less than or equal to the current interrupt mask |
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280 | level are ignored. |
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281 | |
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282 | Although RTEMS supports 256 interrupt levels, the |
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283 | MC68xxx family only supports eight. RTEMS interrupt levels 0 |
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284 | through 7 directly correspond to MC68xxx interrupt levels. All |
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285 | other RTEMS interrupt levels are undefined and their behavior is |
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286 | unpredictable. |
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287 | |
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288 | Default Fatal Error Processing |
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289 | ============================== |
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290 | |
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291 | The default fatal error handler for this architecture disables processor |
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292 | interrupts to level 7, places the error code in D0, and executes a``stop`` instruction to simulate a halt processor instruction. |
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293 | |
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294 | Symmetric Multiprocessing |
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295 | ========================= |
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296 | |
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297 | SMP is not supported. |
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298 | |
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299 | Thread-Local Storage |
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300 | ==================== |
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301 | |
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302 | Thread-local storage is supported. |
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303 | |
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304 | Board Support Packages |
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305 | ====================== |
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306 | |
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307 | System Reset |
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308 | ------------ |
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309 | |
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310 | An RTEMS based application is initiated or re-initiated when the MC68020 |
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311 | processor is reset. When the MC68020 is reset, the processor performs |
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312 | the following actions: |
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313 | |
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314 | - The tracing bits of the status register are cleared to |
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315 | disable tracing. |
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316 | |
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317 | - The supervisor interrupt state is entered by setting the |
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318 | supervisor (S) bit and clearing the master/interrupt (M) bit of |
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319 | the status register. |
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320 | |
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321 | - The interrupt mask of the status register is set to |
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322 | level 7 to effectively disable all maskable interrupts. |
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323 | |
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324 | - The vector base register (VBR) is set to zero. |
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325 | |
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326 | - The cache control register (CACR) is set to zero to |
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327 | disable and freeze the processor cache. |
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328 | |
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329 | - The interrupt stack pointer (ISP) is set to the value |
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330 | stored at vector 0 (bytes 0-3) of the exception vector table |
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331 | (EVT). |
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332 | |
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333 | - The program counter (PC) is set to the value stored at |
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334 | vector 1 (bytes 4-7) of the EVT. |
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335 | |
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336 | - The processor begins execution at the address stored in |
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337 | the PC. |
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338 | |
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339 | Processor Initialization |
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340 | ------------------------ |
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341 | |
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342 | The address of the application's initialization code should be stored in |
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343 | the first vector of the EVT which will allow the immediate vectoring to |
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344 | the application code. If the application requires that the VBR be some |
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345 | value besides zero, then it should be set to the required value at this |
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346 | point. All tasks share the same MC68020's VBR value. Because interrupts |
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347 | are enabled automatically by RTEMS as part of the context switch to the |
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348 | first task, the VBR MUST be set by either RTEMS of the BSP before this |
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349 | occurs ensure correct interrupt vectoring. If processor caching is |
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350 | to be utilized, then it should be enabled during the reset application |
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351 | initialization code. |
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352 | |
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353 | In addition to the requirements described in the |
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354 | Board Support Packages chapter of the Applications User's |
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355 | Manual for the reset code which is executed before the call to |
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356 | initialize executive, the MC68020 version has the following |
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357 | specific requirements: |
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358 | |
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359 | - Must leave the S bit of the status register set so that |
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360 | the MC68020 remains in the supervisor state. |
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361 | |
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362 | - Must set the M bit of the status register to remove the |
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363 | MC68020 from the interrupt state. |
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364 | |
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365 | - Must set the master stack pointer (MSP) such that a |
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366 | minimum stack size of MINIMUM_STACK_SIZE bytes is provided for |
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367 | the initialize executive directive. |
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368 | |
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369 | - Must initialize the MC68020's vector table. |
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370 | |
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371 | .. COMMENT: Copyright (c) 2014 embedded brains GmbH. All rights reserved. |
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372 | |
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