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1Lattice Mico32 Specific Information
2###################################
3
4This chaper discusses the Lattice Mico32 architecture dependencies in
5this port of RTEMS. The Lattice Mico32 is a 32-bit Harvard, RISC
6architecture "soft" microprocessor, available for free with an open IP
7core licensing agreement. Although mainly targeted for Lattice FPGA
8devices the microprocessor can be implemented on other vendors' FPGAs,
9too.
10
11**Architecture Documents**
12
13For information on the Lattice Mico32 architecture, refer to the
14following documents available from Lattice Semiconductor:file:`http://www.latticesemi.com/`.
15
16- *"LatticeMico32 Processor Reference Manual"*:file:`http://www.latticesemi.com/dynamic/view_document.cfm?document_id=20890`
17
18CPU Model Dependent Features
19============================
20
21The Lattice Mico32 architecture allows for different configurations of
22the processor. This port is based on the assumption that the following options are implemented:
23
24- hardware multiplier
25
26- hardware divider
27
28- hardware barrel shifter
29
30- sign extension instructions
31
32- instruction cache
33
34- data cache
35
36- debug
37
38Register Architecture
39=====================
40
41This section gives a brief introduction to the register architecture
42of the Lattice Mico32 processor.
43
44The Lattice Mico32 is a RISC archictecture processor with a
4532-register file of 32-bit registers.
46
47Register Name
48
49Function
50
51r0
52
53holds value zero
54
55r1-r25
56
57general purpose
58
59r26/gp
60
61general pupose / global pointer
62
63r27/fp
64
65general pupose / frame pointer
66
67r28/sp
68
69stack pointer
70
71r29/ra
72
73return address
74
75r30/ea
76
77exception address
78
79r31/ba
80
81breakpoint address
82
83Note that on processor startup all register values are undefined
84including r0, thus r0 has to be initialized to zero.
85
86Calling Conventions
87===================
88
89Calling Mechanism
90-----------------
91
92A call instruction places the return address to register r29 and a
93return from subroutine (ret) is actually a branch to r29/ra.
94
95Register Usage
96--------------
97
98A subroutine may freely use registers r1 to r10 which are *not*
99preserved across subroutine invocations.
100
101Parameter Passing
102-----------------
103
104When calling a C function the first eight arguments are stored in
105registers r1 to r8. Registers r1 and r2 hold the return value.
106
107Memory Model
108============
109
110The Lattice Mico32 processor supports a flat memory model with a 4
111Gbyte address space with 32-bit addresses.
112
113The following data types are supported:
114
115Type
116
117Bits
118
119C Compiler Type
120
121unsigned byte
122
1238
124
125unsigned char
126
127signed byte
128
1298
130
131char
132
133unsigned half-word
134
13516
136
137unsigned short
138
139signed half-word
140
14116
142
143short
144
145unsigned word
146
14732
148
149unsigned int / unsigned long
150
151signed word
152
15332
154
155int / long
156
157Data accesses need to be aligned, with unaligned accesses result are
158undefined.
159
160Interrupt Processing
161====================
162
163The Lattice Mico32 has 32 interrupt lines which are however served by
164only one exception vector. When an interrupt occurs following happens:
165
166- address of next instruction placed in r30/ea
167
168- IE field of IE CSR saved to EIE field and IE field cleared preventing further exceptions from occuring.
169
170- branch to interrupt exception address EBA CSR + 0xC0
171
172The interrupt exception handler determines from the state of the
173interrupt pending registers (IP CSR) and interrupt enable register (IE
174CSR) which interrupt to serve and jumps to the interrupt routine
175pointed to by the corresponding interrupt vector.
176
177For now there is no dedicated interrupt stack so every task in
178the system MUST have enough stack space to accommodate the worst
179case stack usage of that particular task and the interrupt
180service routines COMBINED.
181
182Nested interrupts are not supported.
183
184Default Fatal Error Processing
185==============================
186
187Upon detection of a fatal error by either the application or RTEMS during
188initialization the ``rtems_fatal_error_occurred`` directive supplied
189by the Fatal Error Manager is invoked.  The Fatal Error Manager will
190invoke the user-supplied fatal error handlers.  If no user-supplied
191handlers are configured or all of them return without taking action to
192shutdown the processor or reset, a default fatal error handler is invoked.
193
194Most of the action performed as part of processing the fatal error are
195described in detail in the Fatal Error Manager chapter in the User's
196Guide.  However, the if no user provided extension or BSP specific fatal
197error handler takes action, the final default action is to invoke a
198CPU architecture specific function.  Typically this function disables
199interrupts and halts the processor.
200
201In each of the architecture specific chapters, this describes the precise
202operations of the default CPU specific fatal error handler.
203
204Symmetric Multiprocessing
205=========================
206
207SMP is not supported.
208
209Thread-Local Storage
210====================
211
212Thread-local storage is not implemented.
213
214Board Support Packages
215======================
216
217An RTEMS Board Support Package (BSP) must be designed to support a
218particular processor model and target board combination.
219
220In each of the architecture specific chapters, this section will present
221a discussion of architecture specific BSP issues.   For more information
222on developing a BSP, refer to BSP and Device Driver Development Guide
223and the chapter titled Board Support Packages in the RTEMS
224Applications User's Guide.
225
226System Reset
227------------
228
229An RTEMS based application is initiated or re-initiated when the processor
230is reset.
231
232.. COMMENT: Copyright (c) 2014 embedded brains GmbH.  All rights reserved.
233
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