1 | Lattice Mico32 Specific Information |
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2 | ################################### |
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3 | |
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4 | This chaper discusses the Lattice Mico32 architecture dependencies in |
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5 | this port of RTEMS. The Lattice Mico32 is a 32-bit Harvard, RISC |
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6 | architecture "soft" microprocessor, available for free with an open IP |
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7 | core licensing agreement. Although mainly targeted for Lattice FPGA |
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8 | devices the microprocessor can be implemented on other vendors' FPGAs, |
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9 | too. |
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10 | |
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11 | **Architecture Documents** |
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12 | |
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13 | For information on the Lattice Mico32 architecture, refer to the |
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14 | following documents available from Lattice Semiconductor:file:`http://www.latticesemi.com/`. |
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15 | |
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16 | - *"LatticeMico32 Processor Reference Manual"*:file:`http://www.latticesemi.com/dynamic/view_document.cfm?document_id=20890` |
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17 | |
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18 | CPU Model Dependent Features |
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19 | ============================ |
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20 | |
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21 | The Lattice Mico32 architecture allows for different configurations of |
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22 | the processor. This port is based on the assumption that the following options are implemented: |
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23 | |
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24 | - hardware multiplier |
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25 | |
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26 | - hardware divider |
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27 | |
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28 | - hardware barrel shifter |
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29 | |
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30 | - sign extension instructions |
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31 | |
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32 | - instruction cache |
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33 | |
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34 | - data cache |
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35 | |
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36 | - debug |
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37 | |
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38 | Register Architecture |
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39 | ===================== |
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40 | |
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41 | This section gives a brief introduction to the register architecture |
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42 | of the Lattice Mico32 processor. |
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43 | |
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44 | The Lattice Mico32 is a RISC archictecture processor with a |
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45 | 32-register file of 32-bit registers. |
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46 | |
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47 | Register Name |
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48 | |
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49 | Function |
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50 | |
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51 | r0 |
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52 | |
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53 | holds value zero |
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54 | |
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55 | r1-r25 |
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56 | |
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57 | general purpose |
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58 | |
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59 | r26/gp |
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60 | |
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61 | general pupose / global pointer |
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62 | |
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63 | r27/fp |
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64 | |
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65 | general pupose / frame pointer |
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66 | |
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67 | r28/sp |
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68 | |
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69 | stack pointer |
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70 | |
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71 | r29/ra |
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72 | |
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73 | return address |
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74 | |
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75 | r30/ea |
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76 | |
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77 | exception address |
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78 | |
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79 | r31/ba |
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80 | |
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81 | breakpoint address |
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82 | |
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83 | Note that on processor startup all register values are undefined |
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84 | including r0, thus r0 has to be initialized to zero. |
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85 | |
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86 | Calling Conventions |
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87 | =================== |
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88 | |
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89 | Calling Mechanism |
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90 | ----------------- |
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91 | |
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92 | A call instruction places the return address to register r29 and a |
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93 | return from subroutine (ret) is actually a branch to r29/ra. |
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94 | |
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95 | Register Usage |
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96 | -------------- |
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97 | |
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98 | A subroutine may freely use registers r1 to r10 which are *not* |
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99 | preserved across subroutine invocations. |
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100 | |
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101 | Parameter Passing |
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102 | ----------------- |
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103 | |
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104 | When calling a C function the first eight arguments are stored in |
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105 | registers r1 to r8. Registers r1 and r2 hold the return value. |
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106 | |
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107 | Memory Model |
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108 | ============ |
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109 | |
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110 | The Lattice Mico32 processor supports a flat memory model with a 4 |
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111 | Gbyte address space with 32-bit addresses. |
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112 | |
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113 | The following data types are supported: |
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114 | |
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115 | Type |
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116 | |
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117 | Bits |
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118 | |
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119 | C Compiler Type |
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120 | |
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121 | unsigned byte |
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122 | |
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123 | 8 |
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124 | |
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125 | unsigned char |
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126 | |
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127 | signed byte |
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128 | |
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129 | 8 |
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130 | |
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131 | char |
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132 | |
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133 | unsigned half-word |
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134 | |
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135 | 16 |
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136 | |
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137 | unsigned short |
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138 | |
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139 | signed half-word |
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140 | |
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141 | 16 |
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142 | |
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143 | short |
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144 | |
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145 | unsigned word |
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146 | |
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147 | 32 |
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148 | |
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149 | unsigned int / unsigned long |
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150 | |
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151 | signed word |
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152 | |
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153 | 32 |
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154 | |
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155 | int / long |
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156 | |
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157 | Data accesses need to be aligned, with unaligned accesses result are |
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158 | undefined. |
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159 | |
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160 | Interrupt Processing |
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161 | ==================== |
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162 | |
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163 | The Lattice Mico32 has 32 interrupt lines which are however served by |
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164 | only one exception vector. When an interrupt occurs following happens: |
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165 | |
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166 | - address of next instruction placed in r30/ea |
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167 | |
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168 | - IE field of IE CSR saved to EIE field and IE field cleared preventing further exceptions from occuring. |
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169 | |
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170 | - branch to interrupt exception address EBA CSR + 0xC0 |
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171 | |
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172 | The interrupt exception handler determines from the state of the |
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173 | interrupt pending registers (IP CSR) and interrupt enable register (IE |
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174 | CSR) which interrupt to serve and jumps to the interrupt routine |
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175 | pointed to by the corresponding interrupt vector. |
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176 | |
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177 | For now there is no dedicated interrupt stack so every task in |
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178 | the system MUST have enough stack space to accommodate the worst |
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179 | case stack usage of that particular task and the interrupt |
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180 | service routines COMBINED. |
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181 | |
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182 | Nested interrupts are not supported. |
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183 | |
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184 | Default Fatal Error Processing |
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185 | ============================== |
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186 | |
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187 | Upon detection of a fatal error by either the application or RTEMS during |
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188 | initialization the ``rtems_fatal_error_occurred`` directive supplied |
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189 | by the Fatal Error Manager is invoked. The Fatal Error Manager will |
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190 | invoke the user-supplied fatal error handlers. If no user-supplied |
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191 | handlers are configured or all of them return without taking action to |
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192 | shutdown the processor or reset, a default fatal error handler is invoked. |
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193 | |
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194 | Most of the action performed as part of processing the fatal error are |
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195 | described in detail in the Fatal Error Manager chapter in the User's |
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196 | Guide. However, the if no user provided extension or BSP specific fatal |
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197 | error handler takes action, the final default action is to invoke a |
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198 | CPU architecture specific function. Typically this function disables |
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199 | interrupts and halts the processor. |
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200 | |
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201 | In each of the architecture specific chapters, this describes the precise |
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202 | operations of the default CPU specific fatal error handler. |
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203 | |
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204 | Symmetric Multiprocessing |
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205 | ========================= |
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206 | |
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207 | SMP is not supported. |
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208 | |
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209 | Thread-Local Storage |
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210 | ==================== |
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211 | |
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212 | Thread-local storage is not implemented. |
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213 | |
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214 | Board Support Packages |
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215 | ====================== |
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216 | |
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217 | An RTEMS Board Support Package (BSP) must be designed to support a |
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218 | particular processor model and target board combination. |
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219 | |
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220 | In each of the architecture specific chapters, this section will present |
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221 | a discussion of architecture specific BSP issues. For more information |
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222 | on developing a BSP, refer to BSP and Device Driver Development Guide |
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223 | and the chapter titled Board Support Packages in the RTEMS |
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224 | Applications User's Guide. |
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225 | |
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226 | System Reset |
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227 | ------------ |
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228 | |
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229 | An RTEMS based application is initiated or re-initiated when the processor |
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230 | is reset. |
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231 | |
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232 | .. COMMENT: Copyright (c) 2014 embedded brains GmbH. All rights reserved. |
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233 | |
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