source: rtems-docs/cpu_supplement/ephiphany.rst @ d755cbd

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1Epiphany Specific Information
2#############################
3
4This chapter discusses the`Epiphany Architecture <http://adapteva.com/docs/epiphany_sdk_ref.pdf>`_
5dependencies in this port of RTEMS. Epiphany is a chip that can come with 16 and
664 cores, each of which can run RTEMS separately or they can work together to
7run a SMP RTEMS application.
8
9**Architecture Documents**
10
11For information on the Epiphany architecture refer to the`Epiphany Architecture Reference <http://adapteva.com/docs/epiphany_arch_ref.pdf>`_.
12
13Calling Conventions
14===================
15
16Please refer to the`Epiphany SDK <http://adapteva.com/docs/epiphany_sdk_ref.pdf>`_
17Appendix A: Application Binary Interface
18
19Floating Point Unit
20-------------------
21
22A floating point unit is currently not supported.
23
24Memory Model
25============
26
27A flat 32-bit memory model is supported, no caches. Each core has its own 32 KiB
28strictly ordered local memory along with an access to a shared 32 MiB external
29DRAM.
30
31Interrupt Processing
32====================
33
34Every Epiphany core has 10 exception types:
35
36- Reset
37
38- Software Exception
39
40- Data Page Fault
41
42- Timer 0
43
44- Timer 1
45
46- Message Interrupt
47
48- DMA0 Interrupt
49
50- DMA1 Interrupt
51
52- WANT Interrupt
53
54- User Interrupt
55
56Interrupt Levels
57----------------
58
59There are only two levels: interrupts enabled and interrupts disabled.
60
61Interrupt Stack
62---------------
63
64The Epiphany RTEMS port uses a dedicated software interrupt stack.
65The stack for interrupts is allocated during interrupt driver initialization.
66When an  interrupt is entered, the _ISR_Handler routine is responsible for
67switching from the interrupted task stack to RTEMS software interrupt stack.
68
69Default Fatal Error Processing
70==============================
71
72The default fatal error handler for this architecture performs the
73following actions:
74
75- disables operating system supported interrupts (IRQ),
76
77- places the error code in ``r0``, and
78
79- executes an infinite loop to simulate a halt processor instruction.
80
81Symmetric Multiprocessing
82=========================
83
84SMP is not supported.
85
86.. COMMENT: COPYRIGHT (c) 1988-2002.
87
88.. COMMENT: On-Line Applications Research Corporation (OAR).
89
90.. COMMENT: All rights reserved.
91
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