1 | .. comment SPDX-License-Identifier: CC-BY-SA-4.0 |
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2 | |
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3 | .. COMMENT: COPYRIGHT (c) 1988-2002. |
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4 | .. COMMENT: On-Line Applications Research Corporation (OAR). |
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5 | .. COMMENT: All rights reserved. |
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6 | |
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7 | SuperH Specific Information |
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8 | ########################### |
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9 | |
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10 | This chapter discusses the SuperH architecture dependencies in this port of |
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11 | RTEMS. The SuperH family has a wide variety of implementations by a wide range |
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12 | of vendors. Consequently, there are many, many CPU models within it. |
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13 | |
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14 | **Architecture Documents** |
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15 | |
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16 | For information on the SuperH architecture, refer to the following documents |
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17 | available from VENDOR (http://www.XXX.com/): |
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18 | |
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19 | - *SuperH Family Reference, VENDOR, PART NUMBER*. |
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20 | |
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21 | CPU Model Dependent Features |
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22 | ============================ |
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23 | |
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24 | This chapter presents the set of features which vary across SuperH |
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25 | implementations and are of importance to RTEMS. The set of CPU model feature |
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26 | macros are defined in the file ``cpukit/score/cpu/sh/sh.h`` based upon the |
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27 | particular CPU model specified on the compilation command line. |
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28 | |
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29 | Another Optional Feature |
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30 | ------------------------ |
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31 | |
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32 | The macro XXX |
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33 | |
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34 | Calling Conventions |
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35 | =================== |
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36 | |
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37 | Calling Mechanism |
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38 | ----------------- |
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39 | |
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40 | All RTEMS directives are invoked using a ``XXX`` instruction and return to the |
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41 | user application via the ``XXX`` instruction. |
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42 | |
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43 | Register Usage |
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44 | -------------- |
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45 | |
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46 | The SH1 has 16 general registers (r0..r15). |
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47 | |
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48 | - r0..r3 used as general volatile registers |
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49 | |
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50 | - r4..r7 used to pass up to 4 arguments to functions, arguments above 4 are |
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51 | passed via the stack) |
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52 | |
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53 | - r8..13 caller saved registers (i.e. push them to the stack if you need them |
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54 | inside of a function) |
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55 | |
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56 | - r14 frame pointer |
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57 | |
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58 | - r15 stack pointer |
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59 | |
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60 | Parameter Passing |
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61 | ----------------- |
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62 | |
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63 | XXX |
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64 | |
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65 | Memory Model |
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66 | ============ |
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67 | |
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68 | Flat Memory Model |
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69 | ----------------- |
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70 | |
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71 | The SuperH family supports a flat 32-bit address space with addresses ranging |
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72 | from 0x00000000 to 0xFFFFFFFF (4 gigabytes). Each address is represented by a |
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73 | 32-bit value and is byte addressable. The address may be used to reference a |
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74 | single byte, word (2-bytes), or long word (4 bytes). Memory accesses within |
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75 | this address space are performed in big endian fashion by the processors in |
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76 | this family. |
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77 | |
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78 | Some of the SuperH family members support virtual memory and segmentation. |
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79 | RTEMS does not support virtual memory or segmentation on any of the SuperH |
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80 | family members. It is the responsibility of the BSP to initialize the mapping |
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81 | for a flat memory model. |
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82 | |
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83 | Interrupt Processing |
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84 | ==================== |
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85 | |
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86 | Although RTEMS hides many of the processor dependent details of interrupt |
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87 | processing, it is important to understand how the RTEMS interrupt manager is |
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88 | mapped onto the processor's unique architecture. Discussed in this chapter are |
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89 | the MIPS's interrupt response and control mechanisms as they pertain to RTEMS. |
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90 | |
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91 | Vectoring of an Interrupt Handler |
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92 | --------------------------------- |
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93 | |
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94 | Upon receipt of an interrupt the XXX family members with separate interrupt |
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95 | stacks automatically perform the following actions: |
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96 | |
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97 | - TBD |
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98 | |
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99 | A nested interrupt is processed similarly by these CPU models with the |
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100 | exception that only a single ISF is placed on the interrupt stack and the |
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101 | current stack need not be switched. |
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102 | |
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103 | Interrupt Levels |
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104 | ---------------- |
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105 | |
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106 | TBD |
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107 | |
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108 | Default Fatal Error Processing |
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109 | ============================== |
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110 | |
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111 | The default fatal error handler for this architecture disables processor |
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112 | interrupts, places the error code in *XXX*, and executes a ``XXX`` instruction |
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113 | to simulate a halt processor instruction. |
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114 | |
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115 | Symmetric Multiprocessing |
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116 | ========================= |
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117 | |
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118 | SMP is not supported. |
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119 | |
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120 | Thread-Local Storage |
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121 | ==================== |
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122 | |
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123 | Thread-local storage is not implemented. |
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124 | |
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125 | Board Support Packages |
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126 | ====================== |
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127 | |
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128 | System Reset |
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129 | ------------ |
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130 | |
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131 | An RTEMS based application is initiated or |
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132 | re-initiated when the processor is reset. When the |
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133 | processor is reset, it performs the following actions: |
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134 | |
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135 | - TBD |
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136 | |
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137 | Processor Initialization |
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138 | ------------------------ |
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139 | |
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140 | TBD |
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