source: rtems-docs/cpu-supplement/superh.rst @ 67195aa

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[489740f]1.. comment SPDX-License-Identifier: CC-BY-SA-4.0
2
[f233256]3.. COMMENT: COPYRIGHT (c) 1988-2002.
4.. COMMENT: On-Line Applications Research Corporation (OAR).
5.. COMMENT: All rights reserved.
6
[d755cbd]7SuperH Specific Information
[6916004]8***************************
[d755cbd]9
[f233256]10This chapter discusses the SuperH architecture dependencies in this port of
11RTEMS.  The SuperH family has a wide variety of implementations by a wide range
12of vendors.  Consequently, there are many, many CPU models within it.
[d755cbd]13
14**Architecture Documents**
15
[f233256]16For information on the SuperH architecture, refer to the following documents
17available from VENDOR (http://www.XXX.com/):
[d755cbd]18
19- *SuperH Family Reference, VENDOR, PART NUMBER*.
20
21CPU Model Dependent Features
22============================
23
[f233256]24This chapter presents the set of features which vary across SuperH
25implementations and are of importance to RTEMS.  The set of CPU model feature
26macros are defined in the file ``cpukit/score/cpu/sh/sh.h`` based upon the
27particular CPU model specified on the compilation command line.
[d755cbd]28
29Another Optional Feature
30------------------------
31
32The macro XXX
33
34Calling Conventions
35===================
36
37Calling Mechanism
38-----------------
39
[f233256]40All RTEMS directives are invoked using a ``XXX`` instruction and return to the
41user application via the ``XXX`` instruction.
[d755cbd]42
43Register Usage
44--------------
45
46The SH1 has 16 general registers (r0..r15).
47
48- r0..r3 used as general volatile registers
49
[f233256]50- r4..r7 used to pass up to 4 arguments to functions, arguments above 4 are
[d755cbd]51  passed via the stack)
52
[f233256]53- r8..13 caller saved registers (i.e. push them to the stack if you need them
54  inside of a function)
[d755cbd]55
56- r14 frame pointer
57
58- r15 stack pointer
59
60Parameter Passing
61-----------------
62
63XXX
64
65Memory Model
66============
67
68Flat Memory Model
69-----------------
70
[f233256]71The SuperH family supports a flat 32-bit address space with addresses ranging
72from 0x00000000 to 0xFFFFFFFF (4 gigabytes).  Each address is represented by a
7332-bit value and is byte addressable.  The address may be used to reference a
74single byte, word (2-bytes), or long word (4 bytes).  Memory accesses within
75this address space are performed in big endian fashion by the processors in
76this family.
[d755cbd]77
[f233256]78Some of the SuperH family members support virtual memory and segmentation.
79RTEMS does not support virtual memory or segmentation on any of the SuperH
80family members.  It is the responsibility of the BSP to initialize the mapping
81for a flat memory model.
[d755cbd]82
83Interrupt Processing
84====================
85
[f233256]86Although RTEMS hides many of the processor dependent details of interrupt
87processing, it is important to understand how the RTEMS interrupt manager is
88mapped onto the processor's unique architecture. Discussed in this chapter are
89the MIPS's interrupt response and control mechanisms as they pertain to RTEMS.
[d755cbd]90
91Vectoring of an Interrupt Handler
92---------------------------------
93
[f233256]94Upon receipt of an interrupt the XXX family members with separate interrupt
95stacks automatically perform the following actions:
[d755cbd]96
97- TBD
98
[f233256]99A nested interrupt is processed similarly by these CPU models with the
100exception that only a single ISF is placed on the interrupt stack and the
101current stack need not be switched.
[d755cbd]102
103Interrupt Levels
104----------------
105
106TBD
107
108Default Fatal Error Processing
109==============================
110
111The default fatal error handler for this architecture disables processor
[f233256]112interrupts, places the error code in *XXX*, and executes a ``XXX`` instruction
113to simulate a halt processor instruction.
[d755cbd]114
115Symmetric Multiprocessing
116=========================
117
118SMP is not supported.
119
120Thread-Local Storage
121====================
122
123Thread-local storage is not implemented.
124
125Board Support Packages
126======================
127
128System Reset
129------------
130
131An RTEMS based application is initiated or
132re-initiated when the processor is reset.  When the
133processor is reset, it performs the following actions:
134
135- TBD
136
137Processor Initialization
138------------------------
139
140TBD
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