[e52906b] | 1 | .. SPDX-License-Identifier: CC-BY-SA-4.0 |
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[489740f] | 2 | |
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[4886d60] | 3 | .. Copyright (C) 1988, 2002 On-Line Applications Research Corporation (OAR) |
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[f233256] | 4 | |
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[d755cbd] | 5 | SuperH Specific Information |
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[6916004] | 6 | *************************** |
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[d755cbd] | 7 | |
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[f233256] | 8 | This chapter discusses the SuperH architecture dependencies in this port of |
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| 9 | RTEMS. The SuperH family has a wide variety of implementations by a wide range |
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| 10 | of vendors. Consequently, there are many, many CPU models within it. |
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[d755cbd] | 11 | |
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| 12 | **Architecture Documents** |
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| 13 | |
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[f233256] | 14 | For information on the SuperH architecture, refer to the following documents |
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| 15 | available from VENDOR (http://www.XXX.com/): |
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[d755cbd] | 16 | |
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| 17 | - *SuperH Family Reference, VENDOR, PART NUMBER*. |
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| 18 | |
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| 19 | CPU Model Dependent Features |
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| 20 | ============================ |
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| 21 | |
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[f233256] | 22 | This chapter presents the set of features which vary across SuperH |
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| 23 | implementations and are of importance to RTEMS. The set of CPU model feature |
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| 24 | macros are defined in the file ``cpukit/score/cpu/sh/sh.h`` based upon the |
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| 25 | particular CPU model specified on the compilation command line. |
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[d755cbd] | 26 | |
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| 27 | Another Optional Feature |
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| 28 | ------------------------ |
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| 29 | |
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| 30 | The macro XXX |
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| 31 | |
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| 32 | Calling Conventions |
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| 33 | =================== |
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| 34 | |
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| 35 | Calling Mechanism |
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| 36 | ----------------- |
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| 37 | |
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[f233256] | 38 | All RTEMS directives are invoked using a ``XXX`` instruction and return to the |
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| 39 | user application via the ``XXX`` instruction. |
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[d755cbd] | 40 | |
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| 41 | Register Usage |
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| 42 | -------------- |
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| 43 | |
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| 44 | The SH1 has 16 general registers (r0..r15). |
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| 45 | |
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| 46 | - r0..r3 used as general volatile registers |
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| 47 | |
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[f233256] | 48 | - r4..r7 used to pass up to 4 arguments to functions, arguments above 4 are |
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[d755cbd] | 49 | passed via the stack) |
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| 50 | |
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[f233256] | 51 | - r8..13 caller saved registers (i.e. push them to the stack if you need them |
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| 52 | inside of a function) |
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[d755cbd] | 53 | |
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| 54 | - r14 frame pointer |
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| 55 | |
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| 56 | - r15 stack pointer |
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| 57 | |
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| 58 | Parameter Passing |
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| 59 | ----------------- |
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| 60 | |
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| 61 | XXX |
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| 62 | |
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| 63 | Memory Model |
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| 64 | ============ |
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| 65 | |
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| 66 | Flat Memory Model |
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| 67 | ----------------- |
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| 68 | |
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[f233256] | 69 | The SuperH family supports a flat 32-bit address space with addresses ranging |
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| 70 | from 0x00000000 to 0xFFFFFFFF (4 gigabytes). Each address is represented by a |
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| 71 | 32-bit value and is byte addressable. The address may be used to reference a |
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| 72 | single byte, word (2-bytes), or long word (4 bytes). Memory accesses within |
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| 73 | this address space are performed in big endian fashion by the processors in |
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| 74 | this family. |
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[d755cbd] | 75 | |
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[f233256] | 76 | Some of the SuperH family members support virtual memory and segmentation. |
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| 77 | RTEMS does not support virtual memory or segmentation on any of the SuperH |
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| 78 | family members. It is the responsibility of the BSP to initialize the mapping |
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| 79 | for a flat memory model. |
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[d755cbd] | 80 | |
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| 81 | Interrupt Processing |
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| 82 | ==================== |
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| 83 | |
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[f233256] | 84 | Although RTEMS hides many of the processor dependent details of interrupt |
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| 85 | processing, it is important to understand how the RTEMS interrupt manager is |
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| 86 | mapped onto the processor's unique architecture. Discussed in this chapter are |
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| 87 | the MIPS's interrupt response and control mechanisms as they pertain to RTEMS. |
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[d755cbd] | 88 | |
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| 89 | Vectoring of an Interrupt Handler |
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| 90 | --------------------------------- |
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| 91 | |
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[f233256] | 92 | Upon receipt of an interrupt the XXX family members with separate interrupt |
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| 93 | stacks automatically perform the following actions: |
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[d755cbd] | 94 | |
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| 95 | - TBD |
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| 96 | |
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[f233256] | 97 | A nested interrupt is processed similarly by these CPU models with the |
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| 98 | exception that only a single ISF is placed on the interrupt stack and the |
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| 99 | current stack need not be switched. |
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[d755cbd] | 100 | |
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| 101 | Interrupt Levels |
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| 102 | ---------------- |
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| 103 | |
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| 104 | TBD |
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| 105 | |
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| 106 | Default Fatal Error Processing |
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| 107 | ============================== |
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| 108 | |
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| 109 | The default fatal error handler for this architecture disables processor |
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[f233256] | 110 | interrupts, places the error code in *XXX*, and executes a ``XXX`` instruction |
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| 111 | to simulate a halt processor instruction. |
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[d755cbd] | 112 | |
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| 113 | Symmetric Multiprocessing |
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| 114 | ========================= |
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| 115 | |
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| 116 | SMP is not supported. |
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| 117 | |
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| 118 | Thread-Local Storage |
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| 119 | ==================== |
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| 120 | |
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| 121 | Thread-local storage is not implemented. |
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| 122 | |
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| 123 | Board Support Packages |
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| 124 | ====================== |
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| 125 | |
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| 126 | System Reset |
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| 127 | ------------ |
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| 128 | |
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| 129 | An RTEMS based application is initiated or |
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| 130 | re-initiated when the processor is reset. When the |
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| 131 | processor is reset, it performs the following actions: |
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| 132 | |
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| 133 | - TBD |
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| 134 | |
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| 135 | Processor Initialization |
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| 136 | ------------------------ |
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| 137 | |
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| 138 | TBD |
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