[489740f] | 1 | .. comment SPDX-License-Identifier: CC-BY-SA-4.0 |
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| 2 | |
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[f233256] | 3 | .. COMMENT: COPYRIGHT (c) 1988-2002. |
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| 4 | .. COMMENT: On-Line Applications Research Corporation (OAR). |
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| 5 | .. COMMENT: All rights reserved. |
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| 6 | |
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[d755cbd] | 7 | SPARC-64 Specific Information |
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[6916004] | 8 | ***************************** |
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[d755cbd] | 9 | |
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| 10 | This document discusses the SPARC Version 9 (aka SPARC-64, SPARC64 or SPARC V9) |
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| 11 | architecture dependencies in this port of RTEMS. |
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| 12 | |
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| 13 | The SPARC V9 architecture leaves a lot of undefined implemenation dependencies |
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| 14 | which are defined by the processor models. Consult the specific CPU model |
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| 15 | section in this document for additional documents covering the implementation |
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| 16 | dependent architectural features. |
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| 17 | |
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| 18 | **sun4u Specific Information** |
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| 19 | |
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| 20 | sun4u is the subset of the SPARC V9 implementations comprising the UltraSPARC I |
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| 21 | through UltraSPARC IV processors. |
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| 22 | |
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| 23 | The following documents were used in developing the SPARC-64 sun4u port: |
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| 24 | |
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[d389819] | 25 | - UltraSPARC User's Manual |
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[d755cbd] | 26 | (http://www.sun.com/microelectronics/manuals/ultrasparc/802-7220-02.pdf) |
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| 27 | |
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[f233256] | 28 | - UltraSPARC IIIi Processor (http://datasheets.chipdb.org/Sun/UltraSparc-IIIi.pdf) |
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[d755cbd] | 29 | |
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| 30 | **sun4v Specific Information** |
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| 31 | |
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[f233256] | 32 | sun4v is the subset of the SPARC V9 implementations comprising the UltraSPARC |
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| 33 | T1 or T2 processors. |
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[d755cbd] | 34 | |
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| 35 | The following documents were used in developing the SPARC-64 sun4v port: |
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| 36 | |
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| 37 | - UltraSPARC Architecture 2005 Specification |
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| 38 | (http://opensparc-t1.sunsource.net/specs/UA2005-current-draft-P-EXT.pdf) |
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| 39 | |
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| 40 | - UltraSPARC T1 supplement to UltraSPARC Architecture 2005 Specification |
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| 41 | (http://opensparc-t1.sunsource.net/specs/UST1-UASuppl-current-draft-P-EXT.pdf) |
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| 42 | |
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[f233256] | 43 | The defining feature that separates the sun4v architecture from its predecessor |
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| 44 | is the existence of a super-privileged hypervisor that is responsible for |
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| 45 | providing virtualized execution environments. The impact of the hypervisor on |
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| 46 | the real-time guarantees available with sun4v has not yet been determined. |
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[d755cbd] | 47 | |
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| 48 | CPU Model Dependent Features |
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| 49 | ============================ |
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| 50 | |
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| 51 | CPU Model Feature Flags |
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| 52 | ----------------------- |
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| 53 | |
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[f233256] | 54 | This section presents the set of features which vary across SPARC-64 |
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| 55 | implementations and are of importance to RTEMS. The set of CPU model feature |
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| 56 | macros are defined in the file cpukit/score/cpu/sparc64/sparc64.h based upon |
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| 57 | the particular CPU model defined on the compilation command line. |
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[d755cbd] | 58 | |
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| 59 | CPU Model Name |
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| 60 | ~~~~~~~~~~~~~~ |
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| 61 | |
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[f233256] | 62 | The macro CPU MODEL NAME is a string which designates the name of this CPU |
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| 63 | model. For example, for the UltraSPARC T1 SPARC V9 model, this macro is set to |
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| 64 | the string "sun4v". |
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[d755cbd] | 65 | |
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| 66 | Floating Point Unit |
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| 67 | ~~~~~~~~~~~~~~~~~~~ |
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| 68 | |
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[f233256] | 69 | The macro SPARC_HAS_FPU is set to 1 to indicate that this CPU model has a |
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| 70 | hardware floating point unit and 0 otherwise. |
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[d755cbd] | 71 | |
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| 72 | Number of Register Windows |
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| 73 | ~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 74 | |
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[f233256] | 75 | The macro SPARC_NUMBER_OF_REGISTER_WINDOWS is set to indicate the number of |
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| 76 | register window sets implemented by this CPU model. The SPARC architecture |
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| 77 | allows for a maximum of thirty-two register window sets although most |
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| 78 | implementations only include eight. |
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[d755cbd] | 79 | |
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| 80 | CPU Model Implementation Notes |
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| 81 | ------------------------------ |
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| 82 | |
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[f233256] | 83 | This section describes the implemenation dependencies of the CPU Models sun4u |
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| 84 | and sun4v of the SPARC V9 architecture. |
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[d755cbd] | 85 | |
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| 86 | sun4u Notes |
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| 87 | ~~~~~~~~~~~ |
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| 88 | |
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| 89 | XXX |
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| 90 | |
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| 91 | sun4v Notes |
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| 92 | ----------- |
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| 93 | |
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| 94 | XXX |
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| 95 | |
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| 96 | Calling Conventions |
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| 97 | =================== |
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| 98 | |
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[f233256] | 99 | Each high-level language compiler generates subroutine entry and exit code |
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| 100 | based upon a set of rules known as the compiler's calling convention. These |
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| 101 | rules address the following issues: |
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[d755cbd] | 102 | |
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| 103 | - register preservation and usage |
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| 104 | |
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| 105 | - parameter passing |
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| 106 | |
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| 107 | - call and return mechanism |
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| 108 | |
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[d389819] | 109 | A compiler's calling convention is of importance when |
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[d755cbd] | 110 | interfacing to subroutines written in another language either |
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| 111 | assembly or high-level. Even when the high-level language and |
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| 112 | target processor are the same, different compilers may use |
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| 113 | different calling conventions. As a result, calling conventions |
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| 114 | are both processor and compiler dependent. |
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| 115 | |
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[f233256] | 116 | The following document also provides some conventions on the global register |
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| 117 | usage in SPARC V9: http://developers.sun.com/solaris/articles/sparcv9abi.html |
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[d755cbd] | 118 | |
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| 119 | Programming Model |
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| 120 | ----------------- |
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| 121 | |
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[f233256] | 122 | This section discusses the programming model for the SPARC architecture. |
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[d755cbd] | 123 | |
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| 124 | Non-Floating Point Registers |
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| 125 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 126 | |
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[f233256] | 127 | The SPARC architecture defines thirty-two non-floating point registers directly |
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| 128 | visible to the programmer. These are divided into four sets: |
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[d755cbd] | 129 | |
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| 130 | - input registers |
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| 131 | |
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| 132 | - local registers |
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| 133 | |
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| 134 | - output registers |
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| 135 | |
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| 136 | - global registers |
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| 137 | |
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[f233256] | 138 | Each register is referred to by either two or three names in the SPARC |
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| 139 | reference manuals. First, the registers are referred to as r0 through r31 or |
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| 140 | with the alternate notation r[0] through r[31]. Second, each register is a |
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| 141 | member of one of the four sets listed above. Finally, some registers have an |
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| 142 | architecturally defined role in the programming model which provides an |
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| 143 | alternate name. The following table describes the mapping between the 32 |
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| 144 | registers and the register sets: |
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[d755cbd] | 145 | |
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[0c97890] | 146 | ================ ================ =================== |
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| 147 | Register Number Register Names Description |
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| 148 | ================ ================ =================== |
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| 149 | 0 - 7 g0 - g7 Global Registers |
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| 150 | 8 - 15 o0 - o7 Output Registers |
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| 151 | 16 - 23 l0 - l7 Local Registers |
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| 152 | 24 - 31 i0 - i7 Input Registers |
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| 153 | ================ ================ =================== |
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[d755cbd] | 154 | |
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[f233256] | 155 | As mentioned above, some of the registers serve defined roles in the |
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| 156 | programming model. The following table describes the role of each of these |
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| 157 | registers: |
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[d755cbd] | 158 | |
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[0c97890] | 159 | ============== ================ ================================== |
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| 160 | Register Name Alternate Name Description |
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| 161 | ============== ================ ================================== |
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| 162 | g0 na reads return 0, writes are ignored |
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| 163 | o6 sp stack pointer |
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| 164 | i6 fp frame pointer |
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| 165 | i7 na return address |
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| 166 | ============== ================ ================================== |
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[d755cbd] | 167 | |
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| 168 | Floating Point Registers |
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| 169 | ~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 170 | |
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[f233256] | 171 | The SPARC V9 architecture includes sixty-four, thirty-two bit registers. These |
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| 172 | registers may be viewed as follows: |
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[d755cbd] | 173 | |
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[f233256] | 174 | - 32 32-bit single precision floating point or integer registers (f0, f1, |
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| 175 | ... f31) |
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[d755cbd] | 176 | |
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[f233256] | 177 | - 32 64-bit double precision floating point registers (f0, f2, f4, ... f62) |
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[d755cbd] | 178 | |
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[f233256] | 179 | - 16 128-bit extended precision floating point registers (f0, f4, f8, ... f60) |
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[d755cbd] | 180 | |
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[f233256] | 181 | The floating point state register (fsr) specifies the behavior of the floating |
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| 182 | point unit for rounding, contains its condition codes, version specification, |
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| 183 | and trap information. |
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[d755cbd] | 184 | |
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| 185 | Special Registers |
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| 186 | ~~~~~~~~~~~~~~~~~ |
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| 187 | |
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| 188 | The SPARC architecture includes a number of special registers: |
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| 189 | |
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| 190 | *``Ancillary State Registers (ASRs)``* |
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[f233256] | 191 | The ancillary state registers (ASRs) are optional state registers that may |
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| 192 | be privileged or nonprivileged. ASRs 16-31 are implementation- |
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| 193 | dependent. The SPARC V9 ASRs include: y, ccr, asi, tick, pc, fprs. The |
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| 194 | sun4u ASRs include: pcr, pic, dcr, gsr, softint set, softint clr, softint, |
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| 195 | and tick cmpr. The sun4v ASRs include: pcr, pic, gsr, soft- int set, |
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| 196 | softint clr, softint, tick cmpr, stick, and stick cmpr. |
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[d755cbd] | 197 | |
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| 198 | *``Processor State Register (pstate)``* |
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| 199 | The privileged pstate register contains control fields for the proces- |
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[d389819] | 200 | sor's current state. Its flag fields include the interrupt enable, privi- |
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[d755cbd] | 201 | leged mode, and enable FPU. |
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| 202 | |
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| 203 | *``Processor Interrupt Level (pil)``* |
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| 204 | The PIL specifies the interrupt level above which interrupts will be |
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| 205 | accepted. |
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| 206 | |
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| 207 | *``Trap Registers``* |
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[f233256] | 208 | The trap handling mechanism of the SPARC V9 includes a number of registers, |
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| 209 | including: trap program counter (tpc), trap next pc (tnpc), trap state |
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| 210 | (tstate), trap type (tt), trap base address (tba), and trap level (tl). |
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[d755cbd] | 211 | |
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| 212 | *``Alternate Globals``* |
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[f233256] | 213 | The AG bit of the pstate register provides access to an alternate set of |
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| 214 | global registers. On sun4v, the AG bit is replaced by the global level (gl) |
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| 215 | register, providing access to at least two and at most eight alternate sets |
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| 216 | of globals. |
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[d755cbd] | 217 | |
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| 218 | *``Register Window registers``* |
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[f233256] | 219 | A number of registers assist in register window management. These include |
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| 220 | the current window pointer (cwp), savable windows (cansave), restorable |
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| 221 | windows (canrestore), clean windows (clean- win), other windows (otherwin), |
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| 222 | and window state (wstate). |
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[d755cbd] | 223 | |
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| 224 | Register Windows |
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| 225 | ---------------- |
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| 226 | |
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[f233256] | 227 | The SPARC architecture includes the concept of register windows. An overly |
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| 228 | simplistic way to think of these windows is to imagine them as being an |
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| 229 | infinite supply of "fresh" register sets available for each subroutine to use. |
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| 230 | In reality, they are much more complicated. |
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| 231 | |
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| 232 | The save instruction is used to obtain a new register window. This instruction |
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| 233 | increments the current window pointer, thus providing a new set of registers |
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| 234 | for use. This register set includes eight fresh local registers for use |
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| 235 | exclusively by this subroutine. When done with a register set, the restore |
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| 236 | instruction decrements the current window pointer and the previous register set |
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| 237 | is once again available. |
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| 238 | |
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| 239 | The two primary issues complicating the use of register windows are that (1) |
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| 240 | the set of register windows is finite, and (2) some registers are shared |
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| 241 | between adjacent registers windows. |
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| 242 | |
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| 243 | Because the set of register windows is finite, it is possible to execute enough |
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| 244 | save instructions without corresponding restore's to consume all of the |
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| 245 | register windows. This is easily accomplished in a high level language because |
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| 246 | each subroutine typically performs a save instruction upon entry. Thus having |
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| 247 | a subroutine call depth greater than the number of register windows will result |
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| 248 | in a window overflow condition. The window overflow condition generates a trap |
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| 249 | which must be handled in software. The window overflow trap handler is |
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| 250 | responsible for saving the contents of the oldest register window on the |
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| 251 | program stack. |
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| 252 | |
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| 253 | Similarly, the subroutines will eventually complete and begin to perform |
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| 254 | restore's. If the restore results in the need for a register window which has |
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| 255 | previously been written to memory as part of an overflow, then a window |
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| 256 | underflow condition results. Just like the window overflow, the window |
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| 257 | underflow condition must be handled in software by a trap handler. The window |
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| 258 | underflow trap handler is responsible for reloading the contents of the |
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| 259 | register window requested by the restore instruction from the program stack. |
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| 260 | |
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| 261 | The cansave, canrestore, otherwin, and cwp are used in conjunction to manage |
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| 262 | the finite set of register windows and detect the window overflow and underflow |
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| 263 | conditions. The first three of these registers must satisfy the invariant |
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| 264 | cansave + canrestore + otherwin = nwindow - 2, where nwindow is the number of |
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| 265 | register windows. The cwp contains the index of the register window currently |
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| 266 | in use. RTEMS does not use the cleanwin and otherwin registers. |
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| 267 | |
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| 268 | The save instruction increments the cwp modulo the number of register windows, |
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| 269 | and if cansave is 0 then it also generates a window overflow. Similarly, the |
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| 270 | restore instruction decrements the cwp modulo the number of register windows, |
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| 271 | and if canrestore is 0 then it also generates a window underflow. |
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| 272 | |
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| 273 | Unlike with the SPARC model, the SPARC-64 port does not assume that a register |
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| 274 | window is available for a trap. The window overflow and underflow conditions |
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| 275 | are not detected without hardware generating the trap. (These conditions can be |
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| 276 | detected by reading the register window registers and doing some simple |
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| 277 | arithmetic.) |
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| 278 | |
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| 279 | The window overflow and window underflow trap handlers are a critical part of |
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| 280 | the run-time environment for a SPARC application. The SPARC architectural |
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| 281 | specification allows for the number of register windows to be any power of two |
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| 282 | less than or equal to 32. The most common choice for SPARC implementations |
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| 283 | appears to be 8 register windows. This results in the cwp ranging in value |
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| 284 | from 0 to 7 on most implementations. |
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| 285 | |
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| 286 | The second complicating factor is the sharing of registers between adjacent |
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| 287 | register windows. While each register window has its own set of local |
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| 288 | registers, the input and output registers are shared between adjacent windows. |
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| 289 | The output registers for register window N are the same as the input registers |
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| 290 | for register window ((N + 1) modulo RW) where RW is the number of register |
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| 291 | windows. An alternative way to think of this is to remember how parameters are |
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| 292 | passed to a subroutine on the SPARC. The caller loads values into what are its |
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| 293 | output registers. Then after the callee executes a save instruction, those |
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| 294 | parameters are available in its input registers. This is a very efficient way |
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| 295 | to pass parameters as no data is actually moved by the save or restore |
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| 296 | instructions. |
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[d755cbd] | 297 | |
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| 298 | Call and Return Mechanism |
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| 299 | ------------------------- |
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| 300 | |
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[f233256] | 301 | The SPARC architecture supports a simple yet effective call and return |
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| 302 | mechanism. A subroutine is invoked via the call (call) instruction. This |
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| 303 | instruction places the return address in the caller's output register 7 (o7). |
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| 304 | After the callee executes a save instruction, this value is available in input |
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| 305 | register 7 (i7) until the corresponding restore instruction is executed. |
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| 306 | |
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| 307 | The callee returns to the caller via a jmp to the return address. There is a |
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| 308 | delay slot following this instruction which is commonly used to execute a |
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| 309 | restore instruction - if a register window was allocated by this subroutine. |
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| 310 | |
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| 311 | It is important to note that the SPARC subroutine call and return mechanism |
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| 312 | does not automatically save and restore any registers. This is accomplished |
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| 313 | via the save and restore instructions which manage the set of registers |
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| 314 | windows. This allows for the compiler to generate leaf-optimized functions |
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[d389819] | 315 | that utilize the caller's output registers without using save and restore. |
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[d755cbd] | 316 | |
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| 317 | Calling Mechanism |
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| 318 | ----------------- |
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| 319 | |
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[f233256] | 320 | All RTEMS directives are invoked using the regular SPARC calling convention via |
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| 321 | the call instruction. |
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[d755cbd] | 322 | |
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| 323 | Register Usage |
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| 324 | -------------- |
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| 325 | |
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[f233256] | 326 | As discussed above, the call instruction does not automatically save any |
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| 327 | registers. The save and restore instructions are used to allocate and |
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| 328 | deallocate register windows. When a register window is allocated, the new set |
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| 329 | of local registers are available for the exclusive use of the subroutine which |
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| 330 | allocated this register set. |
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[d755cbd] | 331 | |
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| 332 | Parameter Passing |
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| 333 | ----------------- |
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| 334 | |
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[f233256] | 335 | RTEMS assumes that arguments are placed in the caller's output registers with |
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| 336 | the first argument in output register 0 (o0), the second argument in output |
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| 337 | register 1 (o1), and so forth. Until the callee executes a save instruction, |
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| 338 | the parameters are still visible in the output registers. After the callee |
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| 339 | executes a save instruction, the parameters are visible in the corresponding |
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| 340 | input registers. The following pseudo-code illustrates the typical sequence |
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| 341 | used to call a RTEMS directive with three (3) arguments: |
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| 342 | |
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| 343 | .. code-block:: c |
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[d755cbd] | 344 | |
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| 345 | load third argument into o2 |
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| 346 | load second argument into o1 |
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| 347 | load first argument into o0 |
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| 348 | invoke directive |
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| 349 | |
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| 350 | User-Provided Routines |
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| 351 | ---------------------- |
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| 352 | |
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[f233256] | 353 | All user-provided routines invoked by RTEMS, such as user extensions, device |
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| 354 | drivers, and MPCI routines, must also adhere to these calling conventions. |
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[d755cbd] | 355 | |
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| 356 | Memory Model |
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| 357 | ============ |
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| 358 | |
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[f233256] | 359 | A processor may support any combination of memory models ranging from pure |
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| 360 | physical addressing to complex demand paged virtual memory systems. RTEMS |
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| 361 | supports a flat memory model which ranges contiguously over the processor's |
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| 362 | allowable address space. RTEMS does not support segmentation or virtual memory |
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| 363 | of any kind. The appropriate memory model for RTEMS provided by the targeted |
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| 364 | processor and related characteristics of that model are described in this |
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| 365 | chapter. |
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[d755cbd] | 366 | |
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| 367 | Flat Memory Model |
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| 368 | ----------------- |
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| 369 | |
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[f233256] | 370 | The SPARC-64 architecture supports a flat 64-bit address space with addresses |
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| 371 | ranging from 0x0000000000000000 to 0xFFFFFFFFFFFFFFFF. Each address is |
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| 372 | represented by a 64-bit value (and an 8-bit address space identifider or ASI) |
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| 373 | and is byte addressable. The address may be used to reference a single byte, |
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| 374 | half-word (2-bytes), word (4 bytes), doubleword (8 bytes), or quad-word (16 |
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| 375 | bytes). Memory accesses within this address space are performed in big endian |
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| 376 | fashion by the SPARC. Memory accesses which are not properly aligned generate a |
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| 377 | "memory address not aligned" trap (type number 0x34). The following table lists |
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| 378 | the alignment requirements for a variety of data accesses: |
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[d755cbd] | 379 | |
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[0c97890] | 380 | ============== ====================== |
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| 381 | Data Type Alignment Requirement |
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| 382 | ============== ====================== |
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| 383 | byte 1 |
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| 384 | half-word 2 |
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| 385 | word 4 |
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| 386 | doubleword 8 |
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| 387 | quadword 16 |
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| 388 | ============== ====================== |
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[d755cbd] | 389 | |
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[f233256] | 390 | RTEMS currently does not support any SPARC Memory Management Units, therefore, |
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| 391 | virtual memory or segmentation systems involving the SPARC are not supported. |
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[d755cbd] | 392 | |
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| 393 | Interrupt Processing |
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| 394 | ==================== |
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| 395 | |
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[f233256] | 396 | RTEMS and associated documentation uses the terms interrupt and vector. In the |
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| 397 | SPARC architecture, these terms correspond to traps and trap type, |
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| 398 | respectively. The terms will be used interchangeably in this manual. Note that |
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| 399 | in the SPARC manuals, interrupts are a subset of the traps that are delivered |
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| 400 | to software interrupt handlers. |
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[d755cbd] | 401 | |
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| 402 | Synchronous Versus Asynchronous Traps |
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| 403 | ------------------------------------- |
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| 404 | |
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[f233256] | 405 | The SPARC architecture includes two classes of traps: synchronous (precise) and |
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| 406 | asynchronous (deferred). Asynchronous traps occur when an external event |
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| 407 | interrupts the processor. These traps are not associated with any instruction |
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| 408 | executed by the processor and logically occur between instructions. The |
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| 409 | instruction currently in the execute stage of the processor is allowed to |
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| 410 | complete although subsequent instructions are annulled. The return address |
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| 411 | reported by the processor for asynchronous traps is the pair of instructions |
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| 412 | following the current instruction. |
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| 413 | |
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| 414 | Synchronous traps are caused by the actions of an instruction. The trap |
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| 415 | stimulus in this case either occurs internally to the processor or is from an |
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| 416 | external signal that was provoked by the instruction. These traps are taken |
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| 417 | immediately and the instruction that caused the trap is aborted before any |
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| 418 | state changes occur in the processor itself. The return address reported by |
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| 419 | the processor for synchronous traps is the instruction which caused the trap |
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| 420 | and the following instruction. |
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[d755cbd] | 421 | |
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| 422 | Vectoring of Interrupt Handler |
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| 423 | ------------------------------ |
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| 424 | |
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[f233256] | 425 | Upon receipt of an interrupt the SPARC automatically performs the following |
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| 426 | actions: |
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[d755cbd] | 427 | |
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[f233256] | 428 | - The trap level is set. This provides access to a fresh set of privileged |
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| 429 | trap-state registers used to save the current state, in effect, pushing a |
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| 430 | frame on the trap stack. TL <- TL + 1 |
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[d755cbd] | 431 | |
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| 432 | - Existing state is preserved |
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| 433 | - TSTATE[TL].CCR <- CCR |
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| 434 | - TSTATE[TL].ASI <- ASI |
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| 435 | - TSTATE[TL].PSTATE <- PSTATE |
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| 436 | - TSTATE[TL].CWP <- CWP |
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| 437 | - TPC[TL] <- PC |
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| 438 | - TNPC[TL] <- nPC |
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| 439 | |
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| 440 | - The trap type is preserved. TT[TL] <- the trap type |
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| 441 | |
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| 442 | - The PSTATE register is updated to a predefined state |
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| 443 | - PSTATE.MM is unchanged |
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| 444 | - PSTATE.RED <- 0 |
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| 445 | - PSTATE.PEF <- 1 if FPU is present, 0 otherwise |
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| 446 | - PSTATE.AM <- 0 (address masking is turned off) |
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| 447 | - PSTATE.PRIV <- 1 (the processor enters privileged mode) |
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| 448 | - PSTATE.IE <- 0 (interrupts are disabled) |
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| 449 | - PSTATE.AG <- 1 (global regs are replaced with alternate globals) |
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| 450 | - PSTATE.CLE <- PSTATE.TLE (set endian mode for traps) |
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| 451 | |
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| 452 | - For a register-window trap only, CWP is set to point to the register |
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| 453 | window that must be accessed by the trap-handler software, that is: |
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| 454 | |
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| 455 | - If TT[TL] = 0x24 (a clean window trap), then CWP <- CWP + 1. |
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| 456 | - If (0x80 <= TT[TL] <= 0xBF) (window spill trap), then CWP <- CWP + |
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| 457 | CANSAVE + 2. |
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| 458 | - If (0xC0 <= TT[TL] <= 0xFF) (window fill trap), then CWP <- CWP1. |
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| 459 | - For non-register-window traps, CWP is not changed. |
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| 460 | |
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| 461 | - Control is transferred into the trap table: |
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| 462 | |
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| 463 | - PC <- TBA<63:15> (TL>0) TT[TL] 0 0000 |
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| 464 | - nPC <- TBA<63:15> (TL>0) TT[TL] 0 0100 |
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| 465 | - where (TL>0) is 0 if TL = 0, and 1 if TL > 0. |
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| 466 | |
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| 467 | In order to safely invoke a subroutine during trap handling, traps must be |
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[f233256] | 468 | enabled to allow for the possibility of register window overflow and underflow |
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| 469 | traps. |
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[d755cbd] | 470 | |
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[f233256] | 471 | If the interrupt handler was installed as an RTEMS interrupt handler, then upon |
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| 472 | receipt of the interrupt, the processor passes control to the RTEMS interrupt |
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| 473 | handler which performs the following actions: |
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[d755cbd] | 474 | |
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[d389819] | 475 | - saves the state of the interrupted task on it's stack, |
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[d755cbd] | 476 | |
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| 477 | - switches the processor to trap level 0, |
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| 478 | |
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[f233256] | 479 | - if this is the outermost (i.e. non-nested) interrupt, then the RTEMS |
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| 480 | interrupt handler switches from the current stack to the interrupt stack, |
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[d755cbd] | 481 | |
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| 482 | - enables traps, |
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| 483 | |
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| 484 | - invokes the vectors to a user interrupt service routine (ISR). |
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| 485 | |
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[f233256] | 486 | Asynchronous interrupts are ignored while traps are disabled. Synchronous |
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| 487 | traps which occur while traps are disabled may result in the CPU being forced |
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| 488 | into an error mode. |
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[d755cbd] | 489 | |
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[f233256] | 490 | A nested interrupt is processed similarly with the exception that the current |
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| 491 | stack need not be switched to the interrupt stack. |
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[d755cbd] | 492 | |
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| 493 | Traps and Register Windows |
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| 494 | -------------------------- |
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| 495 | |
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| 496 | XXX |
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| 497 | |
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| 498 | Interrupt Levels |
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| 499 | ---------------- |
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| 500 | |
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[f233256] | 501 | Sixteen levels (0-15) of interrupt priorities are supported by the SPARC |
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| 502 | architecture with level fifteen (15) being the highest priority. Level |
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| 503 | zero (0) indicates that interrupts are fully enabled. Interrupt requests for |
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| 504 | interrupts with priorities less than or equal to the current interrupt mask |
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[d755cbd] | 505 | level are ignored. |
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| 506 | |
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[f233256] | 507 | Although RTEMS supports 256 interrupt levels, the SPARC only supports sixteen. |
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| 508 | RTEMS interrupt levels 0 through 15 directly correspond to SPARC processor |
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| 509 | interrupt levels. All other RTEMS interrupt levels are undefined and their |
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| 510 | behavior is unpredictable. |
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[d755cbd] | 511 | |
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| 512 | Disabling of Interrupts by RTEMS |
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| 513 | -------------------------------- |
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| 514 | |
---|
| 515 | XXX |
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| 516 | |
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| 517 | Interrupt Stack |
---|
| 518 | --------------- |
---|
| 519 | |
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[f233256] | 520 | The SPARC architecture does not provide for a dedicated interrupt stack. Thus |
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| 521 | by default, trap handlers would execute on the stack of the RTEMS task which |
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| 522 | they interrupted. This artificially inflates the stack requirements for each |
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| 523 | task since EVERY task stack would have to include enough space to account for |
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| 524 | the worst case interrupt stack requirements in addition to it's own worst case |
---|
| 525 | usage. RTEMS addresses this problem on the SPARC by providing a dedicated |
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| 526 | interrupt stack managed by software. |
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[d755cbd] | 527 | |
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[f233256] | 528 | During system initialization, RTEMS allocates the interrupt stack from the |
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| 529 | Workspace Area. The amount of memory allocated for the interrupt stack is |
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| 530 | determined by the interrupt_stack_size field in the CPU Configuration Table. |
---|
| 531 | As part of processing a non-nested interrupt, RTEMS will switch to the |
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| 532 | interrupt stack before invoking the installed handler. |
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[d755cbd] | 533 | |
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| 534 | Default Fatal Error Processing |
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| 535 | ============================== |
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| 536 | |
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[f233256] | 537 | Upon detection of a fatal error by either the application or RTEMS the fatal |
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| 538 | error manager is invoked. The fatal error manager will invoke the |
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| 539 | user-supplied fatal error handlers. If no user-supplied handlers are |
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| 540 | configured, the RTEMS provided default fatal error handler is invoked. If the |
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| 541 | user-supplied fatal error handlers return to the executive the default fatal |
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| 542 | error handler is then invoked. This chapter describes the precise operations |
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| 543 | of the default fatal error handler. |
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[d755cbd] | 544 | |
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| 545 | Default Fatal Error Handler Operations |
---|
| 546 | -------------------------------------- |
---|
| 547 | |
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[f233256] | 548 | The default fatal error handler which is invoked by the fatal_error_occurred |
---|
| 549 | directive when there is no user handler configured or the user handler returns |
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| 550 | control to RTEMS. The default fatal error handler disables processor |
---|
| 551 | interrupts to level 15, places the error code in g1, and goes into an infinite |
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[d755cbd] | 552 | loop to simulate a halt processor instruction. |
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| 553 | |
---|
| 554 | Symmetric Multiprocessing |
---|
| 555 | ========================= |
---|
| 556 | |
---|
| 557 | SMP is not supported. |
---|
| 558 | |
---|
| 559 | Thread-Local Storage |
---|
| 560 | ==================== |
---|
| 561 | |
---|
| 562 | Thread-local storage is supported. |
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| 563 | |
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| 564 | Board Support Packages |
---|
| 565 | ====================== |
---|
| 566 | |
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[f233256] | 567 | An RTEMS Board Support Package (BSP) must be designed to support a particular |
---|
| 568 | processor and target board combination. This chapter presents a discussion of |
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| 569 | SPARC specific BSP issues. For more information on developing a BSP, refer to |
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| 570 | the chapter titled Board Support Packages in the RTEMS Applications User's |
---|
| 571 | Guide. |
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[d755cbd] | 572 | |
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| 573 | HelenOS and Open Firmware |
---|
| 574 | ------------------------- |
---|
| 575 | |
---|
[f233256] | 576 | The provided BSPs make use of some bootstrap and low-level hardware code of the |
---|
| 577 | HelenOS operating system. These files can be found in the shared/helenos |
---|
| 578 | directory of the sparc64 bsp directory. Consult the sources for more detailed |
---|
| 579 | information. |
---|
[d755cbd] | 580 | |
---|
| 581 | The shared BSP code also uses the Open Firmware interface to re-use firmware |
---|
| 582 | code, primarily for console support and default trap handlers. |
---|