1 | .. comment SPDX-License-Identifier: CC-BY-SA-4.0 |
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2 | |
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3 | .. COMMENT: COPYRIGHT (c) 1988-2002. |
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4 | .. COMMENT: On-Line Applications Research Corporation (OAR). |
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5 | .. COMMENT: All rights reserved. |
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6 | |
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7 | SPARC Specific Information |
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8 | ************************** |
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9 | |
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10 | The Real Time Executive for Multiprocessor Systems (RTEMS) is designed to be |
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11 | portable across multiple processor architectures. However, the nature of |
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12 | real-time systems makes it essential that the application designer understand |
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13 | certain processor dependent implementation details. These processor |
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14 | dependencies include calling convention, board support package issues, |
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15 | interrupt processing, exact RTEMS memory requirements, performance data, header |
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16 | files, and the assembly language interface to the executive. |
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17 | |
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18 | This document discusses the SPARC architecture dependencies in this port of |
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19 | RTEMS. This architectural port is for SPARC Version 7 and |
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20 | 8. Implementations for SPARC V9 are in the sparc64 target. |
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21 | |
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22 | It is highly recommended that the SPARC RTEMS application developer obtain and |
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23 | become familiar with the documentation for the processor being used as well as |
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24 | the specification for the revision of the SPARC architecture which corresponds |
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25 | to that processor. |
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26 | |
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27 | **SPARC Architecture Documents** |
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28 | |
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29 | For information on the SPARC architecture, refer to the following documents |
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30 | available from SPARC International, Inc. (http://www.sparc.com): |
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31 | |
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32 | - SPARC Standard Version 7. |
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33 | |
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34 | - SPARC Standard Version 8. |
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35 | |
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36 | **ERC32 Specific Information** |
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37 | |
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38 | The European Space Agency's ERC32 is a microprocessor implementing a |
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39 | SPARC V7 processor and associated support circuitry for embedded space |
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40 | applications. The integer and floating-point units (90C601E & 90C602E) are |
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41 | based on the Cypress 7C601 and 7C602, with additional error-detection and |
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42 | recovery functions. The memory controller (MEC) implements system support |
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43 | functions such as address decoding, memory interface, DMA interface, UARTs, |
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44 | timers, interrupt control, write-protection, memory reconfiguration and |
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45 | error-detection. The core is designed to work at 25MHz, but using space |
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46 | qualified memories limits the system frequency to around 15 MHz, resulting in a |
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47 | performance of 10 MIPS and 2 MFLOPS. |
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48 | |
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49 | The ERC32 is available from Atmel as the TSC695F. |
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50 | |
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51 | The RTEMS configuration of GDB enables the SPARC Instruction Simulator (SIS) |
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52 | which can simulate the ERC32 as well as the follow up LEON2 and LEON3 |
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53 | microprocessors. |
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54 | |
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55 | CPU Model Dependent Features |
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56 | ============================ |
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57 | |
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58 | Microprocessors are generally classified into families with a variety of CPU |
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59 | models or implementations within that family. Within a processor family, there |
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60 | is a high level of binary compatibility. This family may be based on either an |
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61 | architectural specification or on maintaining compatibility with a popular |
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62 | processor. Recent microprocessor families such as the SPARC or PowerPC are |
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63 | based on an architectural specification which is independent or any particular |
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64 | CPU model or implementation. Older families such as the M68xxx and the iX86 |
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65 | evolved as the manufacturer strived to produce higher performance processor |
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66 | models which maintained binary compatibility with older models. |
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67 | |
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68 | RTEMS takes advantage of the similarity of the various models within a CPU |
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69 | family. Although the models do vary in significant ways, the high level of |
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70 | compatibility makes it possible to share the bulk of the CPU dependent |
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71 | executive code across the entire family. |
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72 | |
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73 | CPU Model Feature Flags |
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74 | ----------------------- |
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75 | |
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76 | Each processor family supported by RTEMS has a list of features which vary |
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77 | between CPU models within a family. For example, the most common model |
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78 | dependent feature regardless of CPU family is the presence or absence of a |
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79 | floating point unit or coprocessor. When defining the list of features present |
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80 | on a particular CPU model, one simply notes that floating point hardware is or |
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81 | is not present and defines a single constant appropriately. Conditional |
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82 | compilation is utilized to include the appropriate source code for this CPU |
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83 | model's feature set. It is important to note that this means that RTEMS is |
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84 | thus compiled using the appropriate feature set and compilation flags optimal |
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85 | for this CPU model used. The alternative would be to generate a binary which |
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86 | would execute on all family members using only the features which were always |
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87 | present. |
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88 | |
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89 | This section presents the set of features which vary across SPARC |
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90 | implementations and are of importance to RTEMS. The set of CPU model feature |
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91 | macros are defined in the file cpukit/score/cpu/sparc/sparc.h based upon the |
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92 | particular CPU model defined on the compilation command line. |
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93 | |
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94 | CPU Model Name |
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95 | ~~~~~~~~~~~~~~ |
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96 | |
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97 | The macro CPU_MODEL_NAME is a string which designates the name of this CPU |
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98 | model. For example, for the European Space Agency's ERC32 SPARC model, this |
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99 | macro is set to the string "erc32". |
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100 | |
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101 | Floating Point Unit |
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102 | ~~~~~~~~~~~~~~~~~~~ |
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103 | |
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104 | The macro SPARC_HAS_FPU is set to 1 to indicate that this CPU model has a |
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105 | hardware floating point unit and 0 otherwise. |
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106 | |
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107 | Bitscan Instruction |
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108 | ~~~~~~~~~~~~~~~~~~~ |
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109 | |
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110 | The macro SPARC_HAS_BITSCAN is set to 1 to indicate that this CPU model has the |
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111 | bitscan instruction. For example, this instruction is supported by the Fujitsu |
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112 | SPARClite family. |
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113 | |
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114 | Number of Register Windows |
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115 | ~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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116 | |
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117 | The macro SPARC_NUMBER_OF_REGISTER_WINDOWS is set to indicate the number of |
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118 | register window sets implemented by this CPU model. The SPARC architecture |
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119 | allows a for a maximum of thirty-two register window sets although most |
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120 | implementations only include eight. |
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121 | |
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122 | Low Power Mode |
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123 | ~~~~~~~~~~~~~~ |
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124 | |
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125 | The macro SPARC_HAS_LOW_POWER_MODE is set to one to indicate that this CPU |
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126 | model has a low power mode. If low power is enabled, then there must be CPU |
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127 | model specific implementation of the IDLE task in cpukit/score/cpu/sparc/cpu.c. |
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128 | The low power mode IDLE task should be of the form: |
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129 | |
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130 | .. code-block:: c |
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131 | |
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132 | while ( TRUE ) { |
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133 | enter low power mode |
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134 | } |
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135 | |
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136 | The code required to enter low power mode is CPU model specific. |
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137 | |
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138 | CPU Model Implementation Notes |
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139 | ------------------------------ |
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140 | |
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141 | The ERC32 is a custom SPARC V7 implementation based on the Cypress 601/602 |
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142 | chipset. This CPU has a number of on-board peripherals and was developed by |
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143 | the European Space Agency to target space applications. RTEMS currently |
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144 | provides support for the following peripherals: |
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145 | |
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146 | - UART Channels A and B |
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147 | |
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148 | - General Purpose Timer |
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149 | |
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150 | - Real Time Clock |
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151 | |
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152 | - Watchdog Timer (so it can be disabled) |
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153 | |
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154 | - Control Register (so powerdown mode can be enabled) |
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155 | |
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156 | - Memory Control Register |
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157 | |
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158 | - Interrupt Control |
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159 | |
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160 | The General Purpose Timer and Real Time Clock Timer provided with the ERC32 |
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161 | share the Timer Control Register. Because the Timer Control Register is write |
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162 | only, we must mirror it in software and insure that writes to one timer do not |
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163 | alter the current settings and status of the other timer. Routines are |
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164 | provided in erc32.h which promote the view that the two timers are completely |
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165 | independent. By exclusively using these routines to access the Timer Control |
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166 | Register, the application can view the system as having a General Purpose Timer |
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167 | Control Register and a Real Time Clock Timer Control Register rather than the |
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168 | single shared value. |
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169 | |
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170 | The RTEMS Idle thread take advantage of the low power mode provided by the |
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171 | ERC32. Low power mode is entered during idle loops and is enabled at |
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172 | initialization time. |
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173 | |
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174 | Calling Conventions |
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175 | =================== |
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176 | |
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177 | Each high-level language compiler generates subroutine entry and exit code |
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178 | based upon a set of rules known as the application binary interface (ABI) |
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179 | calling convention. These rules address the following issues: |
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180 | |
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181 | - register preservation and usage |
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182 | |
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183 | - parameter passing |
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184 | |
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185 | - call and return mechanism |
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186 | |
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187 | An ABI calling convention is of importance when interfacing to subroutines |
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188 | written in another language either assembly or high-level. It determines also |
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189 | the set of registers to be saved or restored during a context switch and |
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190 | interrupt processing. |
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191 | |
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192 | The ABI relevant for RTEMS on SPARC is defined by SYSTEM V APPLICATION BINARY |
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193 | INTERFACE, SPARC Processor Supplement, Third Edition. |
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194 | |
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195 | Programming Model |
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196 | ----------------- |
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197 | |
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198 | This section discusses the programming model for the SPARC architecture. |
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199 | |
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200 | Non-Floating Point Registers |
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201 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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202 | |
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203 | The SPARC architecture defines thirty-two non-floating point registers directly |
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204 | visible to the programmer. These are divided into four sets: |
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205 | |
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206 | - input registers |
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207 | |
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208 | - local registers |
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209 | |
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210 | - output registers |
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211 | |
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212 | - global registers |
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213 | |
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214 | Each register is referred to by either two or three names in the SPARC |
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215 | reference manuals. First, the registers are referred to as r0 through r31 or |
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216 | with the alternate notation r[0] through r[31]. Second, each register is a |
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217 | member of one of the four sets listed above. Finally, some registers have an |
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218 | architecturally defined role in the programming model which provides an |
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219 | alternate name. The following table describes the mapping between the 32 |
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220 | registers and the register sets: |
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221 | |
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222 | ================ ================ =================== |
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223 | Register Number Register Names Description |
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224 | ================ ================ =================== |
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225 | 0 - 7 g0 - g7 Global Registers |
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226 | 8 - 15 o0 - o7 Output Registers |
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227 | 16 - 23 l0 - l7 Local Registers |
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228 | 24 - 31 i0 - i7 Input Registers |
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229 | ================ ================ =================== |
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230 | |
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231 | As mentioned above, some of the registers serve defined roles in the |
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232 | programming model. The following table describes the role of each of these |
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233 | registers: |
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234 | |
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235 | ============== ================ ================================== |
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236 | Register Name Alternate Name Description |
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237 | ============== ================ ================================== |
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238 | g0 na reads return 0, writes are ignored |
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239 | o6 sp stack pointer |
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240 | i6 fp frame pointer |
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241 | i7 na return address |
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242 | ============== ================ ================================== |
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243 | |
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244 | The registers g2 through g4 are reserved for applications. GCC uses them as |
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245 | volatile registers by default. So they are treated like volatile registers in |
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246 | RTEMS as well. |
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247 | |
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248 | The register g6 is reserved for the operating system and contains the address |
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249 | of the per-CPU control block of the current processor. This register is |
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250 | initialized during system start and then remains unchanged. It is not |
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251 | saved/restored by the context switch or interrupt processing code. |
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252 | |
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253 | The register g7 is reserved for the operating system and contains the thread |
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254 | pointer used for thread-local storage (TLS) as mandated by the SPARC ABI. |
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255 | |
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256 | Floating Point Registers |
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257 | ~~~~~~~~~~~~~~~~~~~~~~~~ |
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258 | |
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259 | The SPARC V7 architecture includes thirty-two, thirty-two bit registers. These |
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260 | registers may be viewed as follows: |
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261 | |
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262 | - 32 single precision floating point or integer registers (f0, f1, ... f31) |
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263 | |
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264 | - 16 double precision floating point registers (f0, f2, f4, ... f30) |
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265 | |
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266 | - 8 extended precision floating point registers (f0, f4, f8, ... f28) |
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267 | |
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268 | The floating point status register (FSR) specifies the behavior of the floating |
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269 | point unit for rounding, contains its condition codes, version specification, |
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270 | and trap information. |
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271 | |
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272 | According to the ABI all floating point registers and the floating point status |
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273 | register (FSR) are volatile. Thus the floating point context of a thread is |
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274 | the empty set. The rounding direction is a system global state and must not be |
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275 | modified by threads. |
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276 | |
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277 | A queue of the floating point instructions which have started execution but not |
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278 | yet completed is maintained. This queue is needed to support the multiple |
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279 | cycle nature of floating point operations and to aid floating point exception |
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280 | trap handlers. Once a floating point exception has been encountered, the queue |
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281 | is frozen until it is emptied by the trap handler. The floating point queue is |
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282 | loaded by launching instructions. It is emptied normally when the floating |
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283 | point completes all outstanding instructions and by floating point exception |
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284 | handlers with the store double floating point queue (stdfq) instruction. |
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285 | |
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286 | Special Registers |
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287 | ~~~~~~~~~~~~~~~~~ |
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288 | |
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289 | The SPARC architecture includes two special registers which are critical to the |
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290 | programming model: the Processor State Register (psr) and the Window Invalid |
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291 | Mask (wim). The psr contains the condition codes, processor interrupt level, |
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292 | trap enable bit, supervisor mode and previous supervisor mode bits, version |
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293 | information, floating point unit and coprocessor enable bits, and the current |
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294 | window pointer (cwp). The cwp field of the psr and wim register are used to |
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295 | manage the register windows in the SPARC architecture. The register windows |
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296 | are discussed in more detail below. |
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297 | |
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298 | Register Windows |
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299 | ---------------- |
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300 | |
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301 | The SPARC architecture includes the concept of register windows. An overly |
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302 | simplistic way to think of these windows is to imagine them as being an |
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303 | infinite supply of "fresh" register sets available for each subroutine to use. |
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304 | In reality, they are much more complicated. |
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305 | |
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306 | The save instruction is used to obtain a new register window. This instruction |
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307 | decrements the current window pointer, thus providing a new set of registers |
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308 | for use. This register set includes eight fresh local registers for use |
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309 | exclusively by this subroutine. When done with a register set, the restore |
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310 | instruction increments the current window pointer and the previous register set |
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311 | is once again available. |
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312 | |
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313 | The two primary issues complicating the use of register windows are that (1) |
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314 | the set of register windows is finite, and (2) some registers are shared |
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315 | between adjacent registers windows. |
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316 | |
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317 | Because the set of register windows is finite, it is possible to execute enough |
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318 | save instructions without corresponding restore's to consume all of the |
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319 | register windows. This is easily accomplished in a high level language because |
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320 | each subroutine typically performs a save instruction upon entry. Thus having |
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321 | a subroutine call depth greater than the number of register windows will result |
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322 | in a window overflow condition. The window overflow condition generates a trap |
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323 | which must be handled in software. The window overflow trap handler is |
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324 | responsible for saving the contents of the oldest register window on the |
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325 | program stack. |
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326 | |
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327 | Similarly, the subroutines will eventually complete and begin to perform |
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328 | restore's. If the restore results in the need for a register window which has |
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329 | previously been written to memory as part of an overflow, then a window |
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330 | underflow condition results. Just like the window overflow, the window |
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331 | underflow condition must be handled in software by a trap handler. The window |
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332 | underflow trap handler is responsible for reloading the contents of the |
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333 | register window requested by the restore instruction from the program stack. |
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334 | |
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335 | The Window Invalid Mask (wim) and the Current Window Pointer (cwp) field in the |
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336 | psr are used in conjunction to manage the finite set of register windows and |
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337 | detect the window overflow and underflow conditions. The cwp contains the |
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338 | index of the register window currently in use. The save instruction decrements |
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339 | the cwp modulo the number of register windows. Similarly, the restore |
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340 | instruction increments the cwp modulo the number of register windows. Each bit |
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341 | in the wim represents represents whether a register window contains valid |
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342 | information. The value of 0 indicates the register window is valid and 1 |
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343 | indicates it is invalid. When a save instruction causes the cwp to point to a |
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344 | register window which is marked as invalid, a window overflow condition |
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345 | results. Conversely, the restore instruction may result in a window underflow |
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346 | condition. |
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347 | |
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348 | Other than the assumption that a register window is always available for trap |
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349 | (i.e. interrupt) handlers, the SPARC architecture places no limits on the |
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350 | number of register windows simultaneously marked as invalid (i.e. number of |
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351 | bits set in the wim). However, RTEMS assumes that only one register window is |
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352 | marked invalid at a time (i.e. only one bit set in the wim). This makes the |
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353 | maximum possible number of register windows available to the user while still |
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354 | meeting the requirement that window overflow and underflow conditions can be |
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355 | detected. |
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356 | |
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357 | The window overflow and window underflow trap handlers are a critical part of |
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358 | the run-time environment for a SPARC application. The SPARC architectural |
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359 | specification allows for the number of register windows to be any power of two |
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360 | less than or equal to 32. The most common choice for SPARC implementations |
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361 | appears to be 8 register windows. This results in the cwp ranging in value |
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362 | from 0 to 7 on most implementations. |
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363 | |
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364 | The second complicating factor is the sharing of registers between adjacent |
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365 | register windows. While each register window has its own set of local |
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366 | registers, the input and output registers are shared between adjacent windows. |
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367 | The output registers for register window N are the same as the input registers |
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368 | for register window ((N - 1) modulo RW) where RW is the number of register |
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369 | windows. An alternative way to think of this is to remember how parameters are |
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370 | passed to a subroutine on the SPARC. The caller loads values into what are its |
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371 | output registers. Then after the callee executes a save instruction, those |
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372 | parameters are available in its input registers. This is a very efficient way |
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373 | to pass parameters as no data is actually moved by the save or restore |
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374 | instructions. |
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375 | |
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376 | Call and Return Mechanism |
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377 | ------------------------- |
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378 | |
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379 | The SPARC architecture supports a simple yet effective call and return |
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380 | mechanism. A subroutine is invoked via the call (call) instruction. This |
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381 | instruction places the return address in the caller's output register 7 (o7). |
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382 | After the callee executes a save instruction, this value is available in input |
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383 | register 7 (i7) until the corresponding restore instruction is executed. |
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384 | |
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385 | The callee returns to the caller via a jmp to the return address. There is a |
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386 | delay slot following this instruction which is commonly used to execute a |
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387 | restore instruction - if a register window was allocated by this subroutine. |
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388 | |
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389 | It is important to note that the SPARC subroutine call and return mechanism |
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390 | does not automatically save and restore any registers. This is accomplished |
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391 | via the save and restore instructions which manage the set of registers |
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392 | windows. |
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393 | |
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394 | In case a floating-point unit is supported, then floating-point return values |
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395 | appear in the floating-point registers. Single-precision values occupy %f0; |
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396 | double-precision values occupy %f0 and %f1. Otherwise, these are scratch |
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397 | registers. Due to this the hardware and software floating-point ABIs are |
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398 | incompatible. |
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399 | |
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400 | Calling Mechanism |
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401 | ----------------- |
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402 | |
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403 | All RTEMS directives are invoked using the regular SPARC calling convention via |
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404 | the call instruction. |
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405 | |
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406 | Register Usage |
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407 | -------------- |
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408 | |
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409 | As discussed above, the call instruction does not automatically save any |
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410 | registers. The save and restore instructions are used to allocate and |
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411 | deallocate register windows. When a register window is allocated, the new set |
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412 | of local registers are available for the exclusive use of the subroutine which |
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413 | allocated this register set. |
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414 | |
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415 | Parameter Passing |
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416 | ----------------- |
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417 | |
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418 | RTEMS assumes that arguments are placed in the caller's output registers with |
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419 | the first argument in output register 0 (o0), the second argument in output |
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420 | register 1 (o1), and so forth. Until the callee executes a save instruction, |
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421 | the parameters are still visible in the output registers. After the callee |
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422 | executes a save instruction, the parameters are visible in the corresponding |
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423 | input registers. The following pseudo-code illustrates the typical sequence |
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424 | used to call a RTEMS directive with three (3) arguments: |
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425 | |
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426 | .. code-block:: c |
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427 | |
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428 | load third argument into o2 |
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429 | load second argument into o1 |
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430 | load first argument into o0 |
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431 | invoke directive |
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432 | |
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433 | User-Provided Routines |
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434 | ---------------------- |
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435 | |
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436 | All user-provided routines invoked by RTEMS, such as user extensions, device |
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437 | drivers, and MPCI routines, must also adhere to these calling conventions. |
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438 | |
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439 | Memory Model |
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440 | ============ |
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441 | |
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442 | A processor may support any combination of memory models ranging from pure |
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443 | physical addressing to complex demand paged virtual memory systems. RTEMS |
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444 | supports a flat memory model which ranges contiguously over the processor's |
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445 | allowable address space. RTEMS does not support segmentation or virtual memory |
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446 | of any kind. The appropriate memory model for RTEMS provided by the targeted |
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447 | processor and related characteristics of that model are described in this |
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448 | chapter. |
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449 | |
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450 | Flat Memory Model |
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451 | ----------------- |
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452 | |
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453 | The SPARC architecture supports a flat 32-bit address space with addresses |
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454 | ranging from 0x00000000 to 0xFFFFFFFF (4 gigabytes). Each address is |
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455 | represented by a 32-bit value and is byte addressable. The address may be used |
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456 | to reference a single byte, half-word (2-bytes), word (4 bytes), or doubleword |
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457 | (8 bytes). Memory accesses within this address space are performed in big |
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458 | endian fashion by the SPARC. Memory accesses which are not properly aligned |
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459 | generate a "memory address not aligned" trap (type number 7). The following |
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460 | table lists the alignment requirements for a variety of data accesses: |
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461 | |
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462 | ============== ====================== |
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463 | Data Type Alignment Requirement |
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464 | ============== ====================== |
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465 | byte 1 |
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466 | half-word 2 |
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467 | word 4 |
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468 | doubleword 8 |
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469 | ============== ====================== |
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470 | |
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471 | Doubleword load and store operations must use a pair of registers as their |
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472 | source or destination. This pair of registers must be an adjacent pair of |
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473 | registers with the first of the pair being even numbered. For example, a valid |
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474 | destination for a doubleword load might be input registers 0 and 1 (i0 and i1). |
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475 | The pair i1 and i2 would be invalid. \[NOTE: Some assemblers for the SPARC do |
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476 | not generate an error if an odd numbered register is specified as the beginning |
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477 | register of the pair. In this case, the assembler assumes that what the |
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478 | programmer meant was to use the even-odd pair which ends at the specified |
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479 | register. This may or may not have been a correct assumption.] |
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480 | |
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481 | RTEMS does not support any SPARC Memory Management Units, therefore, virtual |
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482 | memory or segmentation systems involving the SPARC are not supported. |
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483 | |
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484 | Interrupt Processing |
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485 | ==================== |
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486 | |
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487 | Different types of processors respond to the occurrence of an interrupt in its |
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488 | own unique fashion. In addition, each processor type provides a control |
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489 | mechanism to allow for the proper handling of an interrupt. The processor |
---|
490 | dependent response to the interrupt modifies the current execution state and |
---|
491 | results in a change in the execution stream. Most processors require that an |
---|
492 | interrupt handler utilize some special control mechanisms to return to the |
---|
493 | normal processing stream. Although RTEMS hides many of the processor dependent |
---|
494 | details of interrupt processing, it is important to understand how the RTEMS |
---|
495 | interrupt manager is mapped onto the processor's unique architecture. Discussed |
---|
496 | in this chapter are the SPARC's interrupt response and control mechanisms as |
---|
497 | they pertain to RTEMS. |
---|
498 | |
---|
499 | RTEMS and associated documentation uses the terms interrupt and vector. In the |
---|
500 | SPARC architecture, these terms correspond to traps and trap type, |
---|
501 | respectively. The terms will be used interchangeably in this manual. |
---|
502 | |
---|
503 | Synchronous Versus Asynchronous Traps |
---|
504 | ------------------------------------- |
---|
505 | |
---|
506 | The SPARC architecture includes two classes of traps: synchronous and |
---|
507 | asynchronous. Asynchronous traps occur when an external event interrupts the |
---|
508 | processor. These traps are not associated with any instruction executed by the |
---|
509 | processor and logically occur between instructions. The instruction currently |
---|
510 | in the execute stage of the processor is allowed to complete although |
---|
511 | subsequent instructions are annulled. The return address reported by the |
---|
512 | processor for asynchronous traps is the pair of instructions following the |
---|
513 | current instruction. |
---|
514 | |
---|
515 | Synchronous traps are caused by the actions of an instruction. The trap |
---|
516 | stimulus in this case either occurs internally to the processor or is from an |
---|
517 | external signal that was provoked by the instruction. These traps are taken |
---|
518 | immediately and the instruction that caused the trap is aborted before any |
---|
519 | state changes occur in the processor itself. The return address reported by |
---|
520 | the processor for synchronous traps is the instruction which caused the trap |
---|
521 | and the following instruction. |
---|
522 | |
---|
523 | Vectoring of Interrupt Handler |
---|
524 | ------------------------------ |
---|
525 | |
---|
526 | Upon receipt of an interrupt the SPARC automatically performs the following |
---|
527 | actions: |
---|
528 | |
---|
529 | - disables traps (sets the ET bit of the psr to 0), |
---|
530 | |
---|
531 | - the S bit of the psr is copied into the Previous Supervisor Mode (PS) bit of |
---|
532 | the psr, |
---|
533 | |
---|
534 | - the cwp is decremented by one (modulo the number of register windows) to |
---|
535 | activate a trap window, |
---|
536 | |
---|
537 | - the PC and nPC are loaded into local register 1 and 2 (l0 and l1), |
---|
538 | |
---|
539 | - the trap type (tt) field of the Trap Base Register (TBR) is set to the |
---|
540 | appropriate value, and |
---|
541 | |
---|
542 | - if the trap is not a reset, then the PC is written with the contents of the |
---|
543 | TBR and the nPC is written with TBR + 4. If the trap is a reset, then the PC |
---|
544 | is set to zero and the nPC is set to 4. |
---|
545 | |
---|
546 | Trap processing on the SPARC has two features which are noticeably different |
---|
547 | than interrupt processing on other architectures. First, the value of psr |
---|
548 | register in effect immediately before the trap occurred is not explicitly |
---|
549 | saved. Instead only reversible alterations are made to it. Second, the |
---|
550 | Processor Interrupt Level (pil) is not set to correspond to that of the |
---|
551 | interrupt being processed. When a trap occurs, ALL subsequent traps are |
---|
552 | disabled. In order to safely invoke a subroutine during trap handling, traps |
---|
553 | must be enabled to allow for the possibility of register window overflow and |
---|
554 | underflow traps. |
---|
555 | |
---|
556 | If the interrupt handler was installed as an RTEMS interrupt handler, then upon |
---|
557 | receipt of the interrupt, the processor passes control to the RTEMS interrupt |
---|
558 | handler which performs the following actions: |
---|
559 | |
---|
560 | - saves the state of the interrupted task on it's stack, |
---|
561 | |
---|
562 | - insures that a register window is available for subsequent traps, |
---|
563 | |
---|
564 | - if this is the outermost (i.e. non-nested) interrupt, then the RTEMS |
---|
565 | interrupt handler switches from the current stack to the interrupt stack, |
---|
566 | |
---|
567 | - enables traps, |
---|
568 | |
---|
569 | - invokes the vectors to a user interrupt service routine (ISR). |
---|
570 | |
---|
571 | Asynchronous interrupts are ignored while traps are disabled. Synchronous |
---|
572 | traps which occur while traps are disabled result in the CPU being forced into |
---|
573 | an error mode. |
---|
574 | |
---|
575 | A nested interrupt is processed similarly with the exception that the current |
---|
576 | stack need not be switched to the interrupt stack. |
---|
577 | |
---|
578 | Traps and Register Windows |
---|
579 | -------------------------- |
---|
580 | |
---|
581 | One of the register windows must be reserved at all times for trap processing. |
---|
582 | This is critical to the proper operation of the trap mechanism in the SPARC |
---|
583 | architecture. It is the responsibility of the trap handler to insure that |
---|
584 | there is a register window available for a subsequent trap before re-enabling |
---|
585 | traps. It is likely that any high level language routines invoked by the trap |
---|
586 | handler (such as a user-provided RTEMS interrupt handler) will allocate a new |
---|
587 | register window. The save operation could result in a window overflow trap. |
---|
588 | This trap cannot be correctly processed unless (1) traps are enabled and (2) a |
---|
589 | register window is reserved for traps. Thus, the RTEMS interrupt handler |
---|
590 | insures that a register window is available for subsequent traps before |
---|
591 | enabling traps and invoking the user's interrupt handler. |
---|
592 | |
---|
593 | Interrupt Levels |
---|
594 | ---------------- |
---|
595 | |
---|
596 | Sixteen levels (0-15) of interrupt priorities are supported by the SPARC |
---|
597 | architecture with level fifteen (15) being the highest priority. Level |
---|
598 | zero (0) indicates that interrupts are fully enabled. Interrupt requests for |
---|
599 | interrupts with priorities less than or equal to the current interrupt mask |
---|
600 | level are ignored. Level fifteen (15) is a non-maskable interrupt (NMI), which |
---|
601 | makes it unsuitable for standard usage since it can affect the real-time |
---|
602 | behaviour by interrupting critical sections and spinlocks. Disabling traps |
---|
603 | stops also the NMI interrupt from happening. It can however be used for |
---|
604 | power-down or other critical events. |
---|
605 | |
---|
606 | Although RTEMS supports 256 interrupt levels, the SPARC only supports sixteen. |
---|
607 | RTEMS interrupt levels 0 through 15 directly correspond to SPARC processor |
---|
608 | interrupt levels. All other RTEMS interrupt levels are undefined and their |
---|
609 | behavior is unpredictable. |
---|
610 | |
---|
611 | Many LEON SPARC v7/v8 systems features an extended interrupt controller which |
---|
612 | adds an extra step of interrupt decoding to allow handling of interrupt |
---|
613 | 16-31. When such an extended interrupt is generated the CPU traps into a |
---|
614 | specific interrupt trap level 1-14 and software reads out from the interrupt |
---|
615 | controller which extended interrupt source actually caused the interrupt. |
---|
616 | |
---|
617 | Disabling of Interrupts by RTEMS |
---|
618 | -------------------------------- |
---|
619 | |
---|
620 | During the execution of directive calls, critical sections of code may be |
---|
621 | executed. When these sections are encountered, RTEMS disables interrupts to |
---|
622 | level fifteen (15) before the execution of the section and restores them to the |
---|
623 | previous level upon completion of the section. RTEMS has been optimized to |
---|
624 | ensure that interrupts are disabled for less than RTEMS_MAXIMUM_DISABLE_PERIOD |
---|
625 | microseconds on a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz ERC32 with zero wait |
---|
626 | states. These numbers will vary based the number of wait states and processor |
---|
627 | speed present on the target board. [NOTE: The maximum period with interrupts |
---|
628 | disabled is hand calculated. This calculation was last performed for Release |
---|
629 | RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.] |
---|
630 | |
---|
631 | [NOTE: It is thought that the length of time at which the processor interrupt |
---|
632 | level is elevated to fifteen by RTEMS is not anywhere near as long as the |
---|
633 | length of time ALL traps are disabled as part of the "flush all register |
---|
634 | windows" operation.] |
---|
635 | |
---|
636 | Non-maskable interrupts (NMI) cannot be disabled, and ISRs which execute at |
---|
637 | this level MUST NEVER issue RTEMS system calls. If a directive is invoked, |
---|
638 | unpredictable results may occur due to the inability of RTEMS to protect its |
---|
639 | critical sections. However, ISRs that make no system calls may safely execute |
---|
640 | as non-maskable interrupts. |
---|
641 | |
---|
642 | Interrupts are disabled or enabled by performing a system call to the Operating |
---|
643 | System reserved software traps 9 (SPARC_SWTRAP_IRQDIS) or 10 |
---|
644 | (SPARC_SWTRAP_IRQDIS). The trap is generated by the software trap (Ticc) |
---|
645 | instruction or indirectly by calling sparc_disable_interrupts() or |
---|
646 | sparc_enable_interrupts() functions. Disabling interrupts return the previous |
---|
647 | interrupt level (on trap entry) in register G1 and sets PSR.PIL to 15 to |
---|
648 | disable all maskable interrupts. The interrupt level can be restored by |
---|
649 | trapping into the enable interrupt handler with G1 containing the new interrupt |
---|
650 | level. |
---|
651 | |
---|
652 | Interrupt Stack |
---|
653 | --------------- |
---|
654 | |
---|
655 | The SPARC architecture does not provide for a dedicated interrupt stack. Thus |
---|
656 | by default, trap handlers would execute on the stack of the RTEMS task which |
---|
657 | they interrupted. This artificially inflates the stack requirements for each |
---|
658 | task since EVERY task stack would have to include enough space to account for |
---|
659 | the worst case interrupt stack requirements in addition to it's own worst case |
---|
660 | usage. RTEMS addresses this problem on the SPARC by providing a dedicated |
---|
661 | interrupt stack managed by software. |
---|
662 | |
---|
663 | During system initialization, RTEMS allocates the interrupt stack from the |
---|
664 | Workspace Area. The amount of memory allocated for the interrupt stack is |
---|
665 | determined by the interrupt_stack_size field in the CPU Configuration Table. |
---|
666 | As part of processing a non-nested interrupt, RTEMS will switch to the |
---|
667 | interrupt stack before invoking the installed handler. |
---|
668 | |
---|
669 | Default Fatal Error Processing |
---|
670 | ============================== |
---|
671 | |
---|
672 | Upon detection of a fatal error by either the application or RTEMS the fatal |
---|
673 | error manager is invoked. The fatal error manager will invoke the |
---|
674 | user-supplied fatal error handlers. If no user-supplied handlers are |
---|
675 | configured, the RTEMS provided default fatal error handler is invoked. If the |
---|
676 | user-supplied fatal error handlers return to the executive the default fatal |
---|
677 | error handler is then invoked. This chapter describes the precise operations |
---|
678 | of the default fatal error handler. |
---|
679 | |
---|
680 | Default Fatal Error Handler Operations |
---|
681 | -------------------------------------- |
---|
682 | |
---|
683 | The default fatal error handler which is invoked by the fatal_error_occurred |
---|
684 | directive when there is no user handler configured or the user handler returns |
---|
685 | control to RTEMS. |
---|
686 | |
---|
687 | If the BSP has been configured with ``BSP_POWER_DOWN_AT_FATAL_HALT`` set to |
---|
688 | true, the default handler will disable interrupts and enter power down mode. If |
---|
689 | power down mode is not available, it goes into an infinite loop to simulate a |
---|
690 | halt processor instruction. |
---|
691 | |
---|
692 | If ``BSP_POWER_DOWN_AT_FATAL_HALT`` is set to false, the default handler will |
---|
693 | place the value ``1`` in register ``g1``, the error source in register ``g2``, |
---|
694 | and the error code in register``g3``. It will then generate a system error |
---|
695 | which will hand over control to the debugger, simulator, etc. |
---|
696 | |
---|
697 | Symmetric Multiprocessing |
---|
698 | ========================= |
---|
699 | |
---|
700 | SMP is supported. Available platforms are the Cobham Gaisler GR712RC and |
---|
701 | GR740. |
---|
702 | |
---|
703 | Thread-Local Storage |
---|
704 | ==================== |
---|
705 | |
---|
706 | Thread-local storage is supported. |
---|
707 | |
---|
708 | Board Support Packages |
---|
709 | ====================== |
---|
710 | |
---|
711 | An RTEMS Board Support Package (BSP) must be designed to support a particular |
---|
712 | processor and target board combination. This chapter presents a discussion of |
---|
713 | SPARC specific BSP issues. For more information on developing a BSP, refer to |
---|
714 | the chapter titled Board Support Packages in the RTEMS Applications User's |
---|
715 | Guide. |
---|
716 | |
---|
717 | System Reset |
---|
718 | ------------ |
---|
719 | |
---|
720 | An RTEMS based application is initiated or re-initiated when the SPARC |
---|
721 | processor is reset. When the SPARC is reset, the processor performs the |
---|
722 | following actions: |
---|
723 | |
---|
724 | - the enable trap (ET) of the psr is set to 0 to disable traps, |
---|
725 | |
---|
726 | - the supervisor bit (S) of the psr is set to 1 to enter supervisor mode, and |
---|
727 | |
---|
728 | - the PC is set 0 and the nPC is set to 4. |
---|
729 | |
---|
730 | The processor then begins to execute the code at location 0. It is important |
---|
731 | to note that all fields in the psr are not explicitly set by the above steps |
---|
732 | and all other registers retain their value from the previous execution mode. |
---|
733 | This is true even of the Trap Base Register (TBR) whose contents reflect the |
---|
734 | last trap which occurred before the reset. |
---|
735 | |
---|
736 | Processor Initialization |
---|
737 | ------------------------ |
---|
738 | |
---|
739 | It is the responsibility of the application's initialization code to initialize |
---|
740 | the TBR and install trap handlers for at least the register window overflow and |
---|
741 | register window underflow conditions. Traps should be enabled before invoking |
---|
742 | any subroutines to allow for register window management. However, interrupts |
---|
743 | should be disabled by setting the Processor Interrupt Level (pil) field of the |
---|
744 | psr to 15. RTEMS installs it's own Trap Table as part of initialization which |
---|
745 | is initialized with the contents of the Trap Table in place when the |
---|
746 | ``rtems_initialize_executive`` directive was invoked. Upon completion of |
---|
747 | executive initialization, interrupts are enabled. |
---|
748 | |
---|
749 | If this SPARC implementation supports on-chip caching and this is to be |
---|
750 | utilized, then it should be enabled during the reset application initialization |
---|
751 | code. |
---|
752 | |
---|
753 | In addition to the requirements described in the Board Support Packages chapter |
---|
754 | of the C Applications Users Manual for the reset code which is executed before |
---|
755 | the call to``rtems_initialize_executive``, the SPARC version has the following |
---|
756 | specific requirements: |
---|
757 | |
---|
758 | - Must leave the S bit of the status register set so that the SPARC remains in |
---|
759 | the supervisor state. |
---|
760 | |
---|
761 | - Must set stack pointer (sp) such that a minimum stack size of |
---|
762 | MINIMUM_STACK_SIZE bytes is provided for the``rtems_initialize_executive`` |
---|
763 | directive. |
---|
764 | |
---|
765 | - Must disable all external interrupts (i.e. set the pil to 15). |
---|
766 | |
---|
767 | - Must enable traps so window overflow and underflow conditions can be properly |
---|
768 | handled. |
---|
769 | |
---|
770 | - Must initialize the SPARC's initial trap table with at least trap handlers |
---|
771 | for register window overflow and register window underflow. |
---|