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[489740f]1.. comment SPDX-License-Identifier: CC-BY-SA-4.0
[f233256]3.. COMMENT: COPYRIGHT (c) 1988-2002.
4.. COMMENT: On-Line Applications Research Corporation (OAR).
5.. COMMENT: All rights reserved.
[d755cbd]7SPARC Specific Information
[f233256]10The Real Time Executive for Multiprocessor Systems (RTEMS) is designed to be
11portable across multiple processor architectures.  However, the nature of
12real-time systems makes it essential that the application designer understand
13certain processor dependent implementation details.  These processor
14dependencies include calling convention, board support package issues,
15interrupt processing, exact RTEMS memory requirements, performance data, header
16files, and the assembly language interface to the executive.
18This document discusses the SPARC architecture dependencies in this port of
19RTEMS.  This architectural port is for SPARC Version 7 and
[d755cbd]208. Implementations for SPARC V9 are in the sparc64 target.
[f233256]22It is highly recommended that the SPARC RTEMS application developer obtain and
23become familiar with the documentation for the processor being used as well as
24the specification for the revision of the SPARC architecture which corresponds
25to that processor.
27**SPARC Architecture Documents**
[f233256]29For information on the SPARC architecture, refer to the following documents
30available from SPARC International, Inc.  (
32- SPARC Standard Version 7.
34- SPARC Standard Version 8.
36**ERC32 Specific Information**
[d8beaab]38The European Space Agency's ERC32 is a microprocessor implementing a
[f233256]39SPARC V7 processor and associated support circuitry for embedded space
40applications. The integer and floating-point units (90C601E & 90C602E) are
41based on the Cypress 7C601 and 7C602, with additional error-detection and
42recovery functions. The memory controller (MEC) implements system support
43functions such as address decoding, memory interface, DMA interface, UARTs,
44timers, interrupt control, write-protection, memory reconfiguration and
45error-detection.  The core is designed to work at 25MHz, but using space
46qualified memories limits the system frequency to around 15 MHz, resulting in a
47performance of 10 MIPS and 2 MFLOPS.
[d8beaab]49The ERC32 is available from Atmel as the TSC695F.
[d8beaab]51The RTEMS configuration of GDB enables the SPARC Instruction Simulator (SIS)
52which can simulate the ERC32 as well as the follow up LEON2 and LEON3
55CPU Model Dependent Features
[f233256]58Microprocessors are generally classified into families with a variety of CPU
59models or implementations within that family.  Within a processor family, there
60is a high level of binary compatibility.  This family may be based on either an
61architectural specification or on maintaining compatibility with a popular
62processor.  Recent microprocessor families such as the SPARC or PowerPC are
63based on an architectural specification which is independent or any particular
64CPU model or implementation.  Older families such as the M68xxx and the iX86
65evolved as the manufacturer strived to produce higher performance processor
66models which maintained binary compatibility with older models.
68RTEMS takes advantage of the similarity of the various models within a CPU
69family.  Although the models do vary in significant ways, the high level of
70compatibility makes it possible to share the bulk of the CPU dependent
71executive code across the entire family.
73CPU Model Feature Flags
[f233256]76Each processor family supported by RTEMS has a list of features which vary
77between CPU models within a family.  For example, the most common model
78dependent feature regardless of CPU family is the presence or absence of a
79floating point unit or coprocessor.  When defining the list of features present
80on a particular CPU model, one simply notes that floating point hardware is or
81is not present and defines a single constant appropriately.  Conditional
82compilation is utilized to include the appropriate source code for this CPU
83model's feature set.  It is important to note that this means that RTEMS is
84thus compiled using the appropriate feature set and compilation flags optimal
85for this CPU model used.  The alternative would be to generate a binary which
86would execute on all family members using only the features which were always
[f233256]89This section presents the set of features which vary across SPARC
90implementations and are of importance to RTEMS.  The set of CPU model feature
91macros are defined in the file cpukit/score/cpu/sparc/sparc.h based upon the
92particular CPU model defined on the compilation command line.
94CPU Model Name
[f233256]97The macro CPU_MODEL_NAME is a string which designates the name of this CPU
98model.  For example, for the European Space Agency's ERC32 SPARC model, this
99macro is set to the string "erc32".
101Floating Point Unit
[f233256]104The macro SPARC_HAS_FPU is set to 1 to indicate that this CPU model has a
105hardware floating point unit and 0 otherwise.
107Bitscan Instruction
[f233256]110The macro SPARC_HAS_BITSCAN is set to 1 to indicate that this CPU model has the
111bitscan instruction.  For example, this instruction is supported by the Fujitsu
112SPARClite family.
114Number of Register Windows
[f233256]117The macro SPARC_NUMBER_OF_REGISTER_WINDOWS is set to indicate the number of
118register window sets implemented by this CPU model.  The SPARC architecture
119allows a for a maximum of thirty-two register window sets although most
120implementations only include eight.
122Low Power Mode
[f233256]125The macro SPARC_HAS_LOW_POWER_MODE is set to one to indicate that this CPU
126model has a low power mode.  If low power is enabled, then there must be CPU
127model specific implementation of the IDLE task in cpukit/score/cpu/sparc/cpu.c.
128The low power mode IDLE task should be of the form:
130.. code-block:: c
132    while ( TRUE ) {
[f233256]133        enter low power mode
[d755cbd]134    }
136The code required to enter low power mode is CPU model specific.
138CPU Model Implementation Notes
141The ERC32 is a custom SPARC V7 implementation based on the Cypress 601/602
142chipset.  This CPU has a number of on-board peripherals and was developed by
143the European Space Agency to target space applications.  RTEMS currently
144provides support for the following peripherals:
146- UART Channels A and B
148- General Purpose Timer
150- Real Time Clock
152- Watchdog Timer (so it can be disabled)
154- Control Register (so powerdown mode can be enabled)
156- Memory Control Register
158- Interrupt Control
160The General Purpose Timer and Real Time Clock Timer provided with the ERC32
161share the Timer Control Register.  Because the Timer Control Register is write
162only, we must mirror it in software and insure that writes to one timer do not
163alter the current settings and status of the other timer.  Routines are
164provided in erc32.h which promote the view that the two timers are completely
165independent.  By exclusively using these routines to access the Timer Control
[f233256]166Register, the application can view the system as having a General Purpose Timer
167Control Register and a Real Time Clock Timer Control Register rather than the
168single shared value.
170The RTEMS Idle thread take advantage of the low power mode provided by the
171ERC32.  Low power mode is entered during idle loops and is enabled at
172initialization time.
174Calling Conventions
177Each high-level language compiler generates subroutine entry and exit code
178based upon a set of rules known as the application binary interface (ABI)
[f233256]179calling convention.  These rules address the following issues:
181- register preservation and usage
183- parameter passing
185- call and return mechanism
187An ABI calling convention is of importance when interfacing to subroutines
188written in another language either assembly or high-level.  It determines also
189the set of registers to be saved or restored during a context switch and
190interrupt processing.
192The ABI relevant for RTEMS on SPARC is defined by SYSTEM V APPLICATION BINARY
193INTERFACE, SPARC Processor Supplement, Third Edition.
195Programming Model
[f233256]198This section discusses the programming model for the SPARC architecture.
200Non-Floating Point Registers
[f233256]203The SPARC architecture defines thirty-two non-floating point registers directly
204visible to the programmer.  These are divided into four sets:
206- input registers
208- local registers
210- output registers
212- global registers
[f233256]214Each register is referred to by either two or three names in the SPARC
215reference manuals.  First, the registers are referred to as r0 through r31 or
216with the alternate notation r[0] through r[31].  Second, each register is a
217member of one of the four sets listed above.  Finally, some registers have an
218architecturally defined role in the programming model which provides an
219alternate name.  The following table describes the mapping between the 32
220registers and the register sets:
[0c97890]222================ ================ ===================
223Register Number  Register Names   Description
224================ ================ ===================
2250 - 7            g0 - g7          Global Registers
2268 - 15           o0 - o7          Output Registers
22716 - 23          l0 - l7          Local Registers
22824 - 31          i0 - i7          Input Registers
229================ ================ ===================
231As mentioned above, some of the registers serve defined roles in the
232programming model.  The following table describes the role of each of these
[0c97890]235============== ================ ==================================
236Register Name  Alternate Name   Description
237============== ================ ==================================
238g0             na               reads return 0, writes are ignored
239o6             sp               stack pointer
240i6             fp               frame pointer
241i7             na               return address
242============== ================ ==================================
244The registers g2 through g4 are reserved for applications.  GCC uses them as
245volatile registers by default.  So they are treated like volatile registers in
246RTEMS as well.
248The register g6 is reserved for the operating system and contains the address
249of the per-CPU control block of the current processor.  This register is
250initialized during system start and then remains unchanged.  It is not
251saved/restored by the context switch or interrupt processing code.
253The register g7 is reserved for the operating system and contains the thread
254pointer used for thread-local storage (TLS) as mandated by the SPARC ABI.
256Floating Point Registers
[f233256]259The SPARC V7 architecture includes thirty-two, thirty-two bit registers.  These
260registers may be viewed as follows:
[f233256]262- 32 single precision floating point or integer registers (f0, f1, ... f31)
[f233256]264- 16 double precision floating point registers (f0, f2, f4, ... f30)
[f233256]266- 8 extended precision floating point registers (f0, f4, f8, ... f28)
[f233256]268The floating point status register (FSR) specifies the behavior of the floating
269point unit for rounding, contains its condition codes, version specification,
270and trap information.
272According to the ABI all floating point registers and the floating point status
[f233256]273register (FSR) are volatile.  Thus the floating point context of a thread is
274the empty set.  The rounding direction is a system global state and must not be
[d755cbd]275modified by threads.
[f233256]277A queue of the floating point instructions which have started execution but not
278yet completed is maintained.  This queue is needed to support the multiple
279cycle nature of floating point operations and to aid floating point exception
280trap handlers.  Once a floating point exception has been encountered, the queue
281is frozen until it is emptied by the trap handler.  The floating point queue is
282loaded by launching instructions.  It is emptied normally when the floating
283point completes all outstanding instructions and by floating point exception
284handlers with the store double floating point queue (stdfq) instruction.
286Special Registers
[f233256]289The SPARC architecture includes two special registers which are critical to the
290programming model: the Processor State Register (psr) and the Window Invalid
291Mask (wim).  The psr contains the condition codes, processor interrupt level,
292trap enable bit, supervisor mode and previous supervisor mode bits, version
293information, floating point unit and coprocessor enable bits, and the current
294window pointer (cwp).  The cwp field of the psr and wim register are used to
295manage the register windows in the SPARC architecture.  The register windows
296are discussed in more detail below.
298Register Windows
[f233256]301The SPARC architecture includes the concept of register windows.  An overly
302simplistic way to think of these windows is to imagine them as being an
303infinite supply of "fresh" register sets available for each subroutine to use.
304In reality, they are much more complicated.
306The save instruction is used to obtain a new register window.  This instruction
307decrements the current window pointer, thus providing a new set of registers
308for use.  This register set includes eight fresh local registers for use
309exclusively by this subroutine.  When done with a register set, the restore
310instruction increments the current window pointer and the previous register set
311is once again available.
313The two primary issues complicating the use of register windows are that (1)
314the set of register windows is finite, and (2) some registers are shared
315between adjacent registers windows.
317Because the set of register windows is finite, it is possible to execute enough
318save instructions without corresponding restore's to consume all of the
319register windows.  This is easily accomplished in a high level language because
320each subroutine typically performs a save instruction upon entry.  Thus having
321a subroutine call depth greater than the number of register windows will result
322in a window overflow condition.  The window overflow condition generates a trap
323which must be handled in software.  The window overflow trap handler is
324responsible for saving the contents of the oldest register window on the
325program stack.
327Similarly, the subroutines will eventually complete and begin to perform
328restore's.  If the restore results in the need for a register window which has
329previously been written to memory as part of an overflow, then a window
330underflow condition results.  Just like the window overflow, the window
331underflow condition must be handled in software by a trap handler.  The window
332underflow trap handler is responsible for reloading the contents of the
333register window requested by the restore instruction from the program stack.
335The Window Invalid Mask (wim) and the Current Window Pointer (cwp) field in the
336psr are used in conjunction to manage the finite set of register windows and
337detect the window overflow and underflow conditions.  The cwp contains the
338index of the register window currently in use.  The save instruction decrements
339the cwp modulo the number of register windows.  Similarly, the restore
340instruction increments the cwp modulo the number of register windows.  Each bit
341in the wim represents represents whether a register window contains valid
342information.  The value of 0 indicates the register window is valid and 1
343indicates it is invalid.  When a save instruction causes the cwp to point to a
344register window which is marked as invalid, a window overflow condition
345results.  Conversely, the restore instruction may result in a window underflow
348Other than the assumption that a register window is always available for trap
349(i.e. interrupt) handlers, the SPARC architecture places no limits on the
350number of register windows simultaneously marked as invalid (i.e. number of
351bits set in the wim).  However, RTEMS assumes that only one register window is
352marked invalid at a time (i.e. only one bit set in the wim).  This makes the
353maximum possible number of register windows available to the user while still
354meeting the requirement that window overflow and underflow conditions can be
357The window overflow and window underflow trap handlers are a critical part of
358the run-time environment for a SPARC application.  The SPARC architectural
359specification allows for the number of register windows to be any power of two
360less than or equal to 32.  The most common choice for SPARC implementations
361appears to be 8 register windows.  This results in the cwp ranging in value
362from 0 to 7 on most implementations.
364The second complicating factor is the sharing of registers between adjacent
365register windows.  While each register window has its own set of local
366registers, the input and output registers are shared between adjacent windows.
367The output registers for register window N are the same as the input registers
368for register window ((N - 1) modulo RW) where RW is the number of register
369windows.  An alternative way to think of this is to remember how parameters are
370passed to a subroutine on the SPARC.  The caller loads values into what are its
371output registers.  Then after the callee executes a save instruction, those
372parameters are available in its input registers.  This is a very efficient way
373to pass parameters as no data is actually moved by the save or restore
376Call and Return Mechanism
[f233256]379The SPARC architecture supports a simple yet effective call and return
380mechanism.  A subroutine is invoked via the call (call) instruction.  This
381instruction places the return address in the caller's output register 7 (o7).
382After the callee executes a save instruction, this value is available in input
383register 7 (i7) until the corresponding restore instruction is executed.
385The callee returns to the caller via a jmp to the return address.  There is a
386delay slot following this instruction which is commonly used to execute a
387restore instruction - if a register window was allocated by this subroutine.
389It is important to note that the SPARC subroutine call and return mechanism
390does not automatically save and restore any registers.  This is accomplished
391via the save and restore instructions which manage the set of registers
394In case a floating-point unit is supported, then floating-point return values
395appear in the floating-point registers.  Single-precision values occupy %f0;
396double-precision values occupy %f0 and %f1.  Otherwise, these are scratch
397registers.  Due to this the hardware and software floating-point ABIs are
400Calling Mechanism
[f233256]403All RTEMS directives are invoked using the regular SPARC calling convention via
404the call instruction.
406Register Usage
[f233256]409As discussed above, the call instruction does not automatically save any
410registers.  The save and restore instructions are used to allocate and
411deallocate register windows.  When a register window is allocated, the new set
412of local registers are available for the exclusive use of the subroutine which
413allocated this register set.
415Parameter Passing
[f233256]418RTEMS assumes that arguments are placed in the caller's output registers with
419the first argument in output register 0 (o0), the second argument in output
420register 1 (o1), and so forth.  Until the callee executes a save instruction,
421the parameters are still visible in the output registers.  After the callee
422executes a save instruction, the parameters are visible in the corresponding
423input registers.  The following pseudo-code illustrates the typical sequence
424used to call a RTEMS directive with three (3) arguments:
426.. code-block:: c
428    load third argument into o2
429    load second argument into o1
430    load first argument into o0
431    invoke directive
433User-Provided Routines
[f233256]436All user-provided routines invoked by RTEMS, such as user extensions, device
437drivers, and MPCI routines, must also adhere to these calling conventions.
439Memory Model
[f233256]442A processor may support any combination of memory models ranging from pure
443physical addressing to complex demand paged virtual memory systems.  RTEMS
444supports a flat memory model which ranges contiguously over the processor's
445allowable address space.  RTEMS does not support segmentation or virtual memory
446of any kind.  The appropriate memory model for RTEMS provided by the targeted
447processor and related characteristics of that model are described in this
450Flat Memory Model
[f233256]453The SPARC architecture supports a flat 32-bit address space with addresses
454ranging from 0x00000000 to 0xFFFFFFFF (4 gigabytes).  Each address is
455represented by a 32-bit value and is byte addressable.  The address may be used
456to reference a single byte, half-word (2-bytes), word (4 bytes), or doubleword
457(8 bytes).  Memory accesses within this address space are performed in big
458endian fashion by the SPARC.  Memory accesses which are not properly aligned
459generate a "memory address not aligned" trap (type number 7).  The following
460table lists the alignment requirements for a variety of data accesses:
[0c97890]462==============  ======================
463Data Type       Alignment Requirement
464==============  ======================
465byte            1
466half-word       2
467word            4
468doubleword      8
469==============  ======================
[f233256]471Doubleword load and store operations must use a pair of registers as their
472source or destination.  This pair of registers must be an adjacent pair of
473registers with the first of the pair being even numbered.  For example, a valid
474destination for a doubleword load might be input registers 0 and 1 (i0 and i1).
475The pair i1 and i2 would be invalid.  \[NOTE: Some assemblers for the SPARC do
476not generate an error if an odd numbered register is specified as the beginning
477register of the pair.  In this case, the assembler assumes that what the
478programmer meant was to use the even-odd pair which ends at the specified
479register.  This may or may not have been a correct assumption.]
[f233256]481RTEMS does not support any SPARC Memory Management Units, therefore, virtual
482memory or segmentation systems involving the SPARC are not supported.
484Interrupt Processing
[f233256]487Different types of processors respond to the occurrence of an interrupt in its
488own unique fashion. In addition, each processor type provides a control
489mechanism to allow for the proper handling of an interrupt.  The processor
490dependent response to the interrupt modifies the current execution state and
491results in a change in the execution stream.  Most processors require that an
492interrupt handler utilize some special control mechanisms to return to the
493normal processing stream.  Although RTEMS hides many of the processor dependent
494details of interrupt processing, it is important to understand how the RTEMS
495interrupt manager is mapped onto the processor's unique architecture. Discussed
496in this chapter are the SPARC's interrupt response and control mechanisms as
497they pertain to RTEMS.
499RTEMS and associated documentation uses the terms interrupt and vector.  In the
500SPARC architecture, these terms correspond to traps and trap type,
501respectively.  The terms will be used interchangeably in this manual.
503Synchronous Versus Asynchronous Traps
[f233256]506The SPARC architecture includes two classes of traps: synchronous and
507asynchronous.  Asynchronous traps occur when an external event interrupts the
508processor.  These traps are not associated with any instruction executed by the
509processor and logically occur between instructions.  The instruction currently
510in the execute stage of the processor is allowed to complete although
511subsequent instructions are annulled.  The return address reported by the
512processor for asynchronous traps is the pair of instructions following the
513current instruction.
515Synchronous traps are caused by the actions of an instruction.  The trap
516stimulus in this case either occurs internally to the processor or is from an
517external signal that was provoked by the instruction.  These traps are taken
518immediately and the instruction that caused the trap is aborted before any
519state changes occur in the processor itself.  The return address reported by
520the processor for synchronous traps is the instruction which caused the trap
521and the following instruction.
523Vectoring of Interrupt Handler
[f233256]526Upon receipt of an interrupt the SPARC automatically performs the following
529- disables traps (sets the ET bit of the psr to 0),
[f233256]531- the S bit of the psr is copied into the Previous Supervisor Mode (PS) bit of
532  the psr,
[f233256]534- the cwp is decremented by one (modulo the number of register windows) to
535  activate a trap window,
[f233256]537- the PC and nPC are loaded into local register 1 and 2 (l0 and l1),
[f233256]539- the trap type (tt) field of the Trap Base Register (TBR) is set to the
540  appropriate value, and
[f233256]542- if the trap is not a reset, then the PC is written with the contents of the
543  TBR and the nPC is written with TBR + 4.  If the trap is a reset, then the PC
544  is set to zero and the nPC is set to 4.
[f233256]546Trap processing on the SPARC has two features which are noticeably different
547than interrupt processing on other architectures.  First, the value of psr
548register in effect immediately before the trap occurred is not explicitly
549saved.  Instead only reversible alterations are made to it.  Second, the
550Processor Interrupt Level (pil) is not set to correspond to that of the
551interrupt being processed.  When a trap occurs, ALL subsequent traps are
552disabled.  In order to safely invoke a subroutine during trap handling, traps
553must be enabled to allow for the possibility of register window overflow and
554underflow traps.
[f233256]556If the interrupt handler was installed as an RTEMS interrupt handler, then upon
557receipt of the interrupt, the processor passes control to the RTEMS interrupt
558handler which performs the following actions:
[d389819]560- saves the state of the interrupted task on it's stack,
[f233256]562- insures that a register window is available for subsequent traps,
[f233256]564- if this is the outermost (i.e. non-nested) interrupt, then the RTEMS
565  interrupt handler switches from the current stack to the interrupt stack,
567- enables traps,
569- invokes the vectors to a user interrupt service routine (ISR).
[f233256]571Asynchronous interrupts are ignored while traps are disabled.  Synchronous
572traps which occur while traps are disabled result in the CPU being forced into
573an error mode.
[f233256]575A nested interrupt is processed similarly with the exception that the current
576stack need not be switched to the interrupt stack.
578Traps and Register Windows
[f233256]581One of the register windows must be reserved at all times for trap processing.
582This is critical to the proper operation of the trap mechanism in the SPARC
583architecture.  It is the responsibility of the trap handler to insure that
584there is a register window available for a subsequent trap before re-enabling
585traps.  It is likely that any high level language routines invoked by the trap
586handler (such as a user-provided RTEMS interrupt handler) will allocate a new
587register window.  The save operation could result in a window overflow trap.
588This trap cannot be correctly processed unless (1) traps are enabled and (2) a
589register window is reserved for traps.  Thus, the RTEMS interrupt handler
590insures that a register window is available for subsequent traps before
591enabling traps and invoking the user's interrupt handler.
593Interrupt Levels
[f233256]596Sixteen levels (0-15) of interrupt priorities are supported by the SPARC
597architecture with level fifteen (15) being the highest priority.  Level
598zero (0) indicates that interrupts are fully enabled.  Interrupt requests for
599interrupts with priorities less than or equal to the current interrupt mask
600level are ignored. Level fifteen (15) is a non-maskable interrupt (NMI), which
601makes it unsuitable for standard usage since it can affect the real-time
602behaviour by interrupting critical sections and spinlocks. Disabling traps
603stops also the NMI interrupt from happening. It can however be used for
604power-down or other critical events.
606Although RTEMS supports 256 interrupt levels, the SPARC only supports sixteen.
607RTEMS interrupt levels 0 through 15 directly correspond to SPARC processor
608interrupt levels.  All other RTEMS interrupt levels are undefined and their
609behavior is unpredictable.
611Many LEON SPARC v7/v8 systems features an extended interrupt controller which
612adds an extra step of interrupt decoding to allow handling of interrupt
61316-31. When such an extended interrupt is generated the CPU traps into a
614specific interrupt trap level 1-14 and software reads out from the interrupt
615controller which extended interrupt source actually caused the interrupt.
617Disabling of Interrupts by RTEMS
[f233256]620During the execution of directive calls, critical sections of code may be
621executed.  When these sections are encountered, RTEMS disables interrupts to
622level fifteen (15) before the execution of the section and restores them to the
623previous level upon completion of the section.  RTEMS has been optimized to
624ensure that interrupts are disabled for less than RTEMS_MAXIMUM_DISABLE_PERIOD
625microseconds on a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz ERC32 with zero wait
626states.  These numbers will vary based the number of wait states and processor
627speed present on the target board.  [NOTE: The maximum period with interrupts
628disabled is hand calculated.  This calculation was last performed for Release
[f233256]631[NOTE: It is thought that the length of time at which the processor interrupt
632level is elevated to fifteen by RTEMS is not anywhere near as long as the
633length of time ALL traps are disabled as part of the "flush all register
634windows" operation.]
636Non-maskable interrupts (NMI) cannot be disabled, and ISRs which execute at
637this level MUST NEVER issue RTEMS system calls.  If a directive is invoked,
638unpredictable results may occur due to the inability of RTEMS to protect its
639critical sections.  However, ISRs that make no system calls may safely execute
640as non-maskable interrupts.
642Interrupts are disabled or enabled by performing a system call to the Operating
643System reserved software traps 9 (SPARC_SWTRAP_IRQDIS) or 10
[135b90c]644(SPARC_SWTRAP_IRQEN). The trap is generated by the software trap (Ticc)
[f233256]645instruction or indirectly by calling sparc_disable_interrupts() or
646sparc_enable_interrupts() functions. Disabling interrupts return the previous
647interrupt level (on trap entry) in register G1 and sets PSR.PIL to 15 to
648disable all maskable interrupts. The interrupt level can be restored by
649trapping into the enable interrupt handler with G1 containing the new interrupt
652Interrupt Stack
[f233256]655The SPARC architecture does not provide for a dedicated interrupt stack.  Thus
656by default, trap handlers would execute on the stack of the RTEMS task which
657they interrupted.  This artificially inflates the stack requirements for each
658task since EVERY task stack would have to include enough space to account for
659the worst case interrupt stack requirements in addition to it's own worst case
660usage.  RTEMS addresses this problem on the SPARC by providing a dedicated
661interrupt stack managed by software.
[f233256]663During system initialization, RTEMS allocates the interrupt stack from the
664Workspace Area.  The amount of memory allocated for the interrupt stack is
665determined by the interrupt_stack_size field in the CPU Configuration Table.
666As part of processing a non-nested interrupt, RTEMS will switch to the
667interrupt stack before invoking the installed handler.
669Default Fatal Error Processing
[f233256]672Upon detection of a fatal error by either the application or RTEMS the fatal
673error manager is invoked.  The fatal error manager will invoke the
674user-supplied fatal error handlers.  If no user-supplied handlers are
675configured, the RTEMS provided default fatal error handler is invoked.  If the
676user-supplied fatal error handlers return to the executive the default fatal
677error handler is then invoked.  This chapter describes the precise operations
678of the default fatal error handler.
680Default Fatal Error Handler Operations
[f233256]683The default fatal error handler which is invoked by the fatal_error_occurred
684directive when there is no user handler configured or the user handler returns
685control to RTEMS.
[f233256]687If the BSP has been configured with ``BSP_POWER_DOWN_AT_FATAL_HALT`` set to
688true, the default handler will disable interrupts and enter power down mode. If
689power down mode is not available, it goes into an infinite loop to simulate a
690halt processor instruction.
[f233256]692If ``BSP_POWER_DOWN_AT_FATAL_HALT`` is set to false, the default handler will
693place the value ``1`` in register ``g1``, the error source in register ``g2``,
694and the error code in register``g3``. It will then generate a system error
695which will hand over control to the debugger, simulator, etc.
697Symmetric Multiprocessing
700SMP is supported.  Available platforms are the Cobham Gaisler GR712RC and
703Thread-Local Storage
706Thread-local storage is supported.
708Board Support Packages
[f233256]711An RTEMS Board Support Package (BSP) must be designed to support a particular
712processor and target board combination.  This chapter presents a discussion of
713SPARC specific BSP issues.  For more information on developing a BSP, refer to
714the chapter titled Board Support Packages in the RTEMS Applications User's
717System Reset
[f233256]720An RTEMS based application is initiated or re-initiated when the SPARC
721processor is reset.  When the SPARC is reset, the processor performs the
722following actions:
[f233256]724- the enable trap (ET) of the psr is set to 0 to disable traps,
[f233256]726- the supervisor bit (S) of the psr is set to 1 to enter supervisor mode, and
728- the PC is set 0 and the nPC is set to 4.
[f233256]730The processor then begins to execute the code at location 0.  It is important
731to note that all fields in the psr are not explicitly set by the above steps
732and all other registers retain their value from the previous execution mode.
733This is true even of the Trap Base Register (TBR) whose contents reflect the
734last trap which occurred before the reset.
736Processor Initialization
[f233256]739It is the responsibility of the application's initialization code to initialize
740the TBR and install trap handlers for at least the register window overflow and
741register window underflow conditions.  Traps should be enabled before invoking
742any subroutines to allow for register window management.  However, interrupts
743should be disabled by setting the Processor Interrupt Level (pil) field of the
744psr to 15.  RTEMS installs it's own Trap Table as part of initialization which
745is initialized with the contents of the Trap Table in place when the
746``rtems_initialize_executive`` directive was invoked.  Upon completion of
747executive initialization, interrupts are enabled.
749If this SPARC implementation supports on-chip caching and this is to be
750utilized, then it should be enabled during the reset application initialization
753In addition to the requirements described in the Board Support Packages chapter
754of the C Applications Users Manual for the reset code which is executed before
755the call to``rtems_initialize_executive``, the SPARC version has the following
[d755cbd]756specific requirements:
[f233256]758- Must leave the S bit of the status register set so that the SPARC remains in
759  the supervisor state.
[f233256]761- Must set stack pointer (sp) such that a minimum stack size of
762  MINIMUM_STACK_SIZE bytes is provided for the``rtems_initialize_executive``
763  directive.
[f233256]765- Must disable all external interrupts (i.e. set the pil to 15).
[f233256]767- Must enable traps so window overflow and underflow conditions can be properly
768  handled.
[f233256]770- Must initialize the SPARC's initial trap table with at least trap handlers
771  for register window overflow and register window underflow.
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