source: rtems-docs/cpu-supplement/sparc.rst

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[4886d60]3.. Copyright (C) 1988, 2002 On-Line Applications Research Corporation (OAR)
[d755cbd]5SPARC Specific Information
[f233256]8The Real Time Executive for Multiprocessor Systems (RTEMS) is designed to be
9portable across multiple processor architectures.  However, the nature of
10real-time systems makes it essential that the application designer understand
11certain processor dependent implementation details.  These processor
12dependencies include calling convention, board support package issues,
13interrupt processing, exact RTEMS memory requirements, performance data, header
14files, and the assembly language interface to the executive.
16This document discusses the SPARC architecture dependencies in this port of
17RTEMS.  This architectural port is for SPARC Version 7 and
[d755cbd]188. Implementations for SPARC V9 are in the sparc64 target.
[f233256]20It is highly recommended that the SPARC RTEMS application developer obtain and
21become familiar with the documentation for the processor being used as well as
22the specification for the revision of the SPARC architecture which corresponds
23to that processor.
25**SPARC Architecture Documents**
[f233256]27For information on the SPARC architecture, refer to the following documents
28available from SPARC International, Inc.  (
30- SPARC Standard Version 7.
32- SPARC Standard Version 8.
34**ERC32 Specific Information**
[d8beaab]36The European Space Agency's ERC32 is a microprocessor implementing a
[f233256]37SPARC V7 processor and associated support circuitry for embedded space
38applications. The integer and floating-point units (90C601E & 90C602E) are
39based on the Cypress 7C601 and 7C602, with additional error-detection and
40recovery functions. The memory controller (MEC) implements system support
41functions such as address decoding, memory interface, DMA interface, UARTs,
42timers, interrupt control, write-protection, memory reconfiguration and
43error-detection.  The core is designed to work at 25MHz, but using space
44qualified memories limits the system frequency to around 15 MHz, resulting in a
45performance of 10 MIPS and 2 MFLOPS.
[d8beaab]47The ERC32 is available from Atmel as the TSC695F.
[d8beaab]49The RTEMS configuration of GDB enables the SPARC Instruction Simulator (SIS)
50which can simulate the ERC32 as well as the follow up LEON2 and LEON3
53CPU Model Dependent Features
[f233256]56Microprocessors are generally classified into families with a variety of CPU
57models or implementations within that family.  Within a processor family, there
58is a high level of binary compatibility.  This family may be based on either an
59architectural specification or on maintaining compatibility with a popular
60processor.  Recent microprocessor families such as the SPARC or PowerPC are
61based on an architectural specification which is independent or any particular
62CPU model or implementation.  Older families such as the M68xxx and the iX86
63evolved as the manufacturer strived to produce higher performance processor
64models which maintained binary compatibility with older models.
66RTEMS takes advantage of the similarity of the various models within a CPU
67family.  Although the models do vary in significant ways, the high level of
68compatibility makes it possible to share the bulk of the CPU dependent
69executive code across the entire family.
71CPU Model Feature Flags
[f233256]74Each processor family supported by RTEMS has a list of features which vary
75between CPU models within a family.  For example, the most common model
76dependent feature regardless of CPU family is the presence or absence of a
77floating point unit or coprocessor.  When defining the list of features present
78on a particular CPU model, one simply notes that floating point hardware is or
79is not present and defines a single constant appropriately.  Conditional
80compilation is utilized to include the appropriate source code for this CPU
81model's feature set.  It is important to note that this means that RTEMS is
82thus compiled using the appropriate feature set and compilation flags optimal
83for this CPU model used.  The alternative would be to generate a binary which
84would execute on all family members using only the features which were always
[f233256]87This section presents the set of features which vary across SPARC
88implementations and are of importance to RTEMS.  The set of CPU model feature
89macros are defined in the file cpukit/score/cpu/sparc/sparc.h based upon the
90particular CPU model defined on the compilation command line.
92CPU Model Name
[f233256]95The macro CPU_MODEL_NAME is a string which designates the name of this CPU
96model.  For example, for the European Space Agency's ERC32 SPARC model, this
97macro is set to the string "erc32".
99Floating Point Unit
[f233256]102The macro SPARC_HAS_FPU is set to 1 to indicate that this CPU model has a
103hardware floating point unit and 0 otherwise.
105Bitscan Instruction
[f233256]108The macro SPARC_HAS_BITSCAN is set to 1 to indicate that this CPU model has the
109bitscan instruction.  For example, this instruction is supported by the Fujitsu
110SPARClite family.
112Number of Register Windows
[f233256]115The macro SPARC_NUMBER_OF_REGISTER_WINDOWS is set to indicate the number of
116register window sets implemented by this CPU model.  The SPARC architecture
117allows a for a maximum of thirty-two register window sets although most
118implementations only include eight.
120Low Power Mode
[f233256]123The macro SPARC_HAS_LOW_POWER_MODE is set to one to indicate that this CPU
124model has a low power mode.  If low power is enabled, then there must be CPU
125model specific implementation of the IDLE task in cpukit/score/cpu/sparc/cpu.c.
126The low power mode IDLE task should be of the form:
128.. code-block:: c
130    while ( TRUE ) {
[f233256]131        enter low power mode
[d755cbd]132    }
134The code required to enter low power mode is CPU model specific.
136CPU Model Implementation Notes
139The ERC32 is a custom SPARC V7 implementation based on the Cypress 601/602
140chipset.  This CPU has a number of on-board peripherals and was developed by
141the European Space Agency to target space applications.  RTEMS currently
142provides support for the following peripherals:
144- UART Channels A and B
146- General Purpose Timer
148- Real Time Clock
150- Watchdog Timer (so it can be disabled)
152- Control Register (so powerdown mode can be enabled)
154- Memory Control Register
156- Interrupt Control
158The General Purpose Timer and Real Time Clock Timer provided with the ERC32
159share the Timer Control Register.  Because the Timer Control Register is write
160only, we must mirror it in software and insure that writes to one timer do not
161alter the current settings and status of the other timer.  Routines are
162provided in erc32.h which promote the view that the two timers are completely
163independent.  By exclusively using these routines to access the Timer Control
[f233256]164Register, the application can view the system as having a General Purpose Timer
165Control Register and a Real Time Clock Timer Control Register rather than the
166single shared value.
168The RTEMS Idle thread take advantage of the low power mode provided by the
169ERC32.  Low power mode is entered during idle loops and is enabled at
170initialization time.
172Calling Conventions
175Each high-level language compiler generates subroutine entry and exit code
176based upon a set of rules known as the application binary interface (ABI)
[f233256]177calling convention.  These rules address the following issues:
179- register preservation and usage
181- parameter passing
183- call and return mechanism
185An ABI calling convention is of importance when interfacing to subroutines
186written in another language either assembly or high-level.  It determines also
187the set of registers to be saved or restored during a context switch and
188interrupt processing.
190The ABI relevant for RTEMS on SPARC is defined by SYSTEM V APPLICATION BINARY
191INTERFACE, SPARC Processor Supplement, Third Edition.
193Programming Model
[f233256]196This section discusses the programming model for the SPARC architecture.
198Non-Floating Point Registers
[f233256]201The SPARC architecture defines thirty-two non-floating point registers directly
202visible to the programmer.  These are divided into four sets:
204- input registers
206- local registers
208- output registers
210- global registers
[f233256]212Each register is referred to by either two or three names in the SPARC
213reference manuals.  First, the registers are referred to as r0 through r31 or
214with the alternate notation r[0] through r[31].  Second, each register is a
215member of one of the four sets listed above.  Finally, some registers have an
216architecturally defined role in the programming model which provides an
217alternate name.  The following table describes the mapping between the 32
218registers and the register sets:
[0c97890]220================ ================ ===================
221Register Number  Register Names   Description
222================ ================ ===================
2230 - 7            g0 - g7          Global Registers
2248 - 15           o0 - o7          Output Registers
22516 - 23          l0 - l7          Local Registers
22624 - 31          i0 - i7          Input Registers
227================ ================ ===================
229As mentioned above, some of the registers serve defined roles in the
230programming model.  The following table describes the role of each of these
[0c97890]233============== ================ ==================================
234Register Name  Alternate Name   Description
235============== ================ ==================================
236g0             na               reads return 0, writes are ignored
237o6             sp               stack pointer
238i6             fp               frame pointer
239i7             na               return address
240============== ================ ==================================
242The registers g2 through g4 are reserved for applications.  GCC uses them as
243volatile registers by default.  So they are treated like volatile registers in
244RTEMS as well.
246The register g6 is reserved for the operating system and contains the address
247of the per-CPU control block of the current processor.  This register is
248initialized during system start and then remains unchanged.  It is not
249saved/restored by the context switch or interrupt processing code.
251The register g7 is reserved for the operating system and contains the thread
252pointer used for thread-local storage (TLS) as mandated by the SPARC ABI.
254Floating Point Registers
[f233256]257The SPARC V7 architecture includes thirty-two, thirty-two bit registers.  These
258registers may be viewed as follows:
[f233256]260- 32 single precision floating point or integer registers (f0, f1, ... f31)
[f233256]262- 16 double precision floating point registers (f0, f2, f4, ... f30)
[f233256]264- 8 extended precision floating point registers (f0, f4, f8, ... f28)
[f233256]266The floating point status register (FSR) specifies the behavior of the floating
267point unit for rounding, contains its condition codes, version specification,
268and trap information.
270According to the ABI all floating point registers and the floating point status
[f233256]271register (FSR) are volatile.  Thus the floating point context of a thread is
272the empty set.  The rounding direction is a system global state and must not be
[d755cbd]273modified by threads.
[f233256]275A queue of the floating point instructions which have started execution but not
276yet completed is maintained.  This queue is needed to support the multiple
277cycle nature of floating point operations and to aid floating point exception
278trap handlers.  Once a floating point exception has been encountered, the queue
279is frozen until it is emptied by the trap handler.  The floating point queue is
280loaded by launching instructions.  It is emptied normally when the floating
281point completes all outstanding instructions and by floating point exception
282handlers with the store double floating point queue (stdfq) instruction.
284Special Registers
[f233256]287The SPARC architecture includes two special registers which are critical to the
288programming model: the Processor State Register (psr) and the Window Invalid
289Mask (wim).  The psr contains the condition codes, processor interrupt level,
290trap enable bit, supervisor mode and previous supervisor mode bits, version
291information, floating point unit and coprocessor enable bits, and the current
292window pointer (cwp).  The cwp field of the psr and wim register are used to
293manage the register windows in the SPARC architecture.  The register windows
294are discussed in more detail below.
296Register Windows
[f233256]299The SPARC architecture includes the concept of register windows.  An overly
300simplistic way to think of these windows is to imagine them as being an
301infinite supply of "fresh" register sets available for each subroutine to use.
302In reality, they are much more complicated.
304The save instruction is used to obtain a new register window.  This instruction
305decrements the current window pointer, thus providing a new set of registers
306for use.  This register set includes eight fresh local registers for use
307exclusively by this subroutine.  When done with a register set, the restore
308instruction increments the current window pointer and the previous register set
309is once again available.
311The two primary issues complicating the use of register windows are that (1)
312the set of register windows is finite, and (2) some registers are shared
313between adjacent registers windows.
315Because the set of register windows is finite, it is possible to execute enough
316save instructions without corresponding restore's to consume all of the
317register windows.  This is easily accomplished in a high level language because
318each subroutine typically performs a save instruction upon entry.  Thus having
319a subroutine call depth greater than the number of register windows will result
320in a window overflow condition.  The window overflow condition generates a trap
321which must be handled in software.  The window overflow trap handler is
322responsible for saving the contents of the oldest register window on the
323program stack.
325Similarly, the subroutines will eventually complete and begin to perform
326restore's.  If the restore results in the need for a register window which has
327previously been written to memory as part of an overflow, then a window
328underflow condition results.  Just like the window overflow, the window
329underflow condition must be handled in software by a trap handler.  The window
330underflow trap handler is responsible for reloading the contents of the
331register window requested by the restore instruction from the program stack.
333The Window Invalid Mask (wim) and the Current Window Pointer (cwp) field in the
334psr are used in conjunction to manage the finite set of register windows and
335detect the window overflow and underflow conditions.  The cwp contains the
336index of the register window currently in use.  The save instruction decrements
337the cwp modulo the number of register windows.  Similarly, the restore
338instruction increments the cwp modulo the number of register windows.  Each bit
339in the wim represents represents whether a register window contains valid
340information.  The value of 0 indicates the register window is valid and 1
341indicates it is invalid.  When a save instruction causes the cwp to point to a
342register window which is marked as invalid, a window overflow condition
343results.  Conversely, the restore instruction may result in a window underflow
346Other than the assumption that a register window is always available for trap
347(i.e. interrupt) handlers, the SPARC architecture places no limits on the
348number of register windows simultaneously marked as invalid (i.e. number of
349bits set in the wim).  However, RTEMS assumes that only one register window is
350marked invalid at a time (i.e. only one bit set in the wim).  This makes the
351maximum possible number of register windows available to the user while still
352meeting the requirement that window overflow and underflow conditions can be
355The window overflow and window underflow trap handlers are a critical part of
356the run-time environment for a SPARC application.  The SPARC architectural
357specification allows for the number of register windows to be any power of two
358less than or equal to 32.  The most common choice for SPARC implementations
359appears to be 8 register windows.  This results in the cwp ranging in value
360from 0 to 7 on most implementations.
362The second complicating factor is the sharing of registers between adjacent
363register windows.  While each register window has its own set of local
364registers, the input and output registers are shared between adjacent windows.
365The output registers for register window N are the same as the input registers
366for register window ((N - 1) modulo RW) where RW is the number of register
367windows.  An alternative way to think of this is to remember how parameters are
368passed to a subroutine on the SPARC.  The caller loads values into what are its
369output registers.  Then after the callee executes a save instruction, those
370parameters are available in its input registers.  This is a very efficient way
371to pass parameters as no data is actually moved by the save or restore
374Call and Return Mechanism
[f233256]377The SPARC architecture supports a simple yet effective call and return
378mechanism.  A subroutine is invoked via the call (call) instruction.  This
379instruction places the return address in the caller's output register 7 (o7).
380After the callee executes a save instruction, this value is available in input
381register 7 (i7) until the corresponding restore instruction is executed.
383The callee returns to the caller via a jmp to the return address.  There is a
384delay slot following this instruction which is commonly used to execute a
385restore instruction - if a register window was allocated by this subroutine.
387It is important to note that the SPARC subroutine call and return mechanism
388does not automatically save and restore any registers.  This is accomplished
389via the save and restore instructions which manage the set of registers
392In case a floating-point unit is supported, then floating-point return values
393appear in the floating-point registers.  Single-precision values occupy %f0;
394double-precision values occupy %f0 and %f1.  Otherwise, these are scratch
395registers.  Due to this the hardware and software floating-point ABIs are
398Calling Mechanism
[f233256]401All RTEMS directives are invoked using the regular SPARC calling convention via
402the call instruction.
404Register Usage
[f233256]407As discussed above, the call instruction does not automatically save any
408registers.  The save and restore instructions are used to allocate and
409deallocate register windows.  When a register window is allocated, the new set
410of local registers are available for the exclusive use of the subroutine which
411allocated this register set.
413Parameter Passing
[f233256]416RTEMS assumes that arguments are placed in the caller's output registers with
417the first argument in output register 0 (o0), the second argument in output
418register 1 (o1), and so forth.  Until the callee executes a save instruction,
419the parameters are still visible in the output registers.  After the callee
420executes a save instruction, the parameters are visible in the corresponding
421input registers.  The following pseudo-code illustrates the typical sequence
422used to call a RTEMS directive with three (3) arguments:
424.. code-block:: c
426    load third argument into o2
427    load second argument into o1
428    load first argument into o0
429    invoke directive
431User-Provided Routines
[f233256]434All user-provided routines invoked by RTEMS, such as user extensions, device
435drivers, and MPCI routines, must also adhere to these calling conventions.
439.. sidebar:: *Origin*
441  This SPARC Annul Slot section was originally an email from Jiri Gaisler
442  to Joel Sherrill that explained why sometimes, a single instruction
443  will not be executed, due to the Annul Slot feature.
445In SPARC, the default behaviour is to execute instructions after a branch.
446As with the behaviour of most RISC (Reduced Instruction Set Computer)
447machines, SPARC uses a branch delay slot. This is because completing
448an instruction every clock cycle introduces the problem that a branch
449may not be resolved until the instruction has passed through the
450pipeline. By inserting stalls, this is prevented. In each cycle, if a
451stall is inserted, it is considered one branch delay slot.
453For example, a regular branch instruction might look like so:
455.. code-block:: assembly
457        cmp %o4, %g4    /* if %o4 is equals to %g4 */
458        be 200fd06      /* then branch */
459        mov [%g4], %o4  /* instructions after the branch, this is a */
460                        /* branch delay slot it is executed regardless */
461                        /* of whether %o4 is equals to %g4 */
463However, if marked with "``,a``", the instructions after the branch will
464only be executed if the branch is taken.  In other words, only if the
465condition before is true, then it would be executed. Otherwise if would be
468.. code-block:: assembly
470        cmp %o4, %g4    /* if %o4 is equals to %g4 */
471        be,a 200fd06    /* then branch */
472        mov [%g4], %o4  /* instruction after the branch */
475The ``mov`` instruction is in a branch delay slot and is only executed
476if the branch is taken (e.g. if %o4 is equals to %g4).
478This shows up in analysis of coverage reports when a single instruction
479is marked unexecuted when the instruction above and below it are executed.
[d755cbd]482Memory Model
[f233256]485A processor may support any combination of memory models ranging from pure
486physical addressing to complex demand paged virtual memory systems.  RTEMS
487supports a flat memory model which ranges contiguously over the processor's
488allowable address space.  RTEMS does not support segmentation or virtual memory
489of any kind.  The appropriate memory model for RTEMS provided by the targeted
490processor and related characteristics of that model are described in this
493Flat Memory Model
[f233256]496The SPARC architecture supports a flat 32-bit address space with addresses
497ranging from 0x00000000 to 0xFFFFFFFF (4 gigabytes).  Each address is
498represented by a 32-bit value and is byte addressable.  The address may be used
499to reference a single byte, half-word (2-bytes), word (4 bytes), or doubleword
500(8 bytes).  Memory accesses within this address space are performed in big
501endian fashion by the SPARC.  Memory accesses which are not properly aligned
502generate a "memory address not aligned" trap (type number 7).  The following
503table lists the alignment requirements for a variety of data accesses:
[0c97890]505==============  ======================
506Data Type       Alignment Requirement
507==============  ======================
508byte            1
509half-word       2
510word            4
511doubleword      8
512==============  ======================
[f233256]514Doubleword load and store operations must use a pair of registers as their
515source or destination.  This pair of registers must be an adjacent pair of
516registers with the first of the pair being even numbered.  For example, a valid
517destination for a doubleword load might be input registers 0 and 1 (i0 and i1).
518The pair i1 and i2 would be invalid.  \[NOTE: Some assemblers for the SPARC do
519not generate an error if an odd numbered register is specified as the beginning
520register of the pair.  In this case, the assembler assumes that what the
521programmer meant was to use the even-odd pair which ends at the specified
522register.  This may or may not have been a correct assumption.]
[f233256]524RTEMS does not support any SPARC Memory Management Units, therefore, virtual
525memory or segmentation systems involving the SPARC are not supported.
527Interrupt Processing
[f233256]530Different types of processors respond to the occurrence of an interrupt in its
531own unique fashion. In addition, each processor type provides a control
532mechanism to allow for the proper handling of an interrupt.  The processor
533dependent response to the interrupt modifies the current execution state and
534results in a change in the execution stream.  Most processors require that an
535interrupt handler utilize some special control mechanisms to return to the
536normal processing stream.  Although RTEMS hides many of the processor dependent
537details of interrupt processing, it is important to understand how the RTEMS
538interrupt manager is mapped onto the processor's unique architecture. Discussed
539in this chapter are the SPARC's interrupt response and control mechanisms as
540they pertain to RTEMS.
542RTEMS and associated documentation uses the terms interrupt and vector.  In the
543SPARC architecture, these terms correspond to traps and trap type,
544respectively.  The terms will be used interchangeably in this manual.
546Synchronous Versus Asynchronous Traps
[f233256]549The SPARC architecture includes two classes of traps: synchronous and
550asynchronous.  Asynchronous traps occur when an external event interrupts the
551processor.  These traps are not associated with any instruction executed by the
552processor and logically occur between instructions.  The instruction currently
553in the execute stage of the processor is allowed to complete although
554subsequent instructions are annulled.  The return address reported by the
555processor for asynchronous traps is the pair of instructions following the
556current instruction.
558Synchronous traps are caused by the actions of an instruction.  The trap
559stimulus in this case either occurs internally to the processor or is from an
560external signal that was provoked by the instruction.  These traps are taken
561immediately and the instruction that caused the trap is aborted before any
562state changes occur in the processor itself.  The return address reported by
563the processor for synchronous traps is the instruction which caused the trap
564and the following instruction.
566Vectoring of Interrupt Handler
[f233256]569Upon receipt of an interrupt the SPARC automatically performs the following
572- disables traps (sets the ET bit of the psr to 0),
[f233256]574- the S bit of the psr is copied into the Previous Supervisor Mode (PS) bit of
575  the psr,
[f233256]577- the cwp is decremented by one (modulo the number of register windows) to
578  activate a trap window,
[f233256]580- the PC and nPC are loaded into local register 1 and 2 (l0 and l1),
[f233256]582- the trap type (tt) field of the Trap Base Register (TBR) is set to the
583  appropriate value, and
[f233256]585- if the trap is not a reset, then the PC is written with the contents of the
586  TBR and the nPC is written with TBR + 4.  If the trap is a reset, then the PC
587  is set to zero and the nPC is set to 4.
[f233256]589Trap processing on the SPARC has two features which are noticeably different
590than interrupt processing on other architectures.  First, the value of psr
591register in effect immediately before the trap occurred is not explicitly
592saved.  Instead only reversible alterations are made to it.  Second, the
593Processor Interrupt Level (pil) is not set to correspond to that of the
594interrupt being processed.  When a trap occurs, ALL subsequent traps are
595disabled.  In order to safely invoke a subroutine during trap handling, traps
596must be enabled to allow for the possibility of register window overflow and
597underflow traps.
[f233256]599If the interrupt handler was installed as an RTEMS interrupt handler, then upon
600receipt of the interrupt, the processor passes control to the RTEMS interrupt
601handler which performs the following actions:
[d389819]603- saves the state of the interrupted task on it's stack,
[f233256]605- insures that a register window is available for subsequent traps,
[f233256]607- if this is the outermost (i.e. non-nested) interrupt, then the RTEMS
608  interrupt handler switches from the current stack to the interrupt stack,
610- enables traps,
612- invokes the vectors to a user interrupt service routine (ISR).
[f233256]614Asynchronous interrupts are ignored while traps are disabled.  Synchronous
615traps which occur while traps are disabled result in the CPU being forced into
616an error mode.
[f233256]618A nested interrupt is processed similarly with the exception that the current
619stack need not be switched to the interrupt stack.
621Traps and Register Windows
[f233256]624One of the register windows must be reserved at all times for trap processing.
625This is critical to the proper operation of the trap mechanism in the SPARC
626architecture.  It is the responsibility of the trap handler to insure that
627there is a register window available for a subsequent trap before re-enabling
628traps.  It is likely that any high level language routines invoked by the trap
629handler (such as a user-provided RTEMS interrupt handler) will allocate a new
630register window.  The save operation could result in a window overflow trap.
631This trap cannot be correctly processed unless (1) traps are enabled and (2) a
632register window is reserved for traps.  Thus, the RTEMS interrupt handler
633insures that a register window is available for subsequent traps before
634enabling traps and invoking the user's interrupt handler.
636Interrupt Levels
[f233256]639Sixteen levels (0-15) of interrupt priorities are supported by the SPARC
640architecture with level fifteen (15) being the highest priority.  Level
641zero (0) indicates that interrupts are fully enabled.  Interrupt requests for
642interrupts with priorities less than or equal to the current interrupt mask
643level are ignored. Level fifteen (15) is a non-maskable interrupt (NMI), which
644makes it unsuitable for standard usage since it can affect the real-time
645behaviour by interrupting critical sections and spinlocks. Disabling traps
646stops also the NMI interrupt from happening. It can however be used for
647power-down or other critical events.
649Although RTEMS supports 256 interrupt levels, the SPARC only supports sixteen.
650RTEMS interrupt levels 0 through 15 directly correspond to SPARC processor
651interrupt levels.  All other RTEMS interrupt levels are undefined and their
652behavior is unpredictable.
654Many LEON SPARC v7/v8 systems features an extended interrupt controller which
655adds an extra step of interrupt decoding to allow handling of interrupt
65616-31. When such an extended interrupt is generated the CPU traps into a
657specific interrupt trap level 1-14 and software reads out from the interrupt
658controller which extended interrupt source actually caused the interrupt.
660Disabling of Interrupts by RTEMS
[f233256]663During the execution of directive calls, critical sections of code may be
664executed.  When these sections are encountered, RTEMS disables interrupts to
665level fifteen (15) before the execution of the section and restores them to the
666previous level upon completion of the section.  RTEMS has been optimized to
667ensure that interrupts are disabled for less than RTEMS_MAXIMUM_DISABLE_PERIOD
668microseconds on a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz ERC32 with zero wait
669states.  These numbers will vary based the number of wait states and processor
670speed present on the target board.  [NOTE: The maximum period with interrupts
671disabled is hand calculated.  This calculation was last performed for Release
[f233256]674[NOTE: It is thought that the length of time at which the processor interrupt
675level is elevated to fifteen by RTEMS is not anywhere near as long as the
676length of time ALL traps are disabled as part of the "flush all register
677windows" operation.]
679Non-maskable interrupts (NMI) cannot be disabled, and ISRs which execute at
680this level MUST NEVER issue RTEMS system calls.  If a directive is invoked,
681unpredictable results may occur due to the inability of RTEMS to protect its
682critical sections.  However, ISRs that make no system calls may safely execute
683as non-maskable interrupts.
685Interrupts are disabled or enabled by performing a system call to the Operating
686System reserved software traps 9 (SPARC_SWTRAP_IRQDIS) or 10
[135b90c]687(SPARC_SWTRAP_IRQEN). The trap is generated by the software trap (Ticc)
[f233256]688instruction or indirectly by calling sparc_disable_interrupts() or
689sparc_enable_interrupts() functions. Disabling interrupts return the previous
690interrupt level (on trap entry) in register G1 and sets PSR.PIL to 15 to
691disable all maskable interrupts. The interrupt level can be restored by
692trapping into the enable interrupt handler with G1 containing the new interrupt
695Interrupt Stack
[f233256]698The SPARC architecture does not provide for a dedicated interrupt stack.  Thus
699by default, trap handlers would execute on the stack of the RTEMS task which
700they interrupted.  This artificially inflates the stack requirements for each
701task since EVERY task stack would have to include enough space to account for
702the worst case interrupt stack requirements in addition to it's own worst case
703usage.  RTEMS addresses this problem on the SPARC by providing a dedicated
704interrupt stack managed by software.
[f233256]706During system initialization, RTEMS allocates the interrupt stack from the
707Workspace Area.  The amount of memory allocated for the interrupt stack is
708determined by the interrupt_stack_size field in the CPU Configuration Table.
709As part of processing a non-nested interrupt, RTEMS will switch to the
710interrupt stack before invoking the installed handler.
712Default Fatal Error Processing
[f233256]715Upon detection of a fatal error by either the application or RTEMS the fatal
716error manager is invoked.  The fatal error manager will invoke the
717user-supplied fatal error handlers.  If no user-supplied handlers are
718configured, the RTEMS provided default fatal error handler is invoked.  If the
719user-supplied fatal error handlers return to the executive the default fatal
720error handler is then invoked.  This chapter describes the precise operations
721of the default fatal error handler.
723Default Fatal Error Handler Operations
[f233256]726The default fatal error handler which is invoked by the fatal_error_occurred
727directive when there is no user handler configured or the user handler returns
728control to RTEMS.
[f233256]730If the BSP has been configured with ``BSP_POWER_DOWN_AT_FATAL_HALT`` set to
731true, the default handler will disable interrupts and enter power down mode. If
732power down mode is not available, it goes into an infinite loop to simulate a
733halt processor instruction.
[f233256]735If ``BSP_POWER_DOWN_AT_FATAL_HALT`` is set to false, the default handler will
736place the value ``1`` in register ``g1``, the error source in register ``g2``,
737and the error code in register``g3``. It will then generate a system error
738which will hand over control to the debugger, simulator, etc.
740Symmetric Multiprocessing
743SMP is supported.  Available platforms are the Cobham Gaisler GR712RC and
746Thread-Local Storage
749Thread-local storage is supported.
751Board Support Packages
[f233256]754An RTEMS Board Support Package (BSP) must be designed to support a particular
755processor and target board combination.  This chapter presents a discussion of
756SPARC specific BSP issues.  For more information on developing a BSP, refer to
757the chapter titled Board Support Packages in the RTEMS Applications User's
760System Reset
[f233256]763An RTEMS based application is initiated or re-initiated when the SPARC
764processor is reset.  When the SPARC is reset, the processor performs the
765following actions:
[f233256]767- the enable trap (ET) of the psr is set to 0 to disable traps,
[f233256]769- the supervisor bit (S) of the psr is set to 1 to enter supervisor mode, and
771- the PC is set 0 and the nPC is set to 4.
[f233256]773The processor then begins to execute the code at location 0.  It is important
774to note that all fields in the psr are not explicitly set by the above steps
775and all other registers retain their value from the previous execution mode.
776This is true even of the Trap Base Register (TBR) whose contents reflect the
777last trap which occurred before the reset.
779Processor Initialization
[f233256]782It is the responsibility of the application's initialization code to initialize
783the TBR and install trap handlers for at least the register window overflow and
784register window underflow conditions.  Traps should be enabled before invoking
785any subroutines to allow for register window management.  However, interrupts
786should be disabled by setting the Processor Interrupt Level (pil) field of the
787psr to 15.  RTEMS installs it's own Trap Table as part of initialization which
788is initialized with the contents of the Trap Table in place when the
789``rtems_initialize_executive`` directive was invoked.  Upon completion of
790executive initialization, interrupts are enabled.
792If this SPARC implementation supports on-chip caching and this is to be
793utilized, then it should be enabled during the reset application initialization
796In addition to the requirements described in the Board Support Packages chapter
797of the C Applications Users Manual for the reset code which is executed before
798the call to``rtems_initialize_executive``, the SPARC version has the following
[d755cbd]799specific requirements:
[f233256]801- Must leave the S bit of the status register set so that the SPARC remains in
802  the supervisor state.
[f233256]804- Must set stack pointer (sp) such that a minimum stack size of
805  MINIMUM_STACK_SIZE bytes is provided for the``rtems_initialize_executive``
806  directive.
[f233256]808- Must disable all external interrupts (i.e. set the pil to 15).
[f233256]810- Must enable traps so window overflow and underflow conditions can be properly
811  handled.
[f233256]813- Must initialize the SPARC's initial trap table with at least trap handlers
814  for register window overflow and register window underflow.
816.. COMMENT: Include SPARC v8 Register Windows Explanation
817.. COMMENT: Keep separate until completely formatted, maybe forever
818.. include:: sparc_v8_stacks_regwin.rst
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