1 | .. comment SPDX-License-Identifier: CC-BY-SA-4.0 |
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2 | |
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3 | .. COMMENT: Copyright (c) 2018 |
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4 | .. COMMENT: embedded brains GmbH |
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5 | .. COMMENT: All rights reserved. |
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6 | |
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7 | RISC-V Specific Information |
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8 | *************************** |
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9 | |
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10 | Calling Conventions |
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11 | =================== |
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12 | |
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13 | Please refer to the |
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14 | `RISC-V ELF psABI specification <https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md>`_. |
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15 | |
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16 | Multilibs |
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17 | ========= |
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18 | |
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19 | The GCC for RISC-V can generate code for several 32-bit and 64-bit ISA/ABI |
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20 | variants. The following multilibs are available: |
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21 | |
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22 | * ``.``: The default multilib ISA is RV32IMAFDC with ABI ILP32D. |
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23 | |
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24 | * ``rv32i/ilp32``: ISA RV32I with ABI ILP32. |
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25 | |
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26 | * ``rv32im/ilp32``: ISA RV32IM with ABI ILP32. |
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27 | |
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28 | * ``rv32imafd/ilp32d``: ISA RV32IMAFD with ABI ILP32D. |
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29 | |
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30 | * ``rv32iac/ilp32``: ISA RV32IAC with ABI ILP32. |
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31 | |
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32 | * ``rv32imac/ilp32``: ISA RV32IMAC with ABI ILP32. |
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33 | |
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34 | * ``rv32imafc/ilp32f``: ISA RV32IMAFC with ABI ILP32F. |
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35 | |
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36 | * ``rv64imafd/lp64d``: ISA RV64IMAFD with ABI LP64D and code model medlow. |
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37 | |
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38 | * ``rv64imafd/lp64d/medany``: ISA RV64IMAFD with ABI LP64D and code model medany. |
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39 | |
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40 | * ``rv64imac/lp64``: ISA RV64IMAC with ABI LP64 and code model medlow. |
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41 | |
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42 | * ``rv64imac/lp64/medany``: ISA RV64IMAC with ABI LP64 and code model medany. |
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43 | |
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44 | * ``rv64imafdc/lp64d``: ISA RV64IMAFDC with ABI LP64D and code model medlow. |
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45 | |
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46 | * ``rv64imafdc/lp64d/medany``: ISA RV64IMAFDC with ABI LP64D and code model medany. |
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47 | |
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48 | Interrupt Processing |
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49 | ==================== |
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50 | |
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51 | Interrupt exceptions are handled via the interrupt extensions API. All other |
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52 | exceptions end up in a fatal error (RTEMS_FATAL_SOURCE_EXCEPTION). |
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53 | |
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54 | Interrupt Levels |
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55 | ---------------- |
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56 | |
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57 | There are exactly two interrupt levels on RISC-V with respect to RTEMS. Level |
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58 | zero corresponds to machine interrupts enabled. Level one corresponds to |
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59 | machine interrupts disabled. |
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60 | |
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61 | Interrupt Stack |
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62 | --------------- |
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63 | |
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64 | The memory region for the interrupt stack is defined by the BSP. |
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65 | |
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66 | Default Fatal Error Processing |
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67 | ============================== |
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68 | |
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69 | The default fatal error is BSP-specific. |
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70 | |
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71 | Symmetric Multiprocessing |
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72 | ========================= |
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73 | |
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74 | SMP is supported. |
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75 | |
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76 | Thread-Local Storage |
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77 | ==================== |
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78 | |
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79 | Thread-local storage is supported. |
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