source: rtems-docs/cpu-supplement/riscv.rst @ f067ba3

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Last change on this file since f067ba3 was d909c5f, checked in by Sebastian Huber <sebastian.huber@…>, on Aug 2, 2018 at 10:53:14 AM

cpu-supplement: Add RISC-V chapter

Update #3433.

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[d909c5f]1.. comment SPDX-License-Identifier: CC-BY-SA-4.0
2
3.. COMMENT: Copyright (c) 2018
4.. COMMENT: embedded brains GmbH
5.. COMMENT: All rights reserved.
6
7RISC-V Specific Information
8***************************
9
10Calling Conventions
11===================
12
13Please refer to the
14`RISC-V ELF psABI specification <https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md>`_.
15
16Multilibs
17=========
18
19The GCC for RISC-V can generate code for several 32-bit and 64-bit ISA/ABI
20variants.  The following multilibs are available:
21
22* ``.``: The default multilib ISA is RV32IMAFDC with ABI ILP32D.
23
24* ``rv32i/ilp32``: ISA RV32I with ABI ILP32.
25
26* ``rv32im/ilp32``: ISA RV32IM with ABI ILP32.
27
28* ``rv32imafd/ilp32d``: ISA RV32IMAFD with ABI ILP32D.
29
30* ``rv32iac/ilp32``: ISA RV32IAC with ABI ILP32.
31
32* ``rv32imac/ilp32``: ISA RV32IMAC with ABI ILP32.
33
34* ``rv32imafc/ilp32f``: ISA RV32IMAFC with ABI ILP32F.
35
36* ``rv64imafd/lp64d``: ISA RV64IMAFD with ABI LP64D and code model medlow.
37
38* ``rv64imafd/lp64d/medany``: ISA RV64IMAFD with ABI LP64D and code model medany.
39
40* ``rv64imac/lp64``: ISA RV64IMAC with ABI LP64 and code model medlow.
41
42* ``rv64imac/lp64/medany``: ISA RV64IMAC with ABI LP64 and code model medany.
43
44* ``rv64imafdc/lp64d``: ISA RV64IMAFDC with ABI LP64D and code model medlow.
45
46* ``rv64imafdc/lp64d/medany``: ISA RV64IMAFDC with ABI LP64D and code model medany.
47
48Interrupt Processing
49====================
50
51Interrupt exceptions are handled via the interrupt extensions API.  All other
52exceptions end up in a fatal error (RTEMS_FATAL_SOURCE_EXCEPTION).
53
54Interrupt Levels
55----------------
56
57There are exactly two interrupt levels on RISC-V with respect to RTEMS.  Level
58zero corresponds to machine interrupts enabled.  Level one corresponds to
59machine interrupts disabled.
60
61Interrupt Stack
62---------------
63
64The memory region for the interrupt stack is defined by the BSP.
65
66Default Fatal Error Processing
67==============================
68
69The default fatal error is BSP-specific.
70
71Symmetric Multiprocessing
72=========================
73
74SMP is supported.
75
76Thread-Local Storage
77====================
78
79Thread-local storage is supported.
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