1 | .. comment SPDX-License-Identifier: CC-BY-SA-4.0 |
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2 | |
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3 | .. COMMENT: COPYRIGHT (c) 1988-2002. |
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4 | .. COMMENT: On-Line Applications Research Corporation (OAR). |
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5 | .. COMMENT: All rights reserved. |
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6 | |
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7 | PowerPC Specific Information |
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8 | **************************** |
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9 | |
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10 | This chapter discusses the PowerPC architecture dependencies in this port of |
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11 | RTEMS. The PowerPC family has a wide variety of implementations by a range of |
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12 | vendors. Consequently, there are many, many CPU models within it. |
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13 | |
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14 | It is highly recommended that the PowerPC RTEMS application developer obtain |
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15 | and become familiar with the documentation for the processor being used as well |
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16 | as the specification for the revision of the PowerPC architecture which |
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17 | corresponds to that processor. |
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18 | |
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19 | **PowerPC Architecture Documents** |
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20 | |
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21 | For information on the PowerPC architecture, refer to the following documents |
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22 | available from Motorola and IBM: |
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23 | |
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24 | - *PowerPC Microprocessor Family: The Programming Environment* |
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25 | (Motorola Document MPRPPCFPE-01). |
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26 | |
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27 | - *IBM PPC403GB Embedded Controller User's Manual*. |
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28 | |
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29 | - *PoweRisControl MPC500 Family RCPU RISC Central Processing |
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30 | Unit Reference Manual* (Motorola Document RCPUURM/AD). |
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31 | |
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32 | - *PowerPC 601 RISC Microprocessor User's Manual* |
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33 | (Motorola Document MPR601UM/AD). |
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34 | |
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35 | - *PowerPC 603 RISC Microprocessor User's Manual* |
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36 | (Motorola Document MPR603UM/AD). |
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37 | |
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38 | - *PowerPC 603e RISC Microprocessor User's Manual* |
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39 | (Motorola Document MPR603EUM/AD). |
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40 | |
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41 | - *PowerPC 604 RISC Microprocessor User's Manual* |
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42 | (Motorola Document MPR604UM/AD). |
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43 | |
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44 | - *PowerPC MPC821 Portable Systems Microprocessor User's Manual* |
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45 | (Motorola Document MPC821UM/AD). |
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46 | |
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47 | - *PowerQUICC MPC860 User's Manual* |
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48 | (Motorola Document MPC860UM/AD). |
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49 | |
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50 | Motorola maintains an on-line electronic library for the PowerPC at the |
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51 | following URL: |
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52 | |
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53 | - http://www.mot.com/powerpc/library/library.html |
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54 | |
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55 | This site has a a wealth of information and examples. Many of the manuals are |
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56 | available from that site in electronic format. |
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57 | |
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58 | **PowerPC Processor Simulator Information** |
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59 | |
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60 | PSIM is a program which emulates the Instruction Set Architecture of the |
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61 | PowerPC microprocessor family. It is reely available in source code form under |
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62 | the terms of the GNU General Public License (version 2 or later). PSIM can be |
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63 | integrated with the GNU Debugger (gdb) to execute and debug PowerPC executables |
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64 | on non-PowerPC hosts. PSIM supports the addition of user provided device |
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65 | models which can be used to allow one to develop and debug embedded |
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66 | applications using the simulator. |
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67 | |
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68 | The latest version of PSIM is included in GDB and enabled on pre-built binaries |
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69 | provided by the RTEMS Project. |
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70 | |
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71 | CPU Model Dependent Features |
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72 | ============================ |
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73 | |
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74 | This section presents the set of features which vary across PowerPC |
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75 | implementations and are of importance to RTEMS. The set of CPU model feature |
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76 | macros are defined in the file ``cpukit/score/cpu/powerpc/powerpc.h`` based |
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77 | upon the particular CPU model specified on the compilation command line. |
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78 | |
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79 | Alignment |
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80 | --------- |
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81 | |
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82 | The macro PPC_ALIGNMENT is set to the PowerPC model's worst case alignment |
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83 | requirement for data types on a byte boundary. This value is used to derive |
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84 | the alignment restrictions for memory allocated from regions and partitions. |
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85 | |
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86 | Cache Alignment |
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87 | --------------- |
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88 | |
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89 | The macro PPC_CACHE_ALIGNMENT is set to the line size of the cache. It is used |
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90 | to align the entry point of critical routines so that as much code as possible |
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91 | can be retrieved with the initial read into cache. This is done for the |
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92 | interrupt handler as well as the context switch routines. |
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93 | |
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94 | In addition, the "shortcut" data structure used by the PowerPC implementation |
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95 | to ease access to data elements frequently accessed by RTEMS routines |
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96 | implemented in assembly language is aligned using this value. |
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97 | |
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98 | Maximum Interrupts |
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99 | ------------------ |
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100 | |
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101 | The macro PPC_INTERRUPT_MAX is set to the number of exception sources supported |
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102 | by this PowerPC model. |
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103 | |
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104 | Has Double Precision Floating Point |
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105 | ----------------------------------- |
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106 | |
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107 | The macro PPC_HAS_DOUBLE is set to 1 to indicate that the PowerPC model has |
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108 | support for double precision floating point numbers. This is important because |
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109 | the floating point registers need only be four bytes wide (not eight) if double |
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110 | precision is not supported. |
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111 | |
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112 | Critical Interrupts |
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113 | ------------------- |
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114 | |
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115 | The macro PPC_HAS_RFCI is set to 1 to indicate that the PowerPC model has the |
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116 | Critical Interrupt capability as defined by the IBM 403 models. |
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117 | |
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118 | Use Multiword Load/Store Instructions |
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119 | ------------------------------------- |
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120 | |
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121 | The macro PPC_USE_MULTIPLE is set to 1 to indicate that multiword load and |
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122 | store instructions should be used to perform context switch operations. The |
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123 | relative efficiency of multiword load and store instructions versus an |
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124 | equivalent set of single word load and store instructions varies based upon the |
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125 | PowerPC model. |
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126 | |
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127 | Instruction Cache Size |
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128 | ---------------------- |
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129 | |
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130 | The macro PPC_I_CACHE is set to the size in bytes of the instruction cache. |
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131 | |
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132 | Data Cache Size |
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133 | --------------- |
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134 | |
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135 | The macro PPC_D_CACHE is set to the size in bytes of the data cache. |
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136 | |
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137 | Debug Model |
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138 | ----------- |
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139 | |
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140 | The macro PPC_DEBUG_MODEL is set to indicate the debug support features present |
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141 | in this CPU model. The following debug support feature sets are currently |
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142 | supported: |
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143 | |
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144 | *``PPC_DEBUG_MODEL_STANDARD``* |
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145 | indicates that the single-step trace enable (SE) and branch trace enable |
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146 | (BE) bits in the MSR are supported by this CPU model. |
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147 | |
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148 | *``PPC_DEBUG_MODEL_SINGLE_STEP_ONLY``* |
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149 | indicates that only the single-step trace enable (SE) bit in the MSR is |
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150 | supported by this CPU model. |
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151 | |
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152 | *``PPC_DEBUG_MODEL_IBM4xx``* |
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153 | indicates that the debug exception enable (DE) bit in the MSR is supported |
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154 | by this CPU model. At this time, this particular debug feature set has |
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155 | only been seen in the IBM 4xx series. |
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156 | |
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157 | Low Power Model |
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158 | ~~~~~~~~~~~~~~~ |
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159 | |
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160 | The macro PPC_LOW_POWER_MODE is set to indicate the low power model supported |
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161 | by this CPU model. The following low power modes are currently supported. |
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162 | |
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163 | *``PPC_LOW_POWER_MODE_NONE``* |
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164 | indicates that this CPU model has no low power mode support. |
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165 | |
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166 | *``PPC_LOW_POWER_MODE_STANDARD``* |
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167 | indicates that this CPU model follows the low power model defined for the |
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168 | PPC603e. |
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169 | |
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170 | Multilibs |
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171 | ========= |
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172 | |
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173 | The following multilibs are available: |
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174 | |
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175 | #. ``.``: 32-bit PowerPC with FPU |
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176 | |
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177 | #. ``nof``: 32-bit PowerPC with software floating point support |
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178 | |
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179 | #. ``m403``: Instruction set for PPC403 with FPU |
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180 | |
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181 | #. ``m505``: Instruction set for MPC505 with FPU |
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182 | |
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183 | #. ``m603e``: Instruction set for MPC603e with FPU |
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184 | |
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185 | #. ``m603e/nof``: Instruction set for MPC603e with software floating |
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186 | point support |
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187 | |
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188 | #. ``m604``: Instruction set for MPC604 with FPU |
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189 | |
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190 | #. ``m604/nof``: Instruction set for MPC604 with software floating point |
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191 | support |
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192 | |
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193 | #. ``m860``: Instruction set for MPC860 with FPU |
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194 | |
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195 | #. ``m7400``: Instruction set for MPC7500 with FPU |
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196 | |
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197 | #. ``m7400/nof``: Instruction set for MPC7500 with software floating |
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198 | point support |
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199 | |
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200 | #. ``m8540``: Instruction set for e200, e500 and e500v2 cores with |
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201 | single-precision FPU and SPE |
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202 | |
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203 | #. ``m8540/gprsdouble``: Instruction set for e200, e500 and e500v2 cores |
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204 | with double-precision FPU and SPE |
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205 | |
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206 | #. ``m8540/nof/nospe``: Instruction set for e200, e500 and e500v2 cores |
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207 | with software floating point support and no SPE |
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208 | |
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209 | #. ``me6500/m32``: 32-bit instruction set for e6500 core with FPU and |
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210 | AltiVec |
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211 | |
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212 | #. ``me6500/m32/nof/noaltivec``: 32-bit instruction set for e6500 core |
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213 | with software floating point support and no AltiVec |
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214 | |
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215 | Calling Conventions |
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216 | =================== |
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217 | |
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218 | RTEMS supports the Embedded Application Binary Interface (EABI) calling |
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219 | convention. Documentation for EABI is available by sending a message with a |
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220 | subject line of "EABI" to eabi@goth.sis.mot.com. |
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221 | |
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222 | Programming Model |
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223 | ----------------- |
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224 | |
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225 | This section discusses the programming model for the PowerPC architecture. |
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226 | |
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227 | Non-Floating Point Registers |
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228 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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229 | |
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230 | The PowerPC architecture defines thirty-two non-floating point registers |
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231 | directly visible to the programmer. In thirty-two bit implementations, each |
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232 | register is thirty-two bits wide. In sixty-four bit implementations, each |
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233 | register is sixty-four bits wide. |
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234 | |
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235 | These registers are referred to as ``gpr0`` to ``gpr31``. |
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236 | |
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237 | Some of the registers serve defined roles in the EABI programming model. The |
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238 | following table describes the role of each of these registers: |
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239 | |
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240 | +---------------+----------------+------------------------------+ |
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241 | | Register Name | Alternate Name | Description | |
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242 | +---------------+----------------+------------------------------+ |
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243 | | r1 | sp | stack pointer | |
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244 | +---------------+----------------+------------------------------+ |
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245 | | | | global pointer to the Small | |
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246 | | r2 | na | Constant Area (SDA2) | |
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247 | +---------------+----------------+------------------------------+ |
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248 | | r3 - r12 | na | parameter and result passing | |
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249 | +---------------+----------------+------------------------------+ |
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250 | | | | global pointer to the Small | |
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251 | | r13 | na | Data Area (SDA) | |
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252 | +---------------+----------------+------------------------------+ |
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253 | |
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254 | Floating Point Registers |
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255 | ~~~~~~~~~~~~~~~~~~~~~~~~ |
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256 | |
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257 | The PowerPC architecture includes thirty-two, sixty-four bit floating point |
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258 | registers. All PowerPC floating point instructions interpret these registers |
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259 | as 32 double precision floating point registers, regardless of whether the |
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260 | processor has 64-bit or 32-bit implementation. |
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261 | |
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262 | The floating point status and control register (fpscr) records exceptions and |
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263 | the type of result generated by floating-point operations. Additionally, it |
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264 | controls the rounding mode of operations and allows the reporting of floating |
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265 | exceptions to be enabled or disabled. |
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266 | |
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267 | Special Registers |
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268 | ~~~~~~~~~~~~~~~~~ |
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269 | |
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270 | The PowerPC architecture includes a number of special registers which are |
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271 | critical to the programming model: |
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272 | |
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273 | *Machine State Register* |
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274 | The MSR contains the processor mode, power management mode, endian mode, |
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275 | exception information, privilege level, floating point available and |
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276 | floating point excepiton mode, address translation information and the |
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277 | exception prefix. |
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278 | |
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279 | *Link Register* |
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280 | The LR contains the return address after a function call. This register |
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281 | must be saved before a subsequent subroutine call can be made. The use of |
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282 | this register is discussed further in the *Call and Return Mechanism* |
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283 | section below. |
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284 | |
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285 | *Count Register* |
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286 | The CTR contains the iteration variable for some loops. It may also be |
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287 | used for indirect function calls and jumps. |
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288 | |
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289 | Call and Return Mechanism |
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290 | ------------------------- |
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291 | |
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292 | The PowerPC architecture supports a simple yet effective call and return |
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293 | mechanism. A subroutine is invoked via the "branch and link" (``bl``) and |
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294 | "brank and link absolute" (``bla``) instructions. This instructions place the |
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295 | return address in the Link Register (LR). The callee returns to the caller by |
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296 | executing a "branch unconditional to the link register" (``blr``) instruction. |
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297 | Thus the callee returns to the caller via a jump to the return address which is |
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298 | stored in the LR. |
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299 | |
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300 | The previous contents of the LR are not automatically saved by either the |
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301 | ``bl`` or ``bla``. It is the responsibility of the callee to save the contents |
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302 | of the LR before invoking another subroutine. If the callee invokes another |
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303 | subroutine, it must restore the LR before executing the ``blr`` instruction to |
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304 | return to the caller. |
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305 | |
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306 | It is important to note that the PowerPC subroutine call and return mechanism |
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307 | does not automatically save and restore any registers. |
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308 | |
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309 | The LR may be accessed as special purpose register 8 (``SPR8``) using the "move |
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310 | from special register" (``mfspr``) and "move to special register" (``mtspr``) |
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311 | instructions. |
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312 | |
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313 | Calling Mechanism |
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314 | ----------------- |
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315 | |
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316 | All RTEMS directives are invoked using the regular PowerPC EABI calling |
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317 | convention via the ``bl`` or``bla`` instructions. |
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318 | |
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319 | Register Usage |
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320 | -------------- |
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321 | |
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322 | As discussed above, the call instruction does not automatically save any |
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323 | registers. It is the responsibility of the callee to save and restore any |
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324 | registers which must be preserved across subroutine calls. The callee is |
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325 | responsible for saving callee-preserved registers to the program stack and |
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326 | restoring them before returning to the caller. |
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327 | |
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328 | Parameter Passing |
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329 | ----------------- |
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330 | |
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331 | RTEMS assumes that arguments are placed in the general purpose registers with |
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332 | the first argument in register 3 (``r3``), the second argument in general |
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333 | purpose register 4 (``r4``), and so forth until the seventh argument is in |
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334 | general purpose register 10 (``r10``). If there are more than seven arguments, |
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335 | then subsequent arguments are placed on the program stack. The following |
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336 | pseudo-code illustrates the typical sequence used to call a RTEMS directive |
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337 | with three (3) arguments: |
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338 | |
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339 | .. code-block:: c |
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340 | |
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341 | load third argument into r5 |
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342 | load second argument into r4 |
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343 | load first argument into r3 |
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344 | invoke directive |
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345 | |
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346 | Memory Model |
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347 | ============ |
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348 | |
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349 | Flat Memory Model |
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350 | ----------------- |
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351 | |
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352 | The PowerPC architecture supports a variety of memory models. RTEMS supports |
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353 | the PowerPC using a flat memory model with paging disabled. In this mode, the |
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354 | PowerPC automatically converts every address from a logical to a physical |
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355 | address each time it is used. The PowerPC uses information provided in the |
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356 | Block Address Translation (BAT) to convert these addresses. |
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357 | |
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358 | Implementations of the PowerPC architecture may be thirty-two or sixty-four |
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359 | bit. The PowerPC architecture supports a flat thirty-two or sixty-four bit |
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360 | address space with addresses ranging from 0x00000000 to 0xFFFFFFFF (4 |
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361 | gigabytes) in thirty-two bit implementations or to 0xFFFFFFFFFFFFFFFF in |
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362 | sixty-four bit implementations. Each address is represented by either a |
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363 | thirty-two bit or sixty-four bit value and is byte addressable. The address |
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364 | may be used to reference a single byte, half-word (2-bytes), word (4 bytes), or |
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365 | in sixty-four bit implementations a doubleword (8 bytes). Memory accesses |
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366 | within the address space are performed in big or little endian fashion by the |
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367 | PowerPC based upon the current setting of the Little-endian mode enable bit |
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368 | (LE) in the Machine State Register (MSR). While the processor is in big endian |
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369 | mode, memory accesses which are not properly aligned generate an "alignment |
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370 | exception" (vector offset 0x00600). In little endian mode, the PowerPC |
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371 | architecture does not require the processor to generate alignment exceptions. |
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372 | |
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373 | The following table lists the alignment requirements for a variety of data |
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374 | accesses: |
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375 | |
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376 | ============== ====================== |
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377 | Data Type Alignment Requirement |
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378 | ============== ====================== |
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379 | byte 1 |
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380 | half-word 2 |
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381 | word 4 |
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382 | doubleword 8 |
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383 | ============== ====================== |
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384 | |
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385 | Doubleword load and store operations are only available in PowerPC CPU models |
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386 | which are sixty-four bit implementations. |
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387 | |
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388 | RTEMS does not directly support any PowerPC Memory Management Units, therefore, |
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389 | virtual memory or segmentation systems involving the PowerPC are not supported. |
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390 | |
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391 | Interrupt Processing |
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392 | ==================== |
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393 | |
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394 | Although RTEMS hides many of the processor dependent details of interrupt |
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395 | processing, it is important to understand how the RTEMS interrupt manager is |
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396 | mapped onto the processor's unique architecture. Discussed in this chapter are |
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397 | the PowerPC's interrupt response and control mechanisms as they pertain to |
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398 | RTEMS. |
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399 | |
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400 | RTEMS and associated documentation uses the terms interrupt and vector. In the |
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401 | PowerPC architecture, these terms correspond to exception and exception |
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402 | handler, respectively. The terms will be used interchangeably in this manual. |
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403 | |
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404 | Synchronous Versus Asynchronous Exceptions |
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405 | ------------------------------------------ |
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406 | |
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407 | In the PowerPC architecture exceptions can be either precise or imprecise and |
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408 | either synchronous or asynchronous. Asynchronous exceptions occur when an |
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409 | external event interrupts the processor. Synchronous exceptions are caused by |
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410 | the actions of an instruction. During an exception SRR0 is used to calculate |
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411 | where instruction processing should resume. All instructions prior to the |
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412 | resume instruction will have completed execution. SRR1 is used to store the |
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413 | machine status. |
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414 | |
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415 | There are two asynchronous nonmaskable, highest-priority exceptions system |
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416 | reset and machine check. There are two asynchrononous maskable low-priority |
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417 | exceptions external interrupt and decrementer. Nonmaskable execptions are |
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418 | never delayed, therefore if two nonmaskable, asynchronous exceptions occur in |
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419 | immediate succession, the state information saved by the first exception may be |
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420 | overwritten when the subsequent exception occurs. |
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421 | |
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422 | The PowerPC arcitecure defines one imprecise exception, the imprecise floating |
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423 | point enabled exception. All other synchronous exceptions are precise. The |
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424 | synchronization occuring during asynchronous precise exceptions conforms to the |
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425 | requirements for context synchronization. |
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426 | |
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427 | Vectoring of Interrupt Handler |
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428 | ------------------------------ |
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429 | |
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430 | Upon determining that an exception can be taken the PowerPC automatically |
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431 | performs the following actions: |
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432 | |
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433 | - an instruction address is loaded into SRR0 |
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434 | |
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435 | - bits 33-36 and 42-47 of SRR1 are loaded with information specific to the |
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436 | exception. |
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437 | |
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438 | - bits 0-32, 37-41, and 48-63 of SRR1 are loaded with corresponding bits from |
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439 | the MSR. |
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440 | |
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441 | - the MSR is set based upon the exception type. |
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442 | |
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443 | - instruction fetch and execution resumes, using the new MSR value, at a |
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444 | location specific to the execption type. |
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445 | |
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446 | If the interrupt handler was installed as an RTEMS interrupt handler, then upon |
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447 | receipt of the interrupt, the processor passes control to the RTEMS interrupt |
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448 | handler which performs the following actions: |
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449 | |
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450 | - saves the state of the interrupted task on it's stack, |
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451 | |
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452 | - saves all registers which are not normally preserved by the calling sequence |
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453 | so the user's interrupt service routine can be written in a high-level |
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454 | language. |
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455 | |
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456 | - if this is the outermost (i.e. non-nested) interrupt, then the RTEMS |
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457 | interrupt handler switches from the current stack to the interrupt stack, |
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458 | |
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459 | - enables exceptions, |
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460 | |
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461 | - invokes the vectors to a user interrupt service routine (ISR). |
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462 | |
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463 | Asynchronous interrupts are ignored while exceptions are disabled. Synchronous |
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464 | interrupts which occur while are disabled result in the CPU being forced into |
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465 | an error mode. |
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466 | |
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467 | A nested interrupt is processed similarly with the exception that the current |
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468 | stack need not be switched to the interrupt stack. |
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469 | |
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470 | Interrupt Levels |
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471 | ---------------- |
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472 | |
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473 | The PowerPC architecture supports only a single external asynchronous interrupt |
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474 | source. This interrupt source may be enabled and disabled via the External |
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475 | Interrupt Enable (EE) bit in the Machine State Register (MSR). Thus only two |
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476 | level (enabled and disabled) of external device interrupt priorities are |
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477 | directly supported by the PowerPC architecture. |
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478 | |
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479 | Some PowerPC implementations include a Critical Interrupt capability which is |
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480 | often used to receive interrupts from high priority external devices. |
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481 | |
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482 | The RTEMS interrupt level mapping scheme for the PowerPC is not a numeric level |
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483 | as on most RTEMS ports. It is a bit mapping in which the least three |
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484 | significiant bits of the interrupt level are mapped directly to the enabling of |
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485 | specific interrupt sources as follows: |
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486 | |
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487 | *Critical Interrupt* |
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488 | Setting bit 0 (the least significant bit) of the interrupt level enables |
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489 | the Critical Interrupt source, if it is available on this CPU model. |
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490 | |
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491 | *Machine Check* |
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492 | Setting bit 1 of the interrupt level enables Machine Check execptions. |
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493 | |
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494 | *External Interrupt* |
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495 | Setting bit 2 of the interrupt level enables External Interrupt execptions. |
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496 | |
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497 | All other bits in the RTEMS task interrupt level are ignored. |
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498 | |
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499 | Default Fatal Error Processing |
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500 | ============================== |
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501 | |
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502 | The default fatal error handler for this architecture performs the following |
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503 | actions: |
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504 | |
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505 | - places the error code in r3, and |
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506 | |
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507 | - executes a trap instruction which results in a Program Exception. |
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508 | |
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509 | If the Program Exception returns, then the following actions are performed: |
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510 | |
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511 | - disables all processor exceptions by loading a 0 into the MSR, and |
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512 | |
---|
513 | - goes into an infinite loop to simulate a halt processor instruction. |
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514 | |
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515 | Symmetric Multiprocessing |
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516 | ========================= |
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517 | |
---|
518 | SMP is supported. Available platforms are the Freescale QorIQ P series (e.g. |
---|
519 | P1020) and T series (e.g. T2080, T4240). |
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520 | |
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521 | Thread-Local Storage |
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522 | ==================== |
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523 | |
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524 | Thread-local storage is supported. |
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525 | |
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526 | Board Support Packages |
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527 | ====================== |
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528 | |
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529 | System Reset |
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530 | ------------ |
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531 | |
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532 | An RTEMS based application is initiated or re-initiated when the PowerPC |
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533 | processor is reset. The PowerPC architecture defines a Reset Exception, but |
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534 | leaves the details of the CPU state as implementation specific. Please refer |
---|
535 | to the User's Manual for the CPU model in question. |
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536 | |
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537 | In general, at power-up the PowerPC begin execution at address 0xFFF00100 in |
---|
538 | supervisor mode with all exceptions disabled. For soft resets, the CPU will |
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539 | vector to either 0xFFF00100 or 0x00000100 depending upon the setting of the |
---|
540 | Exception Prefix bit in the MSR. If during a soft reset, a Machine Check |
---|
541 | Exception occurs, then the CPU may execute a hard reset. |
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542 | |
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543 | Processor Initialization |
---|
544 | ------------------------ |
---|
545 | |
---|
546 | If this PowerPC implementation supports on-chip caching and this is to be |
---|
547 | utilized, then it should be enabled during the reset application initialization |
---|
548 | code. On-chip caching has been observed to prevent some emulators from working |
---|
549 | properly, so it may be necessary to run with caching disabled to use these |
---|
550 | emulators. |
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551 | |
---|
552 | In addition to the requirements described in the*Board Support Packages* |
---|
553 | chapter of the RTEMS C Applications User's Manual for the reset code which is |
---|
554 | executed before the call to ``rtems_initialize_executive``, the PowrePC version |
---|
555 | has the following specific requirements: |
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556 | |
---|
557 | - Must leave the PR bit of the Machine State Register (MSR) set to 0 so the |
---|
558 | PowerPC remains in the supervisor state. |
---|
559 | |
---|
560 | - Must set stack pointer (sp or r1) such that a minimum stack size of |
---|
561 | MINIMUM_STACK_SIZE bytes is provided for the RTEMS initialization sequence. |
---|
562 | |
---|
563 | - Must disable all external interrupts (i.e. clear the EI (EE) bit of the |
---|
564 | machine state register). |
---|
565 | |
---|
566 | - Must enable traps so window overflow and underflow conditions can be properly |
---|
567 | handled. |
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568 | |
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569 | - Must initialize the PowerPC's initial Exception Table with default handlers. |
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