[489740f] | 1 | .. comment SPDX-License-Identifier: CC-BY-SA-4.0 |
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| 2 | |
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[f233256] | 3 | .. COMMENT: COPYRIGHT (c) 1988-2002. |
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| 4 | .. COMMENT: On-Line Applications Research Corporation (OAR). |
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| 5 | .. COMMENT: All rights reserved. |
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| 6 | |
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[d755cbd] | 7 | PowerPC Specific Information |
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[6916004] | 8 | **************************** |
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[d755cbd] | 9 | |
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| 10 | Multilibs |
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| 11 | ========= |
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| 12 | |
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| 13 | The following multilibs are available: |
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| 14 | |
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[4cc9094] | 15 | #. ``.``: 32-bit PowerPC with FPU |
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[d755cbd] | 16 | |
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[4cc9094] | 17 | #. ``nof``: 32-bit PowerPC with software floating point support |
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[d755cbd] | 18 | |
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[4cc9094] | 19 | #. ``m403``: Instruction set for PPC403 with FPU |
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[d755cbd] | 20 | |
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[4cc9094] | 21 | #. ``m505``: Instruction set for MPC505 with FPU |
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[d755cbd] | 22 | |
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[4cc9094] | 23 | #. ``m603e``: Instruction set for MPC603e with FPU |
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[d755cbd] | 24 | |
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[4cc9094] | 25 | #. ``m603e/nof``: Instruction set for MPC603e with software floating |
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| 26 | point support |
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[d755cbd] | 27 | |
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[4cc9094] | 28 | #. ``m604``: Instruction set for MPC604 with FPU |
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[d755cbd] | 29 | |
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[4cc9094] | 30 | #. ``m604/nof``: Instruction set for MPC604 with software floating point |
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| 31 | support |
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[d755cbd] | 32 | |
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[4cc9094] | 33 | #. ``m860``: Instruction set for MPC860 with FPU |
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[d755cbd] | 34 | |
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[4cc9094] | 35 | #. ``m7400``: Instruction set for MPC7500 with FPU |
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[d755cbd] | 36 | |
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[4cc9094] | 37 | #. ``m7400/nof``: Instruction set for MPC7500 with software floating |
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| 38 | point support |
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[d755cbd] | 39 | |
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[4cc9094] | 40 | #. ``m8540``: Instruction set for e200, e500 and e500v2 cores with |
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| 41 | single-precision FPU and SPE |
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[d755cbd] | 42 | |
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[4cc9094] | 43 | #. ``m8540/gprsdouble``: Instruction set for e200, e500 and e500v2 cores |
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| 44 | with double-precision FPU and SPE |
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[d755cbd] | 45 | |
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[4cc9094] | 46 | #. ``m8540/nof/nospe``: Instruction set for e200, e500 and e500v2 cores |
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| 47 | with software floating point support and no SPE |
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[d755cbd] | 48 | |
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[4cc9094] | 49 | #. ``me6500/m32``: 32-bit instruction set for e6500 core with FPU and |
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| 50 | AltiVec |
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[d755cbd] | 51 | |
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[4cc9094] | 52 | #. ``me6500/m32/nof/noaltivec``: 32-bit instruction set for e6500 core |
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| 53 | with software floating point support and no AltiVec |
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[d755cbd] | 54 | |
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[b6977f7] | 55 | #. ``me6500/m64``: 64-bit instruction set for e6500 core with FPU and |
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| 56 | AltiVec |
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[f233256] | 57 | |
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[b6977f7] | 58 | #. ``me6500/m64/nof/noaltivec``: 64-bit instruction set for e6500 core |
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| 59 | with software floating point support and no AltiVec |
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[d755cbd] | 60 | |
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[b6977f7] | 61 | Application Binary Interface |
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| 62 | ============================ |
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[d755cbd] | 63 | |
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[b6977f7] | 64 | In 32-bit PowerPC configurations the ABI defined by |
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| 65 | `Power Architecture 32-bit Application Binary Interface Supplement 1.0 - Embedded <https://ftp.rtems.org/pub/rtems/people/sebh/Power-Arch-32-bit-ABI-supp-1.0-Embedded.pdf>`_ |
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| 66 | is used. |
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[d755cbd] | 67 | |
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[b6977f7] | 68 | In 64-bit PowerPC configurations the ABI defined by |
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| 69 | `Power Architecture 64-Bit ELF V2 ABI Specification, Version 1.1 <https://ftp.rtems.org/pub/rtems/people/sebh/ABI64BitOpenPOWERv1.1_16July2015_pub.pdf>`_ |
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| 70 | is used. |
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[d755cbd] | 71 | |
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| 72 | Special Registers |
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[b6977f7] | 73 | ================= |
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[d755cbd] | 74 | |
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[b6977f7] | 75 | The following special-purpose registers are used by RTEMS: |
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[d755cbd] | 76 | |
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[6297ad3] | 77 | *Special-Purpose Register General 0 (SPRG0)* |
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[b6977f7] | 78 | In SMP configurations, this register contains the address of the per-CPU |
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[6297ad3] | 79 | control of the processor. |
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| 80 | |
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| 81 | *Special-Purpose Register General 1 (SPRG1)* |
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| 82 | This register contains the interrupt stack pointer for the outer-most |
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| 83 | interrupt service routine. |
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| 84 | |
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| 85 | *Special-Purpose Register General 2 (SPRG2)* |
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| 86 | This register contains the address of interrupt stack area begin. |
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| 87 | |
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[d755cbd] | 88 | Memory Model |
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| 89 | ============ |
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| 90 | |
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[b6977f7] | 91 | The memory model is flat. |
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[d755cbd] | 92 | |
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| 93 | Interrupt Processing |
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| 94 | ==================== |
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| 95 | |
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| 96 | Interrupt Levels |
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| 97 | ---------------- |
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| 98 | |
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[b6977f7] | 99 | There are exactly two interrupt levels on PowerPC with respect to RTEMS. Level |
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| 100 | zero corresponds to interrupts enabled. Level one corresponds to interrupts |
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| 101 | disabled. |
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[d755cbd] | 102 | |
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[b6977f7] | 103 | Interrupt Stack |
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| 104 | --------------- |
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[d755cbd] | 105 | |
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[b6977f7] | 106 | The interrupt stack size can be configured via the |
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| 107 | ``CONFIGURE_INTERRUPT_STACK_SIZE`` application configuration option. |
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[d755cbd] | 108 | |
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| 109 | Default Fatal Error Processing |
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| 110 | ============================== |
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| 111 | |
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[b6977f7] | 112 | The default fatal error handler is BSP-specific. |
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[d755cbd] | 113 | |
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| 114 | Symmetric Multiprocessing |
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| 115 | ========================= |
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| 116 | |
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| 117 | SMP is supported. Available platforms are the Freescale QorIQ P series (e.g. |
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| 118 | P1020) and T series (e.g. T2080, T4240). |
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| 119 | |
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| 120 | Thread-Local Storage |
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| 121 | ==================== |
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| 122 | |
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| 123 | Thread-local storage is supported. |
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| 124 | |
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[b6977f7] | 125 | 64-bit Caveats |
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| 126 | ============== |
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[d755cbd] | 127 | |
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[3fdea2d] | 128 | * The thread pointer is ``r13`` in contrast to ``r2`` used in the 32-bit ABI. |
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[d755cbd] | 129 | |
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[3fdea2d] | 130 | * The TOC pointer is ``r2``. It must be initialized as part of the C run-time |
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[b6977f7] | 131 | setup. A valid stack pointer is not enough to call C functions. They may |
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| 132 | use the TOC to get addresses and constants. |
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[d755cbd] | 133 | |
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[873ba80] | 134 | * The TOC must be within the first 2GiB of the address space. This simplifies |
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[3fdea2d] | 135 | the interrupt prologue, since the ``r2`` can be set to ``.TOC.`` via the |
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| 136 | usual ``lis`` followed by ``ori`` combination. The ``lis`` is subject to |
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| 137 | sign-extension. |
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[d755cbd] | 138 | |
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[3fdea2d] | 139 | * The ``PPC_REG_LOAD``, ``PPC_REG_STORE``, ``PPC_REG_STORE_UPDATE``, and |
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| 140 | ``PPC_REG_CMP`` macros are available for assembly code to provide register |
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| 141 | size operations selected by the GCC ``-m32`` and ``-m64`` options. |
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[d755cbd] | 142 | |
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[3fdea2d] | 143 | * The ``MSR[CM]`` bit must be set all the time, otherwise the MMU translation |
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| 144 | my yield unexpected results. The ``EPCR[ICM]`` or ``EPCR[GICM]`` bits may be |
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| 145 | used to enable the 64-bit compute mode for exceptions. |
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