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[489740f]1.. comment SPDX-License-Identifier: CC-BY-SA-4.0
[f233256]3.. COMMENT: COPYRIGHT (c) 1988-2002.
4.. COMMENT: On-Line Applications Research Corporation (OAR).
5.. COMMENT: All rights reserved.
[d755cbd]7PowerPC Specific Information
[f233256]10This chapter discusses the PowerPC architecture dependencies in this port of
11RTEMS.  The PowerPC family has a wide variety of implementations by a range of
12vendors.  Consequently, there are many, many CPU models within it.
[f233256]14It is highly recommended that the PowerPC RTEMS application developer obtain
15and become familiar with the documentation for the processor being used as well
16as the specification for the revision of the PowerPC architecture which
[d755cbd]17corresponds to that processor.
19**PowerPC Architecture Documents**
[f233256]21For information on the PowerPC architecture, refer to the following documents
22available from Motorola and IBM:
24- *PowerPC Microprocessor Family: The Programming Environment*
25  (Motorola Document MPRPPCFPE-01).
[d389819]27- *IBM PPC403GB Embedded Controller User's Manual*.
29- *PoweRisControl MPC500 Family RCPU RISC Central Processing
30  Unit Reference Manual* (Motorola Document RCPUURM/AD).
[d389819]32- *PowerPC 601 RISC Microprocessor User's Manual*
[d755cbd]33  (Motorola Document MPR601UM/AD).
[d389819]35- *PowerPC 603 RISC Microprocessor User's Manual*
[d755cbd]36  (Motorola Document MPR603UM/AD).
[d389819]38- *PowerPC 603e RISC Microprocessor User's Manual*
[d755cbd]39  (Motorola Document MPR603EUM/AD).
[d389819]41- *PowerPC 604 RISC Microprocessor User's Manual*
[d755cbd]42  (Motorola Document MPR604UM/AD).
[d389819]44- *PowerPC MPC821 Portable Systems Microprocessor User's Manual*
[d755cbd]45  (Motorola Document MPC821UM/AD).
[f233256]47- *PowerQUICC MPC860 User's Manual*
48  (Motorola Document MPC860UM/AD).
[f233256]50Motorola maintains an on-line electronic library for the PowerPC at the
51following URL:
[f233256]55This site has a a wealth of information and examples.  Many of the manuals are
56available from that site in electronic format.
58**PowerPC Processor Simulator Information**
[f233256]60PSIM is a program which emulates the Instruction Set Architecture of the
61PowerPC microprocessor family.  It is reely available in source code form under
62the terms of the GNU General Public License (version 2 or later).  PSIM can be
63integrated with the GNU Debugger (gdb) to execute and debug PowerPC executables
64on non-PowerPC hosts.  PSIM supports the addition of user provided device
65models which can be used to allow one to develop and debug embedded
66applications using the simulator.
[f233256]68The latest version of PSIM is included in GDB and enabled on pre-built binaries
69provided by the RTEMS Project.
71CPU Model Dependent Features
[f233256]74This section presents the set of features which vary across PowerPC
75implementations and are of importance to RTEMS.  The set of CPU model feature
76macros are defined in the file ``cpukit/score/cpu/powerpc/powerpc.h`` based
77upon the particular CPU model specified on the compilation command line.
[d389819]82The macro PPC_ALIGNMENT is set to the PowerPC model's worst case alignment
[f233256]83requirement for data types on a byte boundary.  This value is used to derive
84the alignment restrictions for memory allocated from regions and partitions.
86Cache Alignment
[f233256]89The macro PPC_CACHE_ALIGNMENT is set to the line size of the cache.  It is used
90to align the entry point of critical routines so that as much code as possible
91can be retrieved with the initial read into cache.  This is done for the
92interrupt handler as well as the context switch routines.
94In addition, the "shortcut" data structure used by the PowerPC implementation
95to ease access to data elements frequently accessed by RTEMS routines
96implemented in assembly language is aligned using this value.
98Maximum Interrupts
[f233256]101The macro PPC_INTERRUPT_MAX is set to the number of exception sources supported
102by this PowerPC model.
104Has Double Precision Floating Point
[f233256]107The macro PPC_HAS_DOUBLE is set to 1 to indicate that the PowerPC model has
108support for double precision floating point numbers.  This is important because
109the floating point registers need only be four bytes wide (not eight) if double
110precision is not supported.
112Critical Interrupts
[f233256]115The macro PPC_HAS_RFCI is set to 1 to indicate that the PowerPC model has the
116Critical Interrupt capability as defined by the IBM 403 models.
118Use Multiword Load/Store Instructions
121The macro PPC_USE_MULTIPLE is set to 1 to indicate that multiword load and
[f233256]122store instructions should be used to perform context switch operations.  The
123relative efficiency of multiword load and store instructions versus an
124equivalent set of single word load and store instructions varies based upon the
125PowerPC model.
127Instruction Cache Size
130The macro PPC_I_CACHE is set to the size in bytes of the instruction cache.
132Data Cache Size
135The macro PPC_D_CACHE is set to the size in bytes of the data cache.
137Debug Model
[f233256]140The macro PPC_DEBUG_MODEL is set to indicate the debug support features present
141in this CPU model.  The following debug support feature sets are currently
[f233256]145    indicates that the single-step trace enable (SE) and branch trace enable
146    (BE) bits in the MSR are supported by this CPU model.
[f233256]149    indicates that only the single-step trace enable (SE) bit in the MSR is
150    supported by this CPU model.
153    indicates that the debug exception enable (DE) bit in the MSR is supported
[f233256]154    by this CPU model.  At this time, this particular debug feature set has
155    only been seen in the IBM 4xx series.
157Low Power Model
[f233256]160The macro PPC_LOW_POWER_MODE is set to indicate the low power model supported
161by this CPU model.  The following low power modes are currently supported.
164    indicates that this CPU model has no low power mode support.
[f233256]167    indicates that this CPU model follows the low power model defined for the
168    PPC603e.
173The following multilibs are available:
[4cc9094]175#. ``.``: 32-bit PowerPC with FPU
[4cc9094]177#. ``nof``: 32-bit PowerPC with software floating point support
[4cc9094]179#. ``m403``: Instruction set for PPC403 with FPU
[4cc9094]181#. ``m505``: Instruction set for MPC505 with FPU
[4cc9094]183#. ``m603e``: Instruction set for MPC603e with FPU
[4cc9094]185#. ``m603e/nof``: Instruction set for MPC603e with software floating
186   point support
[4cc9094]188#. ``m604``: Instruction set for MPC604 with FPU
[4cc9094]190#. ``m604/nof``: Instruction set for MPC604 with software floating point
191   support
[4cc9094]193#. ``m860``: Instruction set for MPC860 with FPU
[4cc9094]195#. ``m7400``: Instruction set for MPC7500 with FPU
[4cc9094]197#. ``m7400/nof``: Instruction set for MPC7500 with software floating
198   point support
[4cc9094]200#. ``m8540``: Instruction set for e200, e500 and e500v2 cores with
201   single-precision FPU and SPE
[4cc9094]203#. ``m8540/gprsdouble``: Instruction set for e200, e500 and e500v2 cores
204   with double-precision FPU and SPE
[4cc9094]206#. ``m8540/nof/nospe``: Instruction set for e200, e500 and e500v2 cores
207   with software floating point support and no SPE
[4cc9094]209#. ``me6500/m32``: 32-bit instruction set for e6500 core with FPU and
210   AltiVec
[4cc9094]212#. ``me6500/m32/nof/noaltivec``: 32-bit instruction set for e6500 core
213   with software floating point support and no AltiVec
215Calling Conventions
[f233256]218RTEMS supports the Embedded Application Binary Interface (EABI) calling
219convention.  Documentation for EABI is available by sending a message with a
220subject line of "EABI" to
222Programming Model
[f233256]225This section discusses the programming model for the PowerPC architecture.
227Non-Floating Point Registers
230The PowerPC architecture defines thirty-two non-floating point registers
231directly visible to the programmer.  In thirty-two bit implementations, each
232register is thirty-two bits wide.  In sixty-four bit implementations, each
233register is sixty-four bits wide.
235These registers are referred to as ``gpr0`` to ``gpr31``.
[f233256]237Some of the registers serve defined roles in the EABI programming model.  The
238following table describes the role of each of these registers:
241| Register Name | Alternate Name |         Description          |
243|      r1       |      sp        |         stack pointer        |
245|               |                |  global pointer to the Small |
246|      r2       |      na        |     Constant Area (SDA2)     |
248|    r3 - r12   |      na        | parameter and result passing |
250|               |                |  global pointer to the Small |
251|      r13      |      na        |         Data Area (SDA)      |
254Floating Point Registers
[f233256]257The PowerPC architecture includes thirty-two, sixty-four bit floating point
258registers.  All PowerPC floating point instructions interpret these registers
259as 32 double precision floating point registers, regardless of whether the
260processor has 64-bit or 32-bit implementation.
[f233256]262The floating point status and control register (fpscr) records exceptions and
263the type of result generated by floating-point operations.  Additionally, it
264controls the rounding mode of operations and allows the reporting of floating
265exceptions to be enabled or disabled.
267Special Registers
[f233256]270The PowerPC architecture includes a number of special registers which are
271critical to the programming model:
273*Machine State Register*
274    The MSR contains the processor mode, power management mode, endian mode,
275    exception information, privilege level, floating point available and
[f233256]276    floating point excepiton mode, address translation information and the
277    exception prefix.
279*Link Register*
280    The LR contains the return address after a function call.  This register
[f233256]281    must be saved before a subsequent subroutine call can be made.  The use of
282    this register is discussed further in the *Call and Return Mechanism*
283    section below.
285*Count Register*
[f233256]286    The CTR contains the iteration variable for some loops.  It may also be
287    used for indirect function calls and jumps.
289Call and Return Mechanism
[f233256]292The PowerPC architecture supports a simple yet effective call and return
293mechanism.  A subroutine is invoked via the "branch and link" (``bl``) and
294"brank and link absolute" (``bla``) instructions.  This instructions place the
295return address in the Link Register (LR).  The callee returns to the caller by
296executing a "branch unconditional to the link register" (``blr``) instruction.
297Thus the callee returns to the caller via a jump to the return address which is
298stored in the LR.
300The previous contents of the LR are not automatically saved by either the
301``bl`` or ``bla``.  It is the responsibility of the callee to save the contents
302of the LR before invoking another subroutine.  If the callee invokes another
303subroutine, it must restore the LR before executing the ``blr`` instruction to
304return to the caller.
306It is important to note that the PowerPC subroutine call and return mechanism
307does not automatically save and restore any registers.
309The LR may be accessed as special purpose register 8 (``SPR8``) using the "move
310from special register" (``mfspr``) and "move to special register" (``mtspr``)
313Calling Mechanism
[f233256]316All RTEMS directives are invoked using the regular PowerPC EABI calling
317convention via the ``bl`` or``bla`` instructions.
319Register Usage
[f233256]322As discussed above, the call instruction does not automatically save any
323registers.  It is the responsibility of the callee to save and restore any
324registers which must be preserved across subroutine calls.  The callee is
325responsible for saving callee-preserved registers to the program stack and
326restoring them before returning to the caller.
328Parameter Passing
[f233256]331RTEMS assumes that arguments are placed in the general purpose registers with
332the first argument in register 3 (``r3``), the second argument in general
333purpose register 4 (``r4``), and so forth until the seventh argument is in
334general purpose register 10 (``r10``).  If there are more than seven arguments,
335then subsequent arguments are placed on the program stack.  The following
336pseudo-code illustrates the typical sequence used to call a RTEMS directive
[d755cbd]337with three (3) arguments:
339.. code-block:: c
341    load third argument into r5
342    load second argument into r4
343    load first argument into r3
344    invoke directive
346Memory Model
349Flat Memory Model
[f233256]352The PowerPC architecture supports a variety of memory models.  RTEMS supports
353the PowerPC using a flat memory model with paging disabled.  In this mode, the
354PowerPC automatically converts every address from a logical to a physical
355address each time it is used.  The PowerPC uses information provided in the
356Block Address Translation (BAT) to convert these addresses.
358Implementations of the PowerPC architecture may be thirty-two or sixty-four
359bit.  The PowerPC architecture supports a flat thirty-two or sixty-four bit
360address space with addresses ranging from 0x00000000 to 0xFFFFFFFF (4
361gigabytes) in thirty-two bit implementations or to 0xFFFFFFFFFFFFFFFF in
362sixty-four bit implementations.  Each address is represented by either a
363thirty-two bit or sixty-four bit value and is byte addressable.  The address
364may be used to reference a single byte, half-word (2-bytes), word (4 bytes), or
365in sixty-four bit implementations a doubleword (8 bytes).  Memory accesses
366within the address space are performed in big or little endian fashion by the
367PowerPC based upon the current setting of the Little-endian mode enable bit
368(LE) in the Machine State Register (MSR).  While the processor is in big endian
369mode, memory accesses which are not properly aligned generate an "alignment
370exception" (vector offset 0x00600).  In little endian mode, the PowerPC
371architecture does not require the processor to generate alignment exceptions.
373The following table lists the alignment requirements for a variety of data
[0c97890]376==============  ======================
377Data Type       Alignment Requirement
378==============  ======================
379byte            1
380half-word       2
381word            4
382doubleword      8
383==============  ======================
385Doubleword load and store operations are only available in PowerPC CPU models
386which are sixty-four bit implementations.
388RTEMS does not directly support any PowerPC Memory Management Units, therefore,
389virtual memory or segmentation systems involving the PowerPC are not supported.
391Interrupt Processing
[f233256]394Although RTEMS hides many of the processor dependent details of interrupt
395processing, it is important to understand how the RTEMS interrupt manager is
396mapped onto the processor's unique architecture. Discussed in this chapter are
397the PowerPC's interrupt response and control mechanisms as they pertain to
[f233256]400RTEMS and associated documentation uses the terms interrupt and vector.  In the
401PowerPC architecture, these terms correspond to exception and exception
402handler, respectively.  The terms will be used interchangeably in this manual.
404Synchronous Versus Asynchronous Exceptions
[f233256]407In the PowerPC architecture exceptions can be either precise or imprecise and
408either synchronous or asynchronous.  Asynchronous exceptions occur when an
409external event interrupts the processor.  Synchronous exceptions are caused by
410the actions of an instruction. During an exception SRR0 is used to calculate
411where instruction processing should resume.  All instructions prior to the
412resume instruction will have completed execution.  SRR1 is used to store the
413machine status.
415There are two asynchronous nonmaskable, highest-priority exceptions system
416reset and machine check.  There are two asynchrononous maskable low-priority
417exceptions external interrupt and decrementer.  Nonmaskable execptions are
418never delayed, therefore if two nonmaskable, asynchronous exceptions occur in
419immediate succession, the state information saved by the first exception may be
420overwritten when the subsequent exception occurs.
422The PowerPC arcitecure defines one imprecise exception, the imprecise floating
423point enabled exception.  All other synchronous exceptions are precise.  The
424synchronization occuring during asynchronous precise exceptions conforms to the
425requirements for context synchronization.
427Vectoring of Interrupt Handler
430Upon determining that an exception can be taken the PowerPC automatically
431performs the following actions:
433- an instruction address is loaded into SRR0
[f233256]435- bits 33-36 and 42-47 of SRR1 are loaded with information specific to the
436  exception.
[f233256]438- bits 0-32, 37-41, and 48-63 of SRR1 are loaded with corresponding bits from
439  the MSR.
441- the MSR is set based upon the exception type.
[f233256]443- instruction fetch and execution resumes, using the new MSR value, at a
444  location specific to the execption type.
[f233256]446If the interrupt handler was installed as an RTEMS interrupt handler, then upon
447receipt of the interrupt, the processor passes control to the RTEMS interrupt
448handler which performs the following actions:
[d389819]450- saves the state of the interrupted task on it's stack,
[f233256]452- saves all registers which are not normally preserved by the calling sequence
453  so the user's interrupt service routine can be written in a high-level
454  language.
[f233256]456- if this is the outermost (i.e. non-nested) interrupt, then the RTEMS
457  interrupt handler switches from the current stack to the interrupt stack,
459- enables exceptions,
461- invokes the vectors to a user interrupt service routine (ISR).
[f233256]463Asynchronous interrupts are ignored while exceptions are disabled.  Synchronous
464interrupts which occur while are disabled result in the CPU being forced into
465an error mode.
[f233256]467A nested interrupt is processed similarly with the exception that the current
468stack need not be switched to the interrupt stack.
470Interrupt Levels
[f233256]473The PowerPC architecture supports only a single external asynchronous interrupt
474source.  This interrupt source may be enabled and disabled via the External
475Interrupt Enable (EE) bit in the Machine State Register (MSR).  Thus only two
476level (enabled and disabled) of external device interrupt priorities are
[d755cbd]477directly supported by the PowerPC architecture.
[f233256]479Some PowerPC implementations include a Critical Interrupt capability which is
480often used to receive interrupts from high priority external devices.
[f233256]482The RTEMS interrupt level mapping scheme for the PowerPC is not a numeric level
483as on most RTEMS ports.  It is a bit mapping in which the least three
484significiant bits of the interrupt level are mapped directly to the enabling of
485specific interrupt sources as follows:
487*Critical Interrupt*
[f233256]488    Setting bit 0 (the least significant bit) of the interrupt level enables
489    the Critical Interrupt source, if it is available on this CPU model.
491*Machine Check*
492    Setting bit 1 of the interrupt level enables Machine Check execptions.
494*External Interrupt*
495    Setting bit 2 of the interrupt level enables External Interrupt execptions.
497All other bits in the RTEMS task interrupt level are ignored.
499Default Fatal Error Processing
[f233256]502The default fatal error handler for this architecture performs the following
505- places the error code in r3, and
507- executes a trap instruction which results in a Program Exception.
509If the Program Exception returns, then the following actions are performed:
511- disables all processor exceptions by loading a 0 into the MSR, and
513- goes into an infinite loop to simulate a halt processor instruction.
515Symmetric Multiprocessing
518SMP is supported.  Available platforms are the Freescale QorIQ P series (e.g.
519P1020) and T series (e.g. T2080, T4240).
521Thread-Local Storage
524Thread-local storage is supported.
526Board Support Packages
529System Reset
[f233256]532An RTEMS based application is initiated or re-initiated when the PowerPC
533processor is reset.  The PowerPC architecture defines a Reset Exception, but
534leaves the details of the CPU state as implementation specific.  Please refer
535to the User's Manual for the CPU model in question.
[f233256]537In general, at power-up the PowerPC begin execution at address 0xFFF00100 in
538supervisor mode with all exceptions disabled.  For soft resets, the CPU will
539vector to either 0xFFF00100 or 0x00000100 depending upon the setting of the
540Exception Prefix bit in the MSR.  If during a soft reset, a Machine Check
541Exception occurs, then the CPU may execute a hard reset.
543Processor Initialization
[f233256]546If this PowerPC implementation supports on-chip caching and this is to be
547utilized, then it should be enabled during the reset application initialization
548code.  On-chip caching has been observed to prevent some emulators from working
549properly, so it may be necessary to run with caching disabled to use these
[f233256]552In addition to the requirements described in the*Board Support Packages*
553chapter of the RTEMS C Applications User's Manual for the reset code which is
554executed before the call to ``rtems_initialize_executive``, the PowrePC version
555has the following specific requirements:
[f233256]557- Must leave the PR bit of the Machine State Register (MSR) set to 0 so the
558  PowerPC remains in the supervisor state.
[f233256]560- Must set stack pointer (sp or r1) such that a minimum stack size of
561  MINIMUM_STACK_SIZE bytes is provided for the RTEMS initialization sequence.
[f233256]563- Must disable all external interrupts (i.e. clear the EI (EE) bit of the
564  machine state register).
[f233256]566- Must enable traps so window overflow and underflow conditions can be properly
567  handled.
[f233256]569- Must initialize the PowerPC's initial Exception Table with default handlers.
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