source: rtems-docs/cpu-supplement/powerpc.rst @ 3fdea2d

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Last change on this file since 3fdea2d was 3fdea2d, checked in by Sebastian Huber <sebastian.huber@…>, on Aug 25, 2017 at 8:35:14 AM

cpu-supplement: Use literal instead of emphasis

Update #3082.

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[489740f]1.. comment SPDX-License-Identifier: CC-BY-SA-4.0
2
[f233256]3.. COMMENT: COPYRIGHT (c) 1988-2002.
4.. COMMENT: On-Line Applications Research Corporation (OAR).
5.. COMMENT: All rights reserved.
6
[d755cbd]7PowerPC Specific Information
[6916004]8****************************
[d755cbd]9
10Multilibs
11=========
12
13The following multilibs are available:
14
[4cc9094]15#. ``.``: 32-bit PowerPC with FPU
[d755cbd]16
[4cc9094]17#. ``nof``: 32-bit PowerPC with software floating point support
[d755cbd]18
[4cc9094]19#. ``m403``: Instruction set for PPC403 with FPU
[d755cbd]20
[4cc9094]21#. ``m505``: Instruction set for MPC505 with FPU
[d755cbd]22
[4cc9094]23#. ``m603e``: Instruction set for MPC603e with FPU
[d755cbd]24
[4cc9094]25#. ``m603e/nof``: Instruction set for MPC603e with software floating
26   point support
[d755cbd]27
[4cc9094]28#. ``m604``: Instruction set for MPC604 with FPU
[d755cbd]29
[4cc9094]30#. ``m604/nof``: Instruction set for MPC604 with software floating point
31   support
[d755cbd]32
[4cc9094]33#. ``m860``: Instruction set for MPC860 with FPU
[d755cbd]34
[4cc9094]35#. ``m7400``: Instruction set for MPC7500 with FPU
[d755cbd]36
[4cc9094]37#. ``m7400/nof``: Instruction set for MPC7500 with software floating
38   point support
[d755cbd]39
[4cc9094]40#. ``m8540``: Instruction set for e200, e500 and e500v2 cores with
41   single-precision FPU and SPE
[d755cbd]42
[4cc9094]43#. ``m8540/gprsdouble``: Instruction set for e200, e500 and e500v2 cores
44   with double-precision FPU and SPE
[d755cbd]45
[4cc9094]46#. ``m8540/nof/nospe``: Instruction set for e200, e500 and e500v2 cores
47   with software floating point support and no SPE
[d755cbd]48
[4cc9094]49#. ``me6500/m32``: 32-bit instruction set for e6500 core with FPU and
50   AltiVec
[d755cbd]51
[4cc9094]52#. ``me6500/m32/nof/noaltivec``: 32-bit instruction set for e6500 core
53   with software floating point support and no AltiVec
[d755cbd]54
[b6977f7]55#. ``me6500/m64``: 64-bit instruction set for e6500 core with FPU and
56   AltiVec
[f233256]57
[b6977f7]58#. ``me6500/m64/nof/noaltivec``: 64-bit instruction set for e6500 core
59   with software floating point support and no AltiVec
[d755cbd]60
[b6977f7]61Application Binary Interface
62============================
[d755cbd]63
[b6977f7]64In 32-bit PowerPC configurations the ABI defined by
65`Power Architecture 32-bit Application Binary Interface Supplement 1.0 - Embedded <https://ftp.rtems.org/pub/rtems/people/sebh/Power-Arch-32-bit-ABI-supp-1.0-Embedded.pdf>`_
66is used.
[d755cbd]67
[b6977f7]68In 64-bit PowerPC configurations the ABI defined by
69`Power Architecture 64-Bit ELF V2 ABI Specification, Version 1.1 <https://ftp.rtems.org/pub/rtems/people/sebh/ABI64BitOpenPOWERv1.1_16July2015_pub.pdf>`_
70is used.
[d755cbd]71
72Special Registers
[b6977f7]73=================
[d755cbd]74
[b6977f7]75The following special-purpose registers are used by RTEMS:
[d755cbd]76
[6297ad3]77*Special-Purpose Register General 0 (SPRG0)*
[b6977f7]78    In SMP configurations, this register contains the address of the per-CPU
[6297ad3]79    control of the processor.
80
81*Special-Purpose Register General 1 (SPRG1)*
82    This register contains the interrupt stack pointer for the outer-most
83    interrupt service routine.
84
85*Special-Purpose Register General 2 (SPRG2)*
86    This register contains the address of interrupt stack area begin.
87
[d755cbd]88Memory Model
89============
90
[b6977f7]91The memory model is flat.
[d755cbd]92
93Interrupt Processing
94====================
95
96Interrupt Levels
97----------------
98
[b6977f7]99There are exactly two interrupt levels on PowerPC with respect to RTEMS.  Level
100zero corresponds to interrupts enabled.  Level one corresponds to interrupts
101disabled.
[d755cbd]102
[b6977f7]103Interrupt Stack
104---------------
[d755cbd]105
[b6977f7]106The interrupt stack size can be configured via the
107``CONFIGURE_INTERRUPT_STACK_SIZE`` application configuration option.
[d755cbd]108
109Default Fatal Error Processing
110==============================
111
[b6977f7]112The default fatal error handler is BSP-specific.
[d755cbd]113
114Symmetric Multiprocessing
115=========================
116
117SMP is supported.  Available platforms are the Freescale QorIQ P series (e.g.
118P1020) and T series (e.g. T2080, T4240).
119
120Thread-Local Storage
121====================
122
123Thread-local storage is supported.
124
[b6977f7]12564-bit Caveats
126==============
[d755cbd]127
[3fdea2d]128* The thread pointer is ``r13`` in contrast to ``r2`` used in the 32-bit ABI.
[d755cbd]129
[3fdea2d]130* The TOC pointer is ``r2``.  It must be initialized as part of the C run-time
[b6977f7]131  setup.  A valid stack pointer is not enough to call C functions.  They may
132  use the TOC to get addresses and constants.
[d755cbd]133
[873ba80]134* The TOC must be within the first 2GiB of the address space.  This simplifies
[3fdea2d]135  the interrupt prologue, since the ``r2`` can be set to ``.TOC.`` via the
136  usual ``lis`` followed by ``ori`` combination.  The ``lis`` is subject to
137  sign-extension.
[d755cbd]138
[3fdea2d]139* The ``PPC_REG_LOAD``, ``PPC_REG_STORE``, ``PPC_REG_STORE_UPDATE``, and
140  ``PPC_REG_CMP`` macros are available for assembly code to provide register
141  size operations selected by the GCC ``-m32`` and ``-m64`` options.
[d755cbd]142
[3fdea2d]143* The ``MSR[CM]`` bit must be set all the time, otherwise the MMU translation
144  my yield unexpected results.  The ``EPCR[ICM]`` or ``EPCR[GICM]`` bits may be
145  used to enable the 64-bit compute mode for exceptions.
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