[e52906b] | 1 | .. SPDX-License-Identifier: CC-BY-SA-4.0 |
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[489740f] | 2 | |
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[4886d60] | 3 | .. Copyright (C) 1988, 2002 On-Line Applications Research Corporation (OAR) |
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[f233256] | 4 | |
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[d755cbd] | 5 | PowerPC Specific Information |
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[6916004] | 6 | **************************** |
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[d755cbd] | 7 | |
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| 8 | Multilibs |
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| 9 | ========= |
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| 10 | |
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| 11 | The following multilibs are available: |
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| 12 | |
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[4cc9094] | 13 | #. ``.``: 32-bit PowerPC with FPU |
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[d755cbd] | 14 | |
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[4cc9094] | 15 | #. ``nof``: 32-bit PowerPC with software floating point support |
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[d755cbd] | 16 | |
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[4cc9094] | 17 | #. ``m403``: Instruction set for PPC403 with FPU |
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[d755cbd] | 18 | |
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[4cc9094] | 19 | #. ``m505``: Instruction set for MPC505 with FPU |
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[d755cbd] | 20 | |
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[4cc9094] | 21 | #. ``m603e``: Instruction set for MPC603e with FPU |
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[d755cbd] | 22 | |
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[4cc9094] | 23 | #. ``m603e/nof``: Instruction set for MPC603e with software floating |
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| 24 | point support |
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[d755cbd] | 25 | |
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[4cc9094] | 26 | #. ``m604``: Instruction set for MPC604 with FPU |
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[d755cbd] | 27 | |
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[4cc9094] | 28 | #. ``m604/nof``: Instruction set for MPC604 with software floating point |
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| 29 | support |
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[d755cbd] | 30 | |
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[4cc9094] | 31 | #. ``m860``: Instruction set for MPC860 with FPU |
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[d755cbd] | 32 | |
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[4cc9094] | 33 | #. ``m7400``: Instruction set for MPC7500 with FPU |
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[d755cbd] | 34 | |
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[4cc9094] | 35 | #. ``m7400/nof``: Instruction set for MPC7500 with software floating |
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| 36 | point support |
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[d755cbd] | 37 | |
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[4cc9094] | 38 | #. ``m8540``: Instruction set for e200, e500 and e500v2 cores with |
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| 39 | single-precision FPU and SPE |
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[d755cbd] | 40 | |
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[4cc9094] | 41 | #. ``m8540/gprsdouble``: Instruction set for e200, e500 and e500v2 cores |
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| 42 | with double-precision FPU and SPE |
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[d755cbd] | 43 | |
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[4cc9094] | 44 | #. ``m8540/nof/nospe``: Instruction set for e200, e500 and e500v2 cores |
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| 45 | with software floating point support and no SPE |
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[d755cbd] | 46 | |
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[4cc9094] | 47 | #. ``me6500/m32``: 32-bit instruction set for e6500 core with FPU and |
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| 48 | AltiVec |
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[d755cbd] | 49 | |
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[4cc9094] | 50 | #. ``me6500/m32/nof/noaltivec``: 32-bit instruction set for e6500 core |
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| 51 | with software floating point support and no AltiVec |
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[d755cbd] | 52 | |
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[b6977f7] | 53 | #. ``me6500/m64``: 64-bit instruction set for e6500 core with FPU and |
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| 54 | AltiVec |
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[f233256] | 55 | |
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[b6977f7] | 56 | #. ``me6500/m64/nof/noaltivec``: 64-bit instruction set for e6500 core |
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| 57 | with software floating point support and no AltiVec |
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[d755cbd] | 58 | |
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[b6977f7] | 59 | Application Binary Interface |
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| 60 | ============================ |
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[d755cbd] | 61 | |
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[b6977f7] | 62 | In 32-bit PowerPC configurations the ABI defined by |
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| 63 | `Power Architecture 32-bit Application Binary Interface Supplement 1.0 - Embedded <https://ftp.rtems.org/pub/rtems/people/sebh/Power-Arch-32-bit-ABI-supp-1.0-Embedded.pdf>`_ |
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| 64 | is used. |
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[d755cbd] | 65 | |
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[b6977f7] | 66 | In 64-bit PowerPC configurations the ABI defined by |
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| 67 | `Power Architecture 64-Bit ELF V2 ABI Specification, Version 1.1 <https://ftp.rtems.org/pub/rtems/people/sebh/ABI64BitOpenPOWERv1.1_16July2015_pub.pdf>`_ |
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| 68 | is used. |
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[d755cbd] | 69 | |
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| 70 | Special Registers |
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[b6977f7] | 71 | ================= |
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[d755cbd] | 72 | |
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[b6977f7] | 73 | The following special-purpose registers are used by RTEMS: |
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[d755cbd] | 74 | |
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[6297ad3] | 75 | *Special-Purpose Register General 0 (SPRG0)* |
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[b6977f7] | 76 | In SMP configurations, this register contains the address of the per-CPU |
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[6297ad3] | 77 | control of the processor. |
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| 78 | |
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| 79 | *Special-Purpose Register General 1 (SPRG1)* |
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| 80 | This register contains the interrupt stack pointer for the outer-most |
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| 81 | interrupt service routine. |
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| 82 | |
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| 83 | *Special-Purpose Register General 2 (SPRG2)* |
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| 84 | This register contains the address of interrupt stack area begin. |
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| 85 | |
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[d755cbd] | 86 | Memory Model |
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| 87 | ============ |
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| 88 | |
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[b6977f7] | 89 | The memory model is flat. |
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[d755cbd] | 90 | |
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| 91 | Interrupt Processing |
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| 92 | ==================== |
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| 93 | |
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| 94 | Interrupt Levels |
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| 95 | ---------------- |
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| 96 | |
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[b6977f7] | 97 | There are exactly two interrupt levels on PowerPC with respect to RTEMS. Level |
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| 98 | zero corresponds to interrupts enabled. Level one corresponds to interrupts |
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| 99 | disabled. |
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[d755cbd] | 100 | |
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[b6977f7] | 101 | Interrupt Stack |
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| 102 | --------------- |
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[d755cbd] | 103 | |
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[b6977f7] | 104 | The interrupt stack size can be configured via the |
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| 105 | ``CONFIGURE_INTERRUPT_STACK_SIZE`` application configuration option. |
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[d755cbd] | 106 | |
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| 107 | Default Fatal Error Processing |
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| 108 | ============================== |
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| 109 | |
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[b6977f7] | 110 | The default fatal error handler is BSP-specific. |
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[d755cbd] | 111 | |
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| 112 | Symmetric Multiprocessing |
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| 113 | ========================= |
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| 114 | |
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| 115 | SMP is supported. Available platforms are the Freescale QorIQ P series (e.g. |
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| 116 | P1020) and T series (e.g. T2080, T4240). |
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| 117 | |
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| 118 | Thread-Local Storage |
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| 119 | ==================== |
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| 120 | |
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| 121 | Thread-local storage is supported. |
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| 122 | |
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[b6977f7] | 123 | 64-bit Caveats |
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| 124 | ============== |
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[d755cbd] | 125 | |
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[3fdea2d] | 126 | * The thread pointer is ``r13`` in contrast to ``r2`` used in the 32-bit ABI. |
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[d755cbd] | 127 | |
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[3fdea2d] | 128 | * The TOC pointer is ``r2``. It must be initialized as part of the C run-time |
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[b6977f7] | 129 | setup. A valid stack pointer is not enough to call C functions. They may |
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| 130 | use the TOC to get addresses and constants. |
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[d755cbd] | 131 | |
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[873ba80] | 132 | * The TOC must be within the first 2GiB of the address space. This simplifies |
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[3fdea2d] | 133 | the interrupt prologue, since the ``r2`` can be set to ``.TOC.`` via the |
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| 134 | usual ``lis`` followed by ``ori`` combination. The ``lis`` is subject to |
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| 135 | sign-extension. |
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[d755cbd] | 136 | |
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[3fdea2d] | 137 | * The ``PPC_REG_LOAD``, ``PPC_REG_STORE``, ``PPC_REG_STORE_UPDATE``, and |
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| 138 | ``PPC_REG_CMP`` macros are available for assembly code to provide register |
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| 139 | size operations selected by the GCC ``-m32`` and ``-m64`` options. |
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[d755cbd] | 140 | |
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[3fdea2d] | 141 | * The ``MSR[CM]`` bit must be set all the time, otherwise the MMU translation |
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| 142 | my yield unexpected results. The ``EPCR[ICM]`` or ``EPCR[GICM]`` bits may be |
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| 143 | used to enable the 64-bit compute mode for exceptions. |
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