[489740f] | 1 | .. comment SPDX-License-Identifier: CC-BY-SA-4.0 |
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| 2 | |
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[f233256] | 3 | .. COMMENT: COPYRIGHT (c) 1988-2002. |
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| 4 | .. COMMENT: On-Line Applications Research Corporation (OAR). |
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| 5 | .. COMMENT: All rights reserved. |
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| 6 | |
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[d755cbd] | 7 | Port Specific Information |
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| 8 | ######################### |
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| 9 | |
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[f233256] | 10 | This chaper provides a general description of the type of architecture specific |
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| 11 | information which is in each of the architecture specific chapters that follow. |
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| 12 | The outline of this chapter is identical to that of the architecture specific |
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| 13 | chapters. |
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[d755cbd] | 14 | |
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[f233256] | 15 | In each of the architecture specific chapters, this introductory section will |
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| 16 | provide an overview of the architecture: |
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[d755cbd] | 17 | |
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| 18 | **Architecture Documents** |
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| 19 | |
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[f233256] | 20 | In each of the architecture specific chapters, this section will provide |
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| 21 | pointers on where to obtain documentation. |
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[d755cbd] | 22 | |
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| 23 | CPU Model Dependent Features |
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| 24 | ============================ |
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| 25 | |
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[f233256] | 26 | Microprocessors are generally classified into families with a variety of CPU |
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| 27 | models or implementations within that family. Within a processor family, there |
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| 28 | is a high level of binary compatibility. This family may be based on either an |
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| 29 | architectural specification or on maintaining compatibility with a popular |
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| 30 | processor. Recent microprocessor families such as the SPARC or PowerPC are |
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| 31 | based on an architectural specification which is independent or any particular |
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| 32 | CPU model or implementation. Older families such as the Motorola 68000 and the |
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| 33 | Intel x86 evolved as the manufacturer strived to produce higher performance |
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| 34 | processor models which maintained binary compatibility with older models. |
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| 35 | |
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| 36 | RTEMS takes advantage of the similarity of the various models within a CPU |
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| 37 | family. Although the models do vary in significant ways, the high level of |
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| 38 | compatibility makes it possible to share the bulk of the CPU dependent |
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| 39 | executive code across the entire family. Each processor family supported by |
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| 40 | RTEMS has a list of features which vary between CPU models within a family. |
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| 41 | For example, the most common model dependent feature regardless of CPU family |
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| 42 | is the presence or absence of a floating point unit or coprocessor. When |
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| 43 | defining the list of features present on a particular CPU model, one simply |
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| 44 | notes that floating point hardware is or is not present and defines a single |
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| 45 | constant appropriately. Conditional compilation is utilized to include the |
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| 46 | appropriate source code for this CPU model's feature set. It is important to |
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| 47 | note that this means that RTEMS is thus compiled using the appropriate feature |
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| 48 | set and compilation flags optimal for this CPU model used. The alternative |
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| 49 | would be to generate a binary which would execute on all family members using |
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| 50 | only the features which were always present. |
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| 51 | |
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| 52 | The set of CPU model feature macros are defined in the |
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| 53 | :file:`cpukit/score/cpu/CPU/rtems/score/cpu.h` based upon the GNU tools |
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| 54 | multilib variant that is appropriate for the particular CPU model defined on |
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| 55 | the compilation command line. |
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| 56 | |
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| 57 | In each of the architecture specific chapters, this section presents the set of |
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| 58 | features which vary across various implementations of the architecture that may |
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| 59 | be of importance to RTEMS application developers. |
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| 60 | |
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| 61 | The subsections will vary amongst the target architecture chapters as the |
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| 62 | specific features may vary. However, each port will include a few common |
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| 63 | features such as the CPU Model Name and presence of a hardware Floating Point |
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| 64 | Unit. The common features are described here. |
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[d755cbd] | 65 | |
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| 66 | CPU Model Name |
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| 67 | -------------- |
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| 68 | |
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[f233256] | 69 | The macro ``CPU_MODEL_NAME`` is a string which designates the name of this CPU |
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| 70 | model. For example, for the MC68020 processor model from the m68k |
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| 71 | architecture, this macro is set to the string "mc68020". |
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[d755cbd] | 72 | |
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| 73 | Floating Point Unit |
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| 74 | ------------------- |
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| 75 | |
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[f233256] | 76 | In most architectures, the presence of a floating point unit is an option. It |
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| 77 | does not matter whether the hardware floating point support is incorporated |
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| 78 | on-chip or is an external coprocessor as long as it appears an FPU per the ISA. |
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| 79 | However, if a hardware FPU is not present, it is possible that the floating |
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| 80 | point emulation library for this CPU is not reentrant and thus context switched |
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| 81 | by RTEMS. |
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[d755cbd] | 82 | |
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| 83 | RTEMS provides two feature macros to indicate the FPU configuration: |
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| 84 | |
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| 85 | - CPU_HARDWARE_FP |
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| 86 | is set to TRUE to indicate that a hardware FPU is present. |
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| 87 | |
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| 88 | - CPU_SOFTWARE_FP |
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[f233256] | 89 | is set to TRUE to indicate that a hardware FPU is not present and that the FP |
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| 90 | software emulation will be context switched. |
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[d755cbd] | 91 | |
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| 92 | Multilibs |
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| 93 | ========= |
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| 94 | |
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[f233256] | 95 | Newlib and GCC provide several target libraries like the :file:`libc.a`, |
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| 96 | :file:`libm.a` and :file:`libgcc.a`. These libraries are artifacts of the GCC |
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[d755cbd] | 97 | build process. Newlib is built together with GCC. To provide optimal support |
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| 98 | for various chip derivatives and instruction set revisions multiple variants of |
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| 99 | these libraries are available for each architecture. For example one set may |
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| 100 | use software floating point support and another set may use hardware floating |
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| 101 | point instructions. These sets of libraries are called *multilibs*. Each |
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| 102 | library set corresponds to an application binary interface (ABI) and |
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| 103 | instruction set. |
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| 104 | |
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| 105 | A multilib variant can be usually detected via built-in compiler defines at |
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| 106 | compile-time. This mechanism is used by RTEMS to select for example the |
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| 107 | context switch support for a particular BSP. The built-in compiler defines |
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| 108 | corresponding to multilibs are the only architecture specific defines allowed |
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| 109 | in the ``cpukit`` area of the RTEMS sources. |
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| 110 | |
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| 111 | Invoking the GCC with the ``-print-multi-lib`` option lists the available |
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| 112 | multilibs. Each line of the output describes one multilib variant. The |
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[f233256] | 113 | default variant is denoted by ``.`` which is selected when no or contradicting |
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| 114 | GCC machine options are selected. The multilib selection for a target is |
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| 115 | specified by target makefile fragments (see file :file:`t-rtems` in the GCC |
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| 116 | sources and section *The Target Makefile Fragment* |
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| 117 | (https://gcc.gnu.org/onlinedocs/gccint/Target-Fragment.html#Target-Fragment) |
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| 118 | in the *GCC Internals Manual* (https://gcc.gnu.org/onlinedocs/gccint/). |
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[d755cbd] | 119 | |
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| 120 | Calling Conventions |
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| 121 | =================== |
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| 122 | |
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[f233256] | 123 | Each high-level language compiler generates subroutine entry and exit code |
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| 124 | based upon a set of rules known as the compiler's calling convention. These |
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| 125 | rules address the following issues: |
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[d755cbd] | 126 | |
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| 127 | - register preservation and usage |
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| 128 | |
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| 129 | - parameter passing |
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| 130 | |
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| 131 | - call and return mechanism |
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| 132 | |
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[f233256] | 133 | A compiler's calling convention is of importance when interfacing to |
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| 134 | subroutines written in another language either assembly or high-level. Even |
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| 135 | when the high-level language and target processor are the same, different |
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| 136 | compilers may use different calling conventions. As a result, calling |
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| 137 | conventions are both processor and compiler dependent. |
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[d755cbd] | 138 | |
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| 139 | Calling Mechanism |
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| 140 | ----------------- |
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| 141 | |
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[f233256] | 142 | In each of the architecture specific chapters, this subsection will describe |
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| 143 | the instruction(s) used to perform a *normal* subroutine invocation. All RTEMS |
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| 144 | directives are invoked as *normal* C language functions so it is important to |
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| 145 | the user application to understand the call and return mechanism. |
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[d755cbd] | 146 | |
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| 147 | Register Usage |
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| 148 | -------------- |
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| 149 | |
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[f233256] | 150 | In each of the architecture specific chapters, this subsection will detail the |
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| 151 | set of registers which are *NOT* preserved across subroutine invocations. The |
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| 152 | registers which are not preserved are assumed to be available for use as |
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| 153 | scratch registers. Therefore, the contents of these registers should not be |
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| 154 | assumed upon return from any RTEMS directive. |
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[d755cbd] | 155 | |
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| 156 | In some architectures, there may be a set of registers made available |
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[f233256] | 157 | automatically as a side-effect of the subroutine invocation mechanism. |
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[d755cbd] | 158 | |
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| 159 | Parameter Passing |
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| 160 | ----------------- |
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| 161 | |
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[f233256] | 162 | In each of the architecture specific chapters, this subsection will describe |
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| 163 | the mechanism by which the parameters or arguments are passed by the caller to |
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| 164 | a subroutine. In some architectures, all parameters are passed on the stack |
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| 165 | while in others some are passed in registers. |
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[d755cbd] | 166 | |
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| 167 | User-Provided Routines |
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| 168 | ---------------------- |
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| 169 | |
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[f233256] | 170 | All user-provided routines invoked by RTEMS, such as user extensions, device |
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| 171 | drivers, and MPCI routines, must also adhere to these calling conventions. |
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[d755cbd] | 172 | |
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| 173 | Memory Model |
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| 174 | ============ |
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| 175 | |
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[f233256] | 176 | A processor may support any combination of memory models ranging from pure |
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| 177 | physical addressing to complex demand paged virtual memory systems. RTEMS |
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| 178 | supports a flat memory model which ranges contiguously over the processor's |
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| 179 | allowable address space. RTEMS does not support segmentation or virtual memory |
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| 180 | of any kind. The appropriate memory model for RTEMS provided by the targeted |
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| 181 | processor and related characteristics of that model are described in this |
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| 182 | chapter. |
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[d755cbd] | 183 | |
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| 184 | Flat Memory Model |
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| 185 | ----------------- |
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| 186 | |
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| 187 | Most RTEMS target processors can be initialized to support a flat address |
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[f233256] | 188 | space. Although the size of addresses varies between architectures, on most |
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| 189 | RTEMS targets, an address is 32-bits wide which defines addresses ranging from |
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| 190 | 0x00000000 to 0xFFFFFFFF (4 gigabytes). Each address is represented by a |
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| 191 | 32-bit value and is byte addressable. The address may be used to reference a |
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| 192 | single byte, word (2-bytes), or long word (4 bytes). Memory accesses within |
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| 193 | this address space may be performed in little or big endian fashion. |
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| 194 | |
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| 195 | On smaller CPU architectures supported by RTEMS, the address space may only be |
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| 196 | 20 or 24 bits wide. |
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| 197 | |
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| 198 | If the CPU model has support for virtual memory or segmentation, it is the |
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| 199 | responsibility of the Board Support Package (BSP) to initialize the MMU |
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| 200 | hardware to perform address translations which correspond to flat memory model. |
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| 201 | |
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| 202 | In each of the architecture specific chapters, this subsection will describe |
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| 203 | any architecture characteristics that differ from this general description. |
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[d755cbd] | 204 | |
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| 205 | Interrupt Processing |
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| 206 | ==================== |
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| 207 | |
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[f233256] | 208 | Different types of processors respond to the occurrence of an interrupt in its |
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| 209 | own unique fashion. In addition, each processor type provides a control |
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| 210 | mechanism to allow for the proper handling of an interrupt. The processor |
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| 211 | dependent response to the interrupt modifies the current execution state and |
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| 212 | results in a change in the execution stream. Most processors require that an |
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| 213 | interrupt handler utilize some special control mechanisms to return to the |
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| 214 | normal processing stream. Although RTEMS hides many of the processor dependent |
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| 215 | details of interrupt processing, it is important to understand how the RTEMS |
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| 216 | interrupt manager is mapped onto the processor's unique architecture. |
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| 217 | |
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| 218 | RTEMS supports a dedicated interrupt stack for all architectures. On |
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| 219 | architectures with hardware support for a dedicated interrupt stack, it will be |
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| 220 | initialized such that when an interrupt occurs, the processor automatically |
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| 221 | switches to this dedicated stack. On architectures without hardware support |
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| 222 | for a dedicated interrupt stack which is separate from those of the tasks, |
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| 223 | RTEMS will support switching to a dedicated stack for interrupt processing. |
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| 224 | |
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| 225 | Without a dedicated interrupt stack, every task in the system MUST have enough |
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| 226 | stack space to accommodate the worst case stack usage of that particular task |
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| 227 | and the interrupt service routines COMBINED. By supporting a dedicated |
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| 228 | interrupt stack, RTEMS significantly lowers the stack requirements for each |
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| 229 | task. |
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| 230 | |
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| 231 | A nested interrupt is processed similarly with the exception that since the CPU |
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| 232 | is already executing on the interrupt stack, there is no need to switch to the |
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| 233 | interrupt stack. |
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| 234 | |
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| 235 | In some configurations, RTEMS allocates the interrupt stack from the Workspace |
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| 236 | Area. The amount of memory allocated for the interrupt stack is user |
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| 237 | configured and based upon the ``confdefs.h`` parameter |
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| 238 | ``CONFIGURE_INTERRUPT_STACK_SIZE``. This parameter is described in detail in |
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| 239 | the Configuring a System chapter of the User's Guide. On configurations in |
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| 240 | which RTEMS allocates the interrupt stack, during the initialization process, |
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| 241 | RTEMS will also install its interrupt stack. In other configurations, the |
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| 242 | interrupt stack is allocated and installed by the Board Support Package (BSP). |
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| 243 | |
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| 244 | In each of the architecture specific chapters, this section discesses the |
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| 245 | interrupt response and control mechanisms of the architecture as they pertain |
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| 246 | to RTEMS. |
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[d755cbd] | 247 | |
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| 248 | Vectoring of an Interrupt Handler |
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| 249 | --------------------------------- |
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| 250 | |
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[f233256] | 251 | In each of the architecture specific chapters, this subsection will describe |
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| 252 | the architecture specific details of the interrupt vectoring process. In |
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| 253 | particular, it should include a description of the Interrupt Stack Frame (ISF). |
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[d755cbd] | 254 | |
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| 255 | Interrupt Levels |
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| 256 | ---------------- |
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| 257 | |
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[f233256] | 258 | In each of the architecture specific chapters, this subsection will describe |
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| 259 | how the interrupt levels available on this particular architecture are mapped |
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| 260 | onto the 255 reserved in the task mode. The interrupt level value of zero (0) |
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| 261 | should always mean that interrupts are enabled. |
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[d755cbd] | 262 | |
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[f233256] | 263 | Any use of an interrupt level that is is not undefined on a particular |
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[d755cbd] | 264 | architecture may result in behavior that is unpredictable. |
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| 265 | |
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| 266 | Disabling of Interrupts by RTEMS |
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| 267 | -------------------------------- |
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| 268 | |
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[f233256] | 269 | During the execution of directive calls, critical sections of code may be |
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| 270 | executed. When these sections are encountered, RTEMS disables all external |
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| 271 | interrupts before the execution of this section and restores them to the |
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| 272 | previous level upon completion of the section. RTEMS has been optimized to |
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| 273 | ensure that interrupts are disabled for the shortest number of instructions |
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| 274 | possible. Since the precise number of instructions and their execution time |
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| 275 | varies based upon target CPU family, CPU model, board memory speed, compiler |
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| 276 | version, and optimization level, it is not practical to provide the precise |
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| 277 | number for all possible RTEMS configurations. |
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| 278 | |
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| 279 | Historically, the measurements were made by hand analyzing and counting the |
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| 280 | execution time of instruction sequences during interrupt disable critical |
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| 281 | sections. For reference purposes, on a 16 Mhz Motorola MC68020, the maximum |
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| 282 | interrupt disable period was typically approximately ten (10) to thirteen (13) |
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| 283 | microseconds. This architecture was memory bound and had a slow bit scan |
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| 284 | instruction. In contrast, during the same period a 14 Mhz SPARC would have a |
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| 285 | worst case disable time of approximately two (2) to three (3) microseconds |
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| 286 | because it had a single cycle bit scan instruction and used fewer cycles for |
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| 287 | memory accesses. |
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| 288 | |
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| 289 | If you are interested in knowing the worst case execution time for a particular |
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| 290 | version of RTEMS, please contact OAR Corporation and we will be happy to |
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| 291 | product the results as a consulting service. |
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| 292 | |
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| 293 | Non-maskable interrupts (NMI) cannot be disabled, and ISRs which execute at |
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| 294 | this level MUST NEVER issue RTEMS system calls. If a directive is invoked, |
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| 295 | unpredictable results may occur due to the inability of RTEMS to protect its |
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| 296 | critical sections. However, ISRs that make no system calls may safely execute |
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| 297 | as non-maskable interrupts. |
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[d755cbd] | 298 | |
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| 299 | Default Fatal Error Processing |
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| 300 | ============================== |
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| 301 | |
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| 302 | Upon detection of a fatal error by either the application or RTEMS during |
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[f233256] | 303 | initialization the ``rtems_fatal_error_occurred`` directive supplied by the |
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| 304 | Fatal Error Manager is invoked. The Fatal Error Manager will invoke the |
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| 305 | user-supplied fatal error handlers. If no user-supplied handlers are |
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| 306 | configured or all of them return without taking action to shutdown the |
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| 307 | processor or reset, a default fatal error handler is invoked. |
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[d755cbd] | 308 | |
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| 309 | Most of the action performed as part of processing the fatal error are |
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[f233256] | 310 | described in detail in the Fatal Error Manager chapter in the User's Guide. |
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| 311 | However, the if no user provided extension or BSP specific fatal error handler |
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| 312 | takes action, the final default action is to invoke a CPU architecture specific |
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| 313 | function. Typically this function disables interrupts and halts the processor. |
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[d755cbd] | 314 | |
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| 315 | In each of the architecture specific chapters, this describes the precise |
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| 316 | operations of the default CPU specific fatal error handler. |
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| 317 | |
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| 318 | Symmetric Multiprocessing |
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| 319 | ========================= |
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| 320 | |
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| 321 | This section contains information about the Symmetric Multiprocessing (SMP) |
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| 322 | status of a particular architecture. |
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| 323 | |
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| 324 | Thread-Local Storage |
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| 325 | ==================== |
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| 326 | |
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| 327 | In order to support thread-local storage (TLS) the CPU port must implement the |
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| 328 | facilities mandated by the application binary interface (ABI) of the CPU |
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[f233256] | 329 | architecture. The CPU port must initialize the TLS area in the |
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| 330 | ``_CPU_Context_Initialize()`` function. There are support functions available |
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[d755cbd] | 331 | via ``#include <rtems/score/tls.h>`` which implement Variants I and II |
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| 332 | according to Ulrich Drepper, *ELF Handling For Thread-Local Storage*. |
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| 333 | |
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| 334 | ``_TLS_TCB_at_area_begin_initialize()`` |
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[f233256] | 335 | Uses Variant I, TLS offsets emitted by linker takes the TCB into account. |
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| 336 | For a reference implementation see :file:`cpukit/score/cpu/arm/cpu.c`. |
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[d755cbd] | 337 | |
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| 338 | ``_TLS_TCB_before_TLS_block_initialize()`` |
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| 339 | Uses Variant I, TLS offsets emitted by linker neglects the TCB. For a |
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[f233256] | 340 | reference implementation see |
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| 341 | :file:`c/src/lib/libcpu/powerpc/new-exceptions/cpu.c`. |
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[d755cbd] | 342 | |
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| 343 | ``_TLS_TCB_after_TLS_block_initialize()`` |
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[f233256] | 344 | Uses Variant II. For a reference implementation see |
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| 345 | :file:`cpukit/score/cpu/sparc/cpu.c`. |
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[d755cbd] | 346 | |
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| 347 | The board support package (BSP) must provide the following sections and symbols |
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| 348 | in its linker command file: |
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[f233256] | 349 | |
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| 350 | .. code-block:: c |
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[d755cbd] | 351 | |
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| 352 | .tdata : { |
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[f233256] | 353 | _TLS_Data_begin = .; |
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| 354 | *(.tdata .tdata.* .gnu.linkonce.td.*) |
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| 355 | _TLS_Data_end = .; |
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[d755cbd] | 356 | } |
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| 357 | .tbss : { |
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[f233256] | 358 | _TLS_BSS_begin = .; |
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| 359 | *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) |
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| 360 | _TLS_BSS_end = .; |
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[d755cbd] | 361 | } |
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| 362 | _TLS_Data_size = _TLS_Data_end - _TLS_Data_begin; |
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| 363 | _TLS_Data_begin = _TLS_Data_size != 0 ? _TLS_Data_begin : _TLS_BSS_begin; |
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| 364 | _TLS_Data_end = _TLS_Data_size != 0 ? _TLS_Data_end : _TLS_BSS_begin; |
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| 365 | _TLS_BSS_size = _TLS_BSS_end - _TLS_BSS_begin; |
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| 366 | _TLS_Size = _TLS_BSS_end - _TLS_Data_begin; |
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| 367 | _TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss)); |
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| 368 | |
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| 369 | CPU counter |
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| 370 | =========== |
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| 371 | |
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| 372 | The CPU support must implement the CPU counter interface. A CPU counter is |
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| 373 | some free-running counter. It ticks usually with a frequency close to the CPU |
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| 374 | or system bus clock. On some architectures the actual implementation is board |
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| 375 | support package dependent. The CPU counter is used for profiling of low-level |
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[f233256] | 376 | functions. It is also used to implement two busy wait functions |
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| 377 | ``rtems_counter_delay_ticks()`` and ``rtems_counter_delay_nanoseconds()`` which |
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| 378 | may be used in device drivers. It may be also used as an entropy source for |
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| 379 | random number generators. |
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[d755cbd] | 380 | |
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[f233256] | 381 | The CPU counter interface uses a CPU port specific unsigned integer type |
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| 382 | ``CPU_Counter_ticks`` to represent CPU counter values. The CPU port must |
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[d755cbd] | 383 | provide the following two functions |
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| 384 | |
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| 385 | - ``_CPU_Counter_read()`` to read the current CPU counter value, and |
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| 386 | |
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| 387 | - ``_CPU_Counter_difference()`` to get the difference between two CPU |
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| 388 | counter values. |
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| 389 | |
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| 390 | Interrupt Profiling |
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| 391 | =================== |
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| 392 | |
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| 393 | The RTEMS profiling needs support by the CPU port for the interrupt entry and |
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| 394 | exit times. In case profiling is enabled via the RTEMS build configuration |
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[f233256] | 395 | option ``--enable-profiling`` (in this case the pre-processor symbol |
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| 396 | ``RTEMS_PROFILING`` is defined) the CPU port may provide data for the interrupt |
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| 397 | entry and exit times of the outer-most interrupt. The CPU port can feed |
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| 398 | interrupt entry and exit times with the |
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| 399 | ``_Profiling_Outer_most_interrupt_entry_and_exit()`` function (``#include |
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| 400 | <rtems/score/profiling.h>``). For an example please have a look at |
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| 401 | :file:`cpukit/score/cpu/arm/arm_exc_interrupt.S`. |
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[d755cbd] | 402 | |
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| 403 | Board Support Packages |
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| 404 | ====================== |
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| 405 | |
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[f233256] | 406 | An RTEMS Board Support Package (BSP) must be designed to support a particular |
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| 407 | processor model and target board combination. |
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[d755cbd] | 408 | |
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[f233256] | 409 | In each of the architecture specific chapters, this section will present a |
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| 410 | discussion of architecture specific BSP issues. For more information on |
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| 411 | developing a BSP, refer to BSP and Device Driver Development Guide and the |
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| 412 | chapter titled Board Support Packages in the RTEMS Applications User's Guide. |
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[d755cbd] | 413 | |
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| 414 | System Reset |
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| 415 | ------------ |
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| 416 | |
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[f233256] | 417 | An RTEMS based application is initiated or re-initiated when the processor is |
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| 418 | reset or transfer is passed to it from a boot monitor or ROM monitor. |
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[d755cbd] | 419 | |
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[f233256] | 420 | In each of the architecture specific chapters, this subsection describes the |
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| 421 | actions that the BSP must tak assuming the application gets control when the |
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| 422 | microprocessor is reset. |
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