[e52906b] | 1 | .. SPDX-License-Identifier: CC-BY-SA-4.0 |
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[489740f] | 2 | |
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[4886d60] | 3 | .. Copyright (C) 1988, 2002 On-Line Applications Research Corporation (OAR) |
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[f233256] | 4 | |
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[d755cbd] | 5 | Port Specific Information |
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[6916004] | 6 | ************************* |
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[d755cbd] | 7 | |
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[f233256] | 8 | This chaper provides a general description of the type of architecture specific |
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| 9 | information which is in each of the architecture specific chapters that follow. |
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| 10 | The outline of this chapter is identical to that of the architecture specific |
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| 11 | chapters. |
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[d755cbd] | 12 | |
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[f233256] | 13 | In each of the architecture specific chapters, this introductory section will |
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| 14 | provide an overview of the architecture: |
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[d755cbd] | 15 | |
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| 16 | **Architecture Documents** |
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| 17 | |
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[f233256] | 18 | In each of the architecture specific chapters, this section will provide |
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| 19 | pointers on where to obtain documentation. |
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[d755cbd] | 20 | |
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| 21 | CPU Model Dependent Features |
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| 22 | ============================ |
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| 23 | |
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[f233256] | 24 | Microprocessors are generally classified into families with a variety of CPU |
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| 25 | models or implementations within that family. Within a processor family, there |
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| 26 | is a high level of binary compatibility. This family may be based on either an |
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| 27 | architectural specification or on maintaining compatibility with a popular |
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| 28 | processor. Recent microprocessor families such as the SPARC or PowerPC are |
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| 29 | based on an architectural specification which is independent or any particular |
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| 30 | CPU model or implementation. Older families such as the Motorola 68000 and the |
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| 31 | Intel x86 evolved as the manufacturer strived to produce higher performance |
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| 32 | processor models which maintained binary compatibility with older models. |
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| 33 | |
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| 34 | RTEMS takes advantage of the similarity of the various models within a CPU |
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| 35 | family. Although the models do vary in significant ways, the high level of |
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| 36 | compatibility makes it possible to share the bulk of the CPU dependent |
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| 37 | executive code across the entire family. Each processor family supported by |
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| 38 | RTEMS has a list of features which vary between CPU models within a family. |
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| 39 | For example, the most common model dependent feature regardless of CPU family |
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| 40 | is the presence or absence of a floating point unit or coprocessor. When |
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| 41 | defining the list of features present on a particular CPU model, one simply |
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| 42 | notes that floating point hardware is or is not present and defines a single |
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| 43 | constant appropriately. Conditional compilation is utilized to include the |
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| 44 | appropriate source code for this CPU model's feature set. It is important to |
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| 45 | note that this means that RTEMS is thus compiled using the appropriate feature |
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| 46 | set and compilation flags optimal for this CPU model used. The alternative |
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| 47 | would be to generate a binary which would execute on all family members using |
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| 48 | only the features which were always present. |
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| 49 | |
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| 50 | The set of CPU model feature macros are defined in the |
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| 51 | :file:`cpukit/score/cpu/CPU/rtems/score/cpu.h` based upon the GNU tools |
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| 52 | multilib variant that is appropriate for the particular CPU model defined on |
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| 53 | the compilation command line. |
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| 54 | |
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| 55 | In each of the architecture specific chapters, this section presents the set of |
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| 56 | features which vary across various implementations of the architecture that may |
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| 57 | be of importance to RTEMS application developers. |
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| 58 | |
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| 59 | The subsections will vary amongst the target architecture chapters as the |
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| 60 | specific features may vary. However, each port will include a few common |
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| 61 | features such as the CPU Model Name and presence of a hardware Floating Point |
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| 62 | Unit. The common features are described here. |
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[d755cbd] | 63 | |
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| 64 | CPU Model Name |
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| 65 | -------------- |
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| 66 | |
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[f233256] | 67 | The macro ``CPU_MODEL_NAME`` is a string which designates the name of this CPU |
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| 68 | model. For example, for the MC68020 processor model from the m68k |
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| 69 | architecture, this macro is set to the string "mc68020". |
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[d755cbd] | 70 | |
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| 71 | Floating Point Unit |
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| 72 | ------------------- |
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| 73 | |
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[f233256] | 74 | In most architectures, the presence of a floating point unit is an option. It |
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| 75 | does not matter whether the hardware floating point support is incorporated |
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| 76 | on-chip or is an external coprocessor as long as it appears an FPU per the ISA. |
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| 77 | However, if a hardware FPU is not present, it is possible that the floating |
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| 78 | point emulation library for this CPU is not reentrant and thus context switched |
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| 79 | by RTEMS. |
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[d755cbd] | 80 | |
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| 81 | RTEMS provides two feature macros to indicate the FPU configuration: |
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| 82 | |
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| 83 | - CPU_HARDWARE_FP |
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| 84 | is set to TRUE to indicate that a hardware FPU is present. |
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| 85 | |
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| 86 | - CPU_SOFTWARE_FP |
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[f233256] | 87 | is set to TRUE to indicate that a hardware FPU is not present and that the FP |
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| 88 | software emulation will be context switched. |
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[d755cbd] | 89 | |
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| 90 | Multilibs |
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| 91 | ========= |
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| 92 | |
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[f233256] | 93 | Newlib and GCC provide several target libraries like the :file:`libc.a`, |
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| 94 | :file:`libm.a` and :file:`libgcc.a`. These libraries are artifacts of the GCC |
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[d755cbd] | 95 | build process. Newlib is built together with GCC. To provide optimal support |
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| 96 | for various chip derivatives and instruction set revisions multiple variants of |
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| 97 | these libraries are available for each architecture. For example one set may |
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| 98 | use software floating point support and another set may use hardware floating |
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| 99 | point instructions. These sets of libraries are called *multilibs*. Each |
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| 100 | library set corresponds to an application binary interface (ABI) and |
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| 101 | instruction set. |
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| 102 | |
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| 103 | A multilib variant can be usually detected via built-in compiler defines at |
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| 104 | compile-time. This mechanism is used by RTEMS to select for example the |
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| 105 | context switch support for a particular BSP. The built-in compiler defines |
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| 106 | corresponding to multilibs are the only architecture specific defines allowed |
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| 107 | in the ``cpukit`` area of the RTEMS sources. |
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| 108 | |
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| 109 | Invoking the GCC with the ``-print-multi-lib`` option lists the available |
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| 110 | multilibs. Each line of the output describes one multilib variant. The |
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[f233256] | 111 | default variant is denoted by ``.`` which is selected when no or contradicting |
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| 112 | GCC machine options are selected. The multilib selection for a target is |
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| 113 | specified by target makefile fragments (see file :file:`t-rtems` in the GCC |
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| 114 | sources and section *The Target Makefile Fragment* |
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| 115 | (https://gcc.gnu.org/onlinedocs/gccint/Target-Fragment.html#Target-Fragment) |
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| 116 | in the *GCC Internals Manual* (https://gcc.gnu.org/onlinedocs/gccint/). |
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[d755cbd] | 117 | |
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| 118 | Calling Conventions |
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| 119 | =================== |
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| 120 | |
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[f233256] | 121 | Each high-level language compiler generates subroutine entry and exit code |
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| 122 | based upon a set of rules known as the compiler's calling convention. These |
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| 123 | rules address the following issues: |
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[d755cbd] | 124 | |
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| 125 | - register preservation and usage |
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| 126 | |
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| 127 | - parameter passing |
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| 128 | |
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| 129 | - call and return mechanism |
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| 130 | |
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[f233256] | 131 | A compiler's calling convention is of importance when interfacing to |
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| 132 | subroutines written in another language either assembly or high-level. Even |
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| 133 | when the high-level language and target processor are the same, different |
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| 134 | compilers may use different calling conventions. As a result, calling |
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| 135 | conventions are both processor and compiler dependent. |
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[d755cbd] | 136 | |
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| 137 | Calling Mechanism |
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| 138 | ----------------- |
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| 139 | |
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[f233256] | 140 | In each of the architecture specific chapters, this subsection will describe |
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| 141 | the instruction(s) used to perform a *normal* subroutine invocation. All RTEMS |
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| 142 | directives are invoked as *normal* C language functions so it is important to |
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| 143 | the user application to understand the call and return mechanism. |
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[d755cbd] | 144 | |
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| 145 | Register Usage |
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| 146 | -------------- |
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| 147 | |
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[f233256] | 148 | In each of the architecture specific chapters, this subsection will detail the |
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| 149 | set of registers which are *NOT* preserved across subroutine invocations. The |
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| 150 | registers which are not preserved are assumed to be available for use as |
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| 151 | scratch registers. Therefore, the contents of these registers should not be |
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| 152 | assumed upon return from any RTEMS directive. |
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[d755cbd] | 153 | |
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| 154 | In some architectures, there may be a set of registers made available |
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[f233256] | 155 | automatically as a side-effect of the subroutine invocation mechanism. |
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[d755cbd] | 156 | |
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| 157 | Parameter Passing |
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| 158 | ----------------- |
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| 159 | |
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[f233256] | 160 | In each of the architecture specific chapters, this subsection will describe |
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| 161 | the mechanism by which the parameters or arguments are passed by the caller to |
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| 162 | a subroutine. In some architectures, all parameters are passed on the stack |
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| 163 | while in others some are passed in registers. |
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[d755cbd] | 164 | |
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| 165 | User-Provided Routines |
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| 166 | ---------------------- |
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| 167 | |
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[f233256] | 168 | All user-provided routines invoked by RTEMS, such as user extensions, device |
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| 169 | drivers, and MPCI routines, must also adhere to these calling conventions. |
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[d755cbd] | 170 | |
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| 171 | Memory Model |
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| 172 | ============ |
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| 173 | |
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[f233256] | 174 | A processor may support any combination of memory models ranging from pure |
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| 175 | physical addressing to complex demand paged virtual memory systems. RTEMS |
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| 176 | supports a flat memory model which ranges contiguously over the processor's |
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| 177 | allowable address space. RTEMS does not support segmentation or virtual memory |
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| 178 | of any kind. The appropriate memory model for RTEMS provided by the targeted |
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| 179 | processor and related characteristics of that model are described in this |
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| 180 | chapter. |
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[d755cbd] | 181 | |
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| 182 | Flat Memory Model |
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| 183 | ----------------- |
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| 184 | |
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| 185 | Most RTEMS target processors can be initialized to support a flat address |
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[f233256] | 186 | space. Although the size of addresses varies between architectures, on most |
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| 187 | RTEMS targets, an address is 32-bits wide which defines addresses ranging from |
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| 188 | 0x00000000 to 0xFFFFFFFF (4 gigabytes). Each address is represented by a |
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| 189 | 32-bit value and is byte addressable. The address may be used to reference a |
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| 190 | single byte, word (2-bytes), or long word (4 bytes). Memory accesses within |
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| 191 | this address space may be performed in little or big endian fashion. |
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| 192 | |
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| 193 | On smaller CPU architectures supported by RTEMS, the address space may only be |
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| 194 | 20 or 24 bits wide. |
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| 195 | |
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| 196 | If the CPU model has support for virtual memory or segmentation, it is the |
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| 197 | responsibility of the Board Support Package (BSP) to initialize the MMU |
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| 198 | hardware to perform address translations which correspond to flat memory model. |
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| 199 | |
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| 200 | In each of the architecture specific chapters, this subsection will describe |
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| 201 | any architecture characteristics that differ from this general description. |
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[d755cbd] | 202 | |
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| 203 | Interrupt Processing |
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| 204 | ==================== |
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| 205 | |
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[f233256] | 206 | Different types of processors respond to the occurrence of an interrupt in its |
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| 207 | own unique fashion. In addition, each processor type provides a control |
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| 208 | mechanism to allow for the proper handling of an interrupt. The processor |
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| 209 | dependent response to the interrupt modifies the current execution state and |
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| 210 | results in a change in the execution stream. Most processors require that an |
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| 211 | interrupt handler utilize some special control mechanisms to return to the |
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| 212 | normal processing stream. Although RTEMS hides many of the processor dependent |
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| 213 | details of interrupt processing, it is important to understand how the RTEMS |
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| 214 | interrupt manager is mapped onto the processor's unique architecture. |
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| 215 | |
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| 216 | RTEMS supports a dedicated interrupt stack for all architectures. On |
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| 217 | architectures with hardware support for a dedicated interrupt stack, it will be |
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| 218 | initialized such that when an interrupt occurs, the processor automatically |
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| 219 | switches to this dedicated stack. On architectures without hardware support |
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| 220 | for a dedicated interrupt stack which is separate from those of the tasks, |
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| 221 | RTEMS will support switching to a dedicated stack for interrupt processing. |
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| 222 | |
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[efd581f] | 223 | Without a dedicated interrupt stack, every task in the system must have enough |
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[f233256] | 224 | stack space to accommodate the worst case stack usage of that particular task |
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[efd581f] | 225 | and the interrupt service routines combined. By supporting a dedicated |
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[f233256] | 226 | interrupt stack, RTEMS significantly lowers the stack requirements for each |
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| 227 | task. |
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| 228 | |
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| 229 | A nested interrupt is processed similarly with the exception that since the CPU |
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| 230 | is already executing on the interrupt stack, there is no need to switch to the |
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| 231 | interrupt stack. |
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| 232 | |
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[efd581f] | 233 | The interrupt stacks (one for each configured processor) are statically |
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| 234 | allocated by the application configuration via ``<rtems/confdefs.h>`` in the |
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| 235 | special section ``.rtemsstack``. This enables an optimal placement of the |
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| 236 | interrupt stacks by the Board Support Package (BSP), e.g. a fast on-chip |
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| 237 | memory. The amount of memory allocated for each interrupt stack is user |
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| 238 | configured and based upon the ``<rtems/confdefs.h>`` parameter |
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[f233256] | 239 | ``CONFIGURE_INTERRUPT_STACK_SIZE``. This parameter is described in detail in |
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[efd581f] | 240 | the Configuring a System chapter of the User's Guide. Since interrupts are |
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| 241 | disabled during the sequential system initialization and the |
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| 242 | ``_Thread_Start_multitasking()`` function does not return to the caller each |
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| 243 | interrupt stack may be used for the initialization stack on the corresponding |
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| 244 | processor. |
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[f233256] | 245 | |
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[efd581f] | 246 | In each of the architecture specific chapters, this section discusses the |
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[f233256] | 247 | interrupt response and control mechanisms of the architecture as they pertain |
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| 248 | to RTEMS. |
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[d755cbd] | 249 | |
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| 250 | Vectoring of an Interrupt Handler |
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| 251 | --------------------------------- |
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| 252 | |
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[f233256] | 253 | In each of the architecture specific chapters, this subsection will describe |
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| 254 | the architecture specific details of the interrupt vectoring process. In |
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| 255 | particular, it should include a description of the Interrupt Stack Frame (ISF). |
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[d755cbd] | 256 | |
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| 257 | Interrupt Levels |
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| 258 | ---------------- |
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| 259 | |
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[f233256] | 260 | In each of the architecture specific chapters, this subsection will describe |
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| 261 | how the interrupt levels available on this particular architecture are mapped |
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| 262 | onto the 255 reserved in the task mode. The interrupt level value of zero (0) |
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| 263 | should always mean that interrupts are enabled. |
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[d755cbd] | 264 | |
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[f233256] | 265 | Any use of an interrupt level that is is not undefined on a particular |
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[d755cbd] | 266 | architecture may result in behavior that is unpredictable. |
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| 267 | |
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| 268 | Disabling of Interrupts by RTEMS |
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| 269 | -------------------------------- |
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| 270 | |
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[f233256] | 271 | During the execution of directive calls, critical sections of code may be |
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| 272 | executed. When these sections are encountered, RTEMS disables all external |
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| 273 | interrupts before the execution of this section and restores them to the |
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| 274 | previous level upon completion of the section. RTEMS has been optimized to |
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| 275 | ensure that interrupts are disabled for the shortest number of instructions |
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| 276 | possible. Since the precise number of instructions and their execution time |
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| 277 | varies based upon target CPU family, CPU model, board memory speed, compiler |
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| 278 | version, and optimization level, it is not practical to provide the precise |
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| 279 | number for all possible RTEMS configurations. |
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| 280 | |
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| 281 | Historically, the measurements were made by hand analyzing and counting the |
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| 282 | execution time of instruction sequences during interrupt disable critical |
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| 283 | sections. For reference purposes, on a 16 Mhz Motorola MC68020, the maximum |
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| 284 | interrupt disable period was typically approximately ten (10) to thirteen (13) |
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| 285 | microseconds. This architecture was memory bound and had a slow bit scan |
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| 286 | instruction. In contrast, during the same period a 14 Mhz SPARC would have a |
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| 287 | worst case disable time of approximately two (2) to three (3) microseconds |
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| 288 | because it had a single cycle bit scan instruction and used fewer cycles for |
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| 289 | memory accesses. |
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| 290 | |
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| 291 | If you are interested in knowing the worst case execution time for a particular |
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| 292 | version of RTEMS, please contact OAR Corporation and we will be happy to |
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| 293 | product the results as a consulting service. |
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| 294 | |
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| 295 | Non-maskable interrupts (NMI) cannot be disabled, and ISRs which execute at |
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| 296 | this level MUST NEVER issue RTEMS system calls. If a directive is invoked, |
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| 297 | unpredictable results may occur due to the inability of RTEMS to protect its |
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| 298 | critical sections. However, ISRs that make no system calls may safely execute |
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| 299 | as non-maskable interrupts. |
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[d755cbd] | 300 | |
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| 301 | Default Fatal Error Processing |
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| 302 | ============================== |
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| 303 | |
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| 304 | Upon detection of a fatal error by either the application or RTEMS during |
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[f233256] | 305 | initialization the ``rtems_fatal_error_occurred`` directive supplied by the |
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| 306 | Fatal Error Manager is invoked. The Fatal Error Manager will invoke the |
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| 307 | user-supplied fatal error handlers. If no user-supplied handlers are |
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| 308 | configured or all of them return without taking action to shutdown the |
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| 309 | processor or reset, a default fatal error handler is invoked. |
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[d755cbd] | 310 | |
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| 311 | Most of the action performed as part of processing the fatal error are |
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[f233256] | 312 | described in detail in the Fatal Error Manager chapter in the User's Guide. |
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| 313 | However, the if no user provided extension or BSP specific fatal error handler |
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| 314 | takes action, the final default action is to invoke a CPU architecture specific |
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| 315 | function. Typically this function disables interrupts and halts the processor. |
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[d755cbd] | 316 | |
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| 317 | In each of the architecture specific chapters, this describes the precise |
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| 318 | operations of the default CPU specific fatal error handler. |
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| 319 | |
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| 320 | Symmetric Multiprocessing |
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| 321 | ========================= |
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| 322 | |
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| 323 | This section contains information about the Symmetric Multiprocessing (SMP) |
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| 324 | status of a particular architecture. |
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| 325 | |
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| 326 | Thread-Local Storage |
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| 327 | ==================== |
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| 328 | |
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| 329 | In order to support thread-local storage (TLS) the CPU port must implement the |
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| 330 | facilities mandated by the application binary interface (ABI) of the CPU |
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[f233256] | 331 | architecture. The CPU port must initialize the TLS area in the |
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| 332 | ``_CPU_Context_Initialize()`` function. There are support functions available |
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[d755cbd] | 333 | via ``#include <rtems/score/tls.h>`` which implement Variants I and II |
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[97e1553] | 334 | according to :cite:`Drepper:2013:TLS`. |
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[d755cbd] | 335 | |
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| 336 | ``_TLS_TCB_at_area_begin_initialize()`` |
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[f233256] | 337 | Uses Variant I, TLS offsets emitted by linker takes the TCB into account. |
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| 338 | For a reference implementation see :file:`cpukit/score/cpu/arm/cpu.c`. |
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[d755cbd] | 339 | |
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| 340 | ``_TLS_TCB_before_TLS_block_initialize()`` |
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| 341 | Uses Variant I, TLS offsets emitted by linker neglects the TCB. For a |
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[f233256] | 342 | reference implementation see |
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| 343 | :file:`c/src/lib/libcpu/powerpc/new-exceptions/cpu.c`. |
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[d755cbd] | 344 | |
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| 345 | ``_TLS_TCB_after_TLS_block_initialize()`` |
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[f233256] | 346 | Uses Variant II. For a reference implementation see |
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| 347 | :file:`cpukit/score/cpu/sparc/cpu.c`. |
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[d755cbd] | 348 | |
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| 349 | The board support package (BSP) must provide the following sections and symbols |
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| 350 | in its linker command file: |
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[f233256] | 351 | |
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| 352 | .. code-block:: c |
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[d755cbd] | 353 | |
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| 354 | .tdata : { |
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[f233256] | 355 | _TLS_Data_begin = .; |
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| 356 | *(.tdata .tdata.* .gnu.linkonce.td.*) |
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| 357 | _TLS_Data_end = .; |
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[d755cbd] | 358 | } |
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| 359 | .tbss : { |
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[f233256] | 360 | _TLS_BSS_begin = .; |
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| 361 | *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) |
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| 362 | _TLS_BSS_end = .; |
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[d755cbd] | 363 | } |
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| 364 | _TLS_Data_size = _TLS_Data_end - _TLS_Data_begin; |
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| 365 | _TLS_Data_begin = _TLS_Data_size != 0 ? _TLS_Data_begin : _TLS_BSS_begin; |
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| 366 | _TLS_Data_end = _TLS_Data_size != 0 ? _TLS_Data_end : _TLS_BSS_begin; |
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| 367 | _TLS_BSS_size = _TLS_BSS_end - _TLS_BSS_begin; |
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| 368 | _TLS_Size = _TLS_BSS_end - _TLS_Data_begin; |
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| 369 | _TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss)); |
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| 370 | |
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| 371 | CPU counter |
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| 372 | =========== |
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| 373 | |
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| 374 | The CPU support must implement the CPU counter interface. A CPU counter is |
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| 375 | some free-running counter. It ticks usually with a frequency close to the CPU |
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| 376 | or system bus clock. On some architectures the actual implementation is board |
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| 377 | support package dependent. The CPU counter is used for profiling of low-level |
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[f233256] | 378 | functions. It is also used to implement two busy wait functions |
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| 379 | ``rtems_counter_delay_ticks()`` and ``rtems_counter_delay_nanoseconds()`` which |
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| 380 | may be used in device drivers. It may be also used as an entropy source for |
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| 381 | random number generators. |
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[d755cbd] | 382 | |
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[f233256] | 383 | The CPU counter interface uses a CPU port specific unsigned integer type |
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| 384 | ``CPU_Counter_ticks`` to represent CPU counter values. The CPU port must |
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[d755cbd] | 385 | provide the following two functions |
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| 386 | |
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| 387 | - ``_CPU_Counter_read()`` to read the current CPU counter value, and |
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| 388 | |
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| 389 | - ``_CPU_Counter_difference()`` to get the difference between two CPU |
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| 390 | counter values. |
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| 391 | |
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| 392 | Interrupt Profiling |
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| 393 | =================== |
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| 394 | |
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| 395 | The RTEMS profiling needs support by the CPU port for the interrupt entry and |
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| 396 | exit times. In case profiling is enabled via the RTEMS build configuration |
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[f233256] | 397 | option ``--enable-profiling`` (in this case the pre-processor symbol |
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| 398 | ``RTEMS_PROFILING`` is defined) the CPU port may provide data for the interrupt |
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| 399 | entry and exit times of the outer-most interrupt. The CPU port can feed |
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| 400 | interrupt entry and exit times with the |
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| 401 | ``_Profiling_Outer_most_interrupt_entry_and_exit()`` function (``#include |
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| 402 | <rtems/score/profiling.h>``). For an example please have a look at |
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| 403 | :file:`cpukit/score/cpu/arm/arm_exc_interrupt.S`. |
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[d755cbd] | 404 | |
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| 405 | Board Support Packages |
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| 406 | ====================== |
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| 407 | |
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[f233256] | 408 | An RTEMS Board Support Package (BSP) must be designed to support a particular |
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| 409 | processor model and target board combination. |
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[d755cbd] | 410 | |
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[f233256] | 411 | In each of the architecture specific chapters, this section will present a |
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| 412 | discussion of architecture specific BSP issues. For more information on |
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[c6f8e51] | 413 | developing a BSP, refer to *RTEMS BSP and Driver Guide* chapter titled |
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| 414 | ``Board Support Packages`` in the *RTEMS Classic API Guide*. |
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[d755cbd] | 415 | |
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| 416 | System Reset |
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| 417 | ------------ |
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| 418 | |
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[f233256] | 419 | An RTEMS based application is initiated or re-initiated when the processor is |
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| 420 | reset or transfer is passed to it from a boot monitor or ROM monitor. |
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[d755cbd] | 421 | |
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[f233256] | 422 | In each of the architecture specific chapters, this subsection describes the |
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[c6f8e51] | 423 | actions that the BSP must take assuming the application gets control |
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| 424 | when the microprocessor is reset. |
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