source: rtems-docs/cpu-supplement/openrisc_1000.rst @ ec95748

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1.. SPDX-License-Identifier: CC-BY-SA-4.0
2
3.. Copyright (C) 2014 Hesham Almatary
4.. Copyright (C) 1989, 2007 On-Line Applications Research Corporation (OAR)
5
6OpenRISC 1000 Specific Information
7**********************************
8
9This chapter discusses the`OpenRISC 1000 architecture
10http://opencores.org/or1k/Main_Page dependencies in this port of RTEMS. There
11are many implementations for OpenRISC like or1200 and mor1kx. Currently RTEMS
12supports basic features that all implementations should have.
13
14**Architecture Documents**
15
16For information on the OpenRISC 1000 architecture refer to the`OpenRISC 1000
17architecture manual http://openrisc.github.io/or1k.html.
18
19Calling Conventions
20===================
21
22Please refer to the`Function Calling Sequence
23http://openrisc.github.io/or1k.html#__RefHeading__504887_595890882.
24
25Floating Point Unit
26-------------------
27
28A floating point unit is currently not supported.
29
30Memory Model
31============
32
33A flat 32-bit memory model is supported.
34
35Interrupt Processing
36====================
37
38OpenRISC 1000 architecture has 13 exception types:
39
40- Reset
41
42- Bus Error
43
44- Data Page Fault
45
46- Instruction Page Fault
47
48- Tick Timer
49
50- Alignment
51
52- Illegal Instruction
53
54- External Interrupt
55
56- D-TLB Miss
57
58- I-TLB Miss
59
60- Range
61
62- System Call
63
64- Floating Point
65
66- Trap
67
68Interrupt Levels
69----------------
70
71There are only two levels: interrupts enabled and interrupts disabled.
72
73Interrupt Stack
74---------------
75
76The OpenRISC RTEMS port uses a dedicated software interrupt stack.  The stack
77for interrupts is allocated during interrupt driver initialization.  When an
78interrupt is entered, the _ISR_Handler routine is responsible for switching
79from the interrupted task stack to RTEMS software interrupt stack.
80
81Default Fatal Error Processing
82==============================
83
84The default fatal error handler for this architecture performs the following
85actions:
86
87- disables operating system supported interrupts (IRQ),
88
89- places the error code in ``r0``, and
90
91- executes an infinite loop to simulate a halt processor instruction.
92
93Symmetric Multiprocessing
94=========================
95
96SMP is not supported.
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