source: rtems-docs/cpu-supplement/openrisc_1000.rst @ e52906b

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Last change on this file since e52906b was e52906b, checked in by Sebastian Huber <sebastian.huber@…>, on 01/09/19 at 15:14:06

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1.. SPDX-License-Identifier: CC-BY-SA-4.0
2
3.. Copyright (C) 1989, 2007 On-Line Applications Research Corporation (OAR)
4
5OpenRISC 1000 Specific Information
6**********************************
7
8This chapter discusses the`OpenRISC 1000 architecture
9http://opencores.org/or1k/Main_Page dependencies in this port of RTEMS. There
10are many implementations for OpenRISC like or1200 and mor1kx. Currently RTEMS
11supports basic features that all implementations should have.
12
13**Architecture Documents**
14
15For information on the OpenRISC 1000 architecture refer to the`OpenRISC 1000
16architecture manual http://openrisc.github.io/or1k.html.
17
18Calling Conventions
19===================
20
21Please refer to the`Function Calling Sequence
22http://openrisc.github.io/or1k.html#__RefHeading__504887_595890882.
23
24Floating Point Unit
25-------------------
26
27A floating point unit is currently not supported.
28
29Memory Model
30============
31
32A flat 32-bit memory model is supported.
33
34Interrupt Processing
35====================
36
37OpenRISC 1000 architecture has 13 exception types:
38
39- Reset
40
41- Bus Error
42
43- Data Page Fault
44
45- Instruction Page Fault
46
47- Tick Timer
48
49- Alignment
50
51- Illegal Instruction
52
53- External Interrupt
54
55- D-TLB Miss
56
57- I-TLB Miss
58
59- Range
60
61- System Call
62
63- Floating Point
64
65- Trap
66
67Interrupt Levels
68----------------
69
70There are only two levels: interrupts enabled and interrupts disabled.
71
72Interrupt Stack
73---------------
74
75The OpenRISC RTEMS port uses a dedicated software interrupt stack.  The stack
76for interrupts is allocated during interrupt driver initialization.  When an
77interrupt is entered, the _ISR_Handler routine is responsible for switching
78from the interrupted task stack to RTEMS software interrupt stack.
79
80Default Fatal Error Processing
81==============================
82
83The default fatal error handler for this architecture performs the following
84actions:
85
86- disables operating system supported interrupts (IRQ),
87
88- places the error code in ``r0``, and
89
90- executes an infinite loop to simulate a halt processor instruction.
91
92Symmetric Multiprocessing
93=========================
94
95SMP is not supported.
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