source: rtems-docs/cpu-supplement/openrisc_1000.rst @ f067ba3

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Last change on this file since f067ba3 was 6916004, checked in by Chris Johns <chrisj@…>, on Nov 9, 2016 at 1:39:16 AM

cpu-supplement: Fix header levels.

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[489740f]1.. comment SPDX-License-Identifier: CC-BY-SA-4.0
2
[f233256]3.. COMMENT: COPYRIGHT (c) 1989-2007.
4.. COMMENT: On-Line Applications Research Corporation (OAR).
5.. COMMENT: All rights reserved.
6
[d755cbd]7OpenRISC 1000 Specific Information
[6916004]8**********************************
[d755cbd]9
[f233256]10This chapter discusses the`OpenRISC 1000 architecture
11http://opencores.org/or1k/Main_Page dependencies in this port of RTEMS. There
12are many implementations for OpenRISC like or1200 and mor1kx. Currently RTEMS
13supports basic features that all implementations should have.
[d755cbd]14
15**Architecture Documents**
16
[f233256]17For information on the OpenRISC 1000 architecture refer to the`OpenRISC 1000
18architecture manual http://openrisc.github.io/or1k.html.
[d755cbd]19
20Calling Conventions
21===================
22
[f233256]23Please refer to the`Function Calling Sequence
24http://openrisc.github.io/or1k.html#__RefHeading__504887_595890882.
[d755cbd]25
26Floating Point Unit
27-------------------
28
29A floating point unit is currently not supported.
30
31Memory Model
32============
33
34A flat 32-bit memory model is supported.
35
36Interrupt Processing
37====================
38
39OpenRISC 1000 architecture has 13 exception types:
40
41- Reset
42
43- Bus Error
44
45- Data Page Fault
46
47- Instruction Page Fault
48
49- Tick Timer
50
51- Alignment
52
53- Illegal Instruction
54
55- External Interrupt
56
57- D-TLB Miss
58
59- I-TLB Miss
60
61- Range
62
63- System Call
64
65- Floating Point
66
67- Trap
68
69Interrupt Levels
70----------------
71
72There are only two levels: interrupts enabled and interrupts disabled.
73
74Interrupt Stack
75---------------
76
[f233256]77The OpenRISC RTEMS port uses a dedicated software interrupt stack.  The stack
78for interrupts is allocated during interrupt driver initialization.  When an
79interrupt is entered, the _ISR_Handler routine is responsible for switching
80from the interrupted task stack to RTEMS software interrupt stack.
[d755cbd]81
82Default Fatal Error Processing
83==============================
84
[f233256]85The default fatal error handler for this architecture performs the following
86actions:
[d755cbd]87
88- disables operating system supported interrupts (IRQ),
89
90- places the error code in ``r0``, and
91
92- executes an infinite loop to simulate a halt processor instruction.
93
94Symmetric Multiprocessing
95=========================
96
97SMP is not supported.
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