[489740f] | 1 | .. comment SPDX-License-Identifier: CC-BY-SA-4.0 |
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| 2 | |
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[f233256] | 3 | .. COMMENT: COPYRIGHT (c) 1989-2007. |
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| 4 | .. COMMENT: On-Line Applications Research Corporation (OAR). |
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| 5 | .. COMMENT: All rights reserved. |
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| 6 | |
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[d755cbd] | 7 | OpenRISC 1000 Specific Information |
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[6916004] | 8 | ********************************** |
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[d755cbd] | 9 | |
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[f233256] | 10 | This chapter discusses the`OpenRISC 1000 architecture |
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| 11 | http://opencores.org/or1k/Main_Page dependencies in this port of RTEMS. There |
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| 12 | are many implementations for OpenRISC like or1200 and mor1kx. Currently RTEMS |
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| 13 | supports basic features that all implementations should have. |
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[d755cbd] | 14 | |
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| 15 | **Architecture Documents** |
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| 16 | |
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[f233256] | 17 | For information on the OpenRISC 1000 architecture refer to the`OpenRISC 1000 |
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| 18 | architecture manual http://openrisc.github.io/or1k.html. |
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[d755cbd] | 19 | |
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| 20 | Calling Conventions |
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| 21 | =================== |
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| 22 | |
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[f233256] | 23 | Please refer to the`Function Calling Sequence |
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| 24 | http://openrisc.github.io/or1k.html#__RefHeading__504887_595890882. |
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[d755cbd] | 25 | |
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| 26 | Floating Point Unit |
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| 27 | ------------------- |
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| 28 | |
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| 29 | A floating point unit is currently not supported. |
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| 30 | |
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| 31 | Memory Model |
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| 32 | ============ |
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| 33 | |
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| 34 | A flat 32-bit memory model is supported. |
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| 35 | |
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| 36 | Interrupt Processing |
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| 37 | ==================== |
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| 38 | |
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| 39 | OpenRISC 1000 architecture has 13 exception types: |
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| 40 | |
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| 41 | - Reset |
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| 42 | |
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| 43 | - Bus Error |
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| 44 | |
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| 45 | - Data Page Fault |
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| 46 | |
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| 47 | - Instruction Page Fault |
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| 48 | |
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| 49 | - Tick Timer |
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| 50 | |
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| 51 | - Alignment |
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| 52 | |
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| 53 | - Illegal Instruction |
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| 54 | |
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| 55 | - External Interrupt |
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| 56 | |
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| 57 | - D-TLB Miss |
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| 58 | |
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| 59 | - I-TLB Miss |
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| 60 | |
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| 61 | - Range |
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| 62 | |
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| 63 | - System Call |
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| 64 | |
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| 65 | - Floating Point |
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| 66 | |
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| 67 | - Trap |
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| 68 | |
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| 69 | Interrupt Levels |
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| 70 | ---------------- |
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| 71 | |
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| 72 | There are only two levels: interrupts enabled and interrupts disabled. |
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| 73 | |
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| 74 | Interrupt Stack |
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| 75 | --------------- |
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| 76 | |
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[f233256] | 77 | The OpenRISC RTEMS port uses a dedicated software interrupt stack. The stack |
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| 78 | for interrupts is allocated during interrupt driver initialization. When an |
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| 79 | interrupt is entered, the _ISR_Handler routine is responsible for switching |
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| 80 | from the interrupted task stack to RTEMS software interrupt stack. |
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[d755cbd] | 81 | |
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| 82 | Default Fatal Error Processing |
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| 83 | ============================== |
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| 84 | |
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[f233256] | 85 | The default fatal error handler for this architecture performs the following |
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| 86 | actions: |
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[d755cbd] | 87 | |
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| 88 | - disables operating system supported interrupts (IRQ), |
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| 89 | |
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| 90 | - places the error code in ``r0``, and |
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| 91 | |
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| 92 | - executes an infinite loop to simulate a halt processor instruction. |
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| 93 | |
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| 94 | Symmetric Multiprocessing |
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| 95 | ========================= |
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| 96 | |
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| 97 | SMP is not supported. |
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