source: rtems-docs/cpu-supplement/mips.rst @ e52906b

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4MIPS Specific Information
5*************************
6
7This chapter discusses the MIPS architecture dependencies in this port of
8RTEMS.  The MIPS family has a wide variety of implementations by a wide range
9of vendors.  Consequently, there are many, many CPU models within it.
10
11**Architecture Documents**
12
13IDT docs are online at http://www.idt.com/products/risc/Welcome.html
14
15CPU Model Dependent Features
16============================
17
18This section presents the set of features which vary across MIPS
19implementations and are of importance to RTEMS.  The set of CPU model feature
20macros are defined in the file ``cpukit/score/cpu/mips/mips.h`` based upon the
21particular CPU model specified on the compilation command line.
22
23Another Optional Feature
24------------------------
25
26The macro XXX
27
28Calling Conventions
29===================
30
31Processor Background
32--------------------
33
34TBD
35
36Calling Mechanism
37-----------------
38
39TBD
40
41Register Usage
42--------------
43
44TBD
45
46Parameter Passing
47-----------------
48
49TBD
50
51Memory Model
52============
53
54Flat Memory Model
55-----------------
56
57The MIPS family supports a flat 32-bit address space with addresses ranging
58from 0x00000000 to 0xFFFFFFFF (4 gigabytes).  Each address is represented by a
5932-bit value and is byte addressable.  The address may be used to reference a
60single byte, word (2-bytes), or long word (4 bytes).  Memory accesses within
61this address space are performed in big endian fashion by the processors in
62this family.
63
64Some of the MIPS family members such as the support virtual memory and
65segmentation.  RTEMS does not support virtual memory or segmentation on any of
66these family members.
67
68Interrupt Processing
69====================
70
71Although RTEMS hides many of the processor dependent details of interrupt
72processing, it is important to understand how the RTEMS interrupt manager is
73mapped onto the processor's unique architecture. Discussed in this chapter are
74the MIPS's interrupt response and control mechanisms as they pertain to RTEMS.
75
76Vectoring of an Interrupt Handler
77---------------------------------
78
79Upon receipt of an interrupt the XXX family members with separate interrupt
80stacks automatically perform the following actions:
81
82- TBD
83
84A nested interrupt is processed similarly by these CPU models with the
85exception that only a single ISF is placed on the interrupt stack and the
86current stack need not be switched.
87
88Interrupt Levels
89----------------
90
91TBD
92
93Default Fatal Error Processing
94==============================
95
96The default fatal error handler for this target architecture disables processor
97interrupts, places the error code in *XXX*, and executes a``XXX`` instruction
98to simulate a halt processor instruction.
99
100Symmetric Multiprocessing
101=========================
102
103SMP is not supported.
104
105Thread-Local Storage
106====================
107
108Thread-local storage is not implemented.
109
110Board Support Packages
111======================
112
113System Reset
114------------
115
116An RTEMS based application is initiated or re-initiated when the processor is
117reset.  When the processor is reset, it performs the following actions:
118
119- TBD
120
121Processor Initialization
122------------------------
123
124TBD
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