1 | .. comment SPDX-License-Identifier: CC-BY-SA-4.0 |
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2 | |
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3 | .. COMMENT: Copyright (c) 2014 embedded brains GmbH. All rights reserved. |
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4 | |
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5 | MIPS Specific Information |
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6 | ************************* |
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7 | |
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8 | This chapter discusses the MIPS architecture dependencies in this port of |
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9 | RTEMS. The MIPS family has a wide variety of implementations by a wide range |
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10 | of vendors. Consequently, there are many, many CPU models within it. |
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11 | |
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12 | **Architecture Documents** |
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13 | |
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14 | IDT docs are online at http://www.idt.com/products/risc/Welcome.html |
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15 | |
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16 | CPU Model Dependent Features |
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17 | ============================ |
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18 | |
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19 | This section presents the set of features which vary across MIPS |
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20 | implementations and are of importance to RTEMS. The set of CPU model feature |
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21 | macros are defined in the file ``cpukit/score/cpu/mips/mips.h`` based upon the |
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22 | particular CPU model specified on the compilation command line. |
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23 | |
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24 | Another Optional Feature |
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25 | ------------------------ |
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26 | |
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27 | The macro XXX |
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28 | |
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29 | Calling Conventions |
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30 | =================== |
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31 | |
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32 | Processor Background |
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33 | -------------------- |
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34 | |
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35 | TBD |
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36 | |
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37 | Calling Mechanism |
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38 | ----------------- |
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39 | |
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40 | TBD |
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41 | |
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42 | Register Usage |
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43 | -------------- |
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44 | |
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45 | TBD |
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46 | |
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47 | Parameter Passing |
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48 | ----------------- |
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49 | |
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50 | TBD |
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51 | |
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52 | Memory Model |
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53 | ============ |
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54 | |
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55 | Flat Memory Model |
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56 | ----------------- |
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57 | |
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58 | The MIPS family supports a flat 32-bit address space with addresses ranging |
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59 | from 0x00000000 to 0xFFFFFFFF (4 gigabytes). Each address is represented by a |
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60 | 32-bit value and is byte addressable. The address may be used to reference a |
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61 | single byte, word (2-bytes), or long word (4 bytes). Memory accesses within |
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62 | this address space are performed in big endian fashion by the processors in |
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63 | this family. |
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64 | |
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65 | Some of the MIPS family members such as the support virtual memory and |
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66 | segmentation. RTEMS does not support virtual memory or segmentation on any of |
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67 | these family members. |
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68 | |
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69 | Interrupt Processing |
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70 | ==================== |
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71 | |
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72 | Although RTEMS hides many of the processor dependent details of interrupt |
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73 | processing, it is important to understand how the RTEMS interrupt manager is |
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74 | mapped onto the processor's unique architecture. Discussed in this chapter are |
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75 | the MIPS's interrupt response and control mechanisms as they pertain to RTEMS. |
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76 | |
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77 | Vectoring of an Interrupt Handler |
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78 | --------------------------------- |
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79 | |
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80 | Upon receipt of an interrupt the XXX family members with separate interrupt |
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81 | stacks automatically perform the following actions: |
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82 | |
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83 | - TBD |
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84 | |
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85 | A nested interrupt is processed similarly by these CPU models with the |
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86 | exception that only a single ISF is placed on the interrupt stack and the |
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87 | current stack need not be switched. |
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88 | |
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89 | Interrupt Levels |
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90 | ---------------- |
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91 | |
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92 | TBD |
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93 | |
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94 | Default Fatal Error Processing |
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95 | ============================== |
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96 | |
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97 | The default fatal error handler for this target architecture disables processor |
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98 | interrupts, places the error code in *XXX*, and executes a``XXX`` instruction |
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99 | to simulate a halt processor instruction. |
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100 | |
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101 | Symmetric Multiprocessing |
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102 | ========================= |
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103 | |
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104 | SMP is not supported. |
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105 | |
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106 | Thread-Local Storage |
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107 | ==================== |
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108 | |
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109 | Thread-local storage is not implemented. |
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110 | |
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111 | Board Support Packages |
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112 | ====================== |
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113 | |
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114 | System Reset |
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115 | ------------ |
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116 | |
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117 | An RTEMS based application is initiated or re-initiated when the processor is |
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118 | reset. When the processor is reset, it performs the following actions: |
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119 | |
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120 | - TBD |
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121 | |
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122 | Processor Initialization |
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123 | ------------------------ |
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124 | |
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125 | TBD |
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