source: rtems-docs/cpu-supplement/mips.rst @ 67195aa

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[489740f]1.. comment SPDX-License-Identifier: CC-BY-SA-4.0
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[f233256]3.. COMMENT: Copyright (c) 2014 embedded brains GmbH.  All rights reserved.
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[d755cbd]5MIPS Specific Information
[6916004]6*************************
[d755cbd]7
[f233256]8This chapter discusses the MIPS architecture dependencies in this port of
9RTEMS.  The MIPS family has a wide variety of implementations by a wide range
10of vendors.  Consequently, there are many, many CPU models within it.
[d755cbd]11
12**Architecture Documents**
13
14IDT docs are online at http://www.idt.com/products/risc/Welcome.html
15
16CPU Model Dependent Features
17============================
18
[f233256]19This section presents the set of features which vary across MIPS
20implementations and are of importance to RTEMS.  The set of CPU model feature
21macros are defined in the file ``cpukit/score/cpu/mips/mips.h`` based upon the
22particular CPU model specified on the compilation command line.
[d755cbd]23
24Another Optional Feature
25------------------------
26
27The macro XXX
28
29Calling Conventions
30===================
31
32Processor Background
33--------------------
34
35TBD
36
37Calling Mechanism
38-----------------
39
40TBD
41
42Register Usage
43--------------
44
45TBD
46
47Parameter Passing
48-----------------
49
50TBD
51
52Memory Model
53============
54
55Flat Memory Model
56-----------------
57
[f233256]58The MIPS family supports a flat 32-bit address space with addresses ranging
59from 0x00000000 to 0xFFFFFFFF (4 gigabytes).  Each address is represented by a
6032-bit value and is byte addressable.  The address may be used to reference a
61single byte, word (2-bytes), or long word (4 bytes).  Memory accesses within
62this address space are performed in big endian fashion by the processors in
63this family.
[d755cbd]64
65Some of the MIPS family members such as the support virtual memory and
[f233256]66segmentation.  RTEMS does not support virtual memory or segmentation on any of
67these family members.
[d755cbd]68
69Interrupt Processing
70====================
71
[f233256]72Although RTEMS hides many of the processor dependent details of interrupt
73processing, it is important to understand how the RTEMS interrupt manager is
74mapped onto the processor's unique architecture. Discussed in this chapter are
75the MIPS's interrupt response and control mechanisms as they pertain to RTEMS.
[d755cbd]76
77Vectoring of an Interrupt Handler
78---------------------------------
79
[f233256]80Upon receipt of an interrupt the XXX family members with separate interrupt
81stacks automatically perform the following actions:
[d755cbd]82
83- TBD
84
[f233256]85A nested interrupt is processed similarly by these CPU models with the
86exception that only a single ISF is placed on the interrupt stack and the
87current stack need not be switched.
[d755cbd]88
89Interrupt Levels
90----------------
91
92TBD
93
94Default Fatal Error Processing
95==============================
96
[f233256]97The default fatal error handler for this target architecture disables processor
98interrupts, places the error code in *XXX*, and executes a``XXX`` instruction
99to simulate a halt processor instruction.
[d755cbd]100
101Symmetric Multiprocessing
102=========================
103
104SMP is not supported.
105
106Thread-Local Storage
107====================
108
109Thread-local storage is not implemented.
110
111Board Support Packages
112======================
113
114System Reset
115------------
116
[f233256]117An RTEMS based application is initiated or re-initiated when the processor is
118reset.  When the processor is reset, it performs the following actions:
[d755cbd]119
120- TBD
121
122Processor Initialization
123------------------------
124
125TBD
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