[489740f] | 1 | .. comment SPDX-License-Identifier: CC-BY-SA-4.0 |
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[f233256] | 3 | .. COMMENT: Copyright (c) 2014 embedded brains GmbH. All rights reserved. |
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| 4 | |
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[d755cbd] | 5 | M68xxx and Coldfire Specific Information |
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[6916004] | 6 | **************************************** |
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[d755cbd] | 7 | |
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[f233256] | 8 | This chapter discusses the Freescale (formerly Motorola) MC68xxx and Coldfire |
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| 9 | architectural dependencies. The MC68xxx family has a wide variety of CPU |
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| 10 | models within it based upon different CPU core implementations. Ignoring the |
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| 11 | Coldfire parts, the part numbers for these models are generally divided into |
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| 12 | MC680xx and MC683xx. The MC680xx models are more general purpose processors |
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| 13 | with no integrated peripherals. The MC683xx models, on the other hand, are |
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| 14 | more specialized and have a variety of peripherals on chip including |
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| 15 | sophisticated timers and serial communications controllers. |
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[d755cbd] | 16 | |
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| 17 | **Architecture Documents** |
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| 18 | |
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[f233256] | 19 | For information on the MC68xxx and Coldfire architecture, refer to the |
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| 20 | following documents available from Freescale website |
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| 21 | (http//www.freescale.com/): |
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[d755cbd] | 22 | |
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| 23 | - *M68000 Family Reference, Motorola, FR68K/D*. |
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| 24 | |
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[d389819] | 25 | - *MC68020 User's Manual, Motorola, MC68020UM/AD*. |
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[d755cbd] | 26 | |
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[d389819] | 27 | - *MC68881/MC68882 Floating-Point Coprocessor User's Manual, |
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[d755cbd] | 28 | Motorola, MC68881UM/AD*. |
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| 29 | |
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| 30 | CPU Model Dependent Features |
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| 31 | ============================ |
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| 32 | |
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[f233256] | 33 | This section presents the set of features which vary across m68k/Coldfire |
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| 34 | implementations that are of importance to RTEMS. The set of CPU model feature |
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| 35 | macros are defined in the file :file:`cpukit/score/cpu/m68k/m68k.h` based upon |
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| 36 | the particular CPU model selected on the compilation command line. |
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[d755cbd] | 37 | |
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| 38 | BFFFO Instruction |
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| 39 | ----------------- |
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| 40 | |
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[f233256] | 41 | The macro ``M68K_HAS_BFFFO`` is set to 1 to indicate that this CPU model has |
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| 42 | the bfffo instruction. |
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[d755cbd] | 43 | |
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| 44 | Vector Base Register |
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| 45 | -------------------- |
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| 46 | |
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[f233256] | 47 | The macro ``M68K_HAS_VBR`` is set to 1 to indicate that this CPU model has a |
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| 48 | vector base register (vbr). |
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[d755cbd] | 49 | |
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| 50 | Separate Stacks |
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| 51 | --------------- |
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| 52 | |
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[f233256] | 53 | The macro ``M68K_HAS_SEPARATE_STACKS`` is set to 1 to indicate that this CPU |
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| 54 | model has separate interrupt, user, and supervisor mode stacks. |
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[d755cbd] | 55 | |
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| 56 | Pre-Indexing Address Mode |
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| 57 | ------------------------- |
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| 58 | |
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[f233256] | 59 | The macro ``M68K_HAS_PREINDEXING`` is set to 1 to indicate that this CPU model |
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| 60 | has the pre-indexing address mode. |
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[d755cbd] | 61 | |
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| 62 | Extend Byte to Long Instruction |
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| 63 | ------------------------------- |
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| 64 | |
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[f233256] | 65 | The macro ``M68K_HAS_EXTB_L`` is set to 1 to indicate that this CPU model has |
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| 66 | the extb.l instruction. This instruction is supposed to be available in all |
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| 67 | models based on the cpu32 core as well as mc68020 and up models. |
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[d755cbd] | 68 | |
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| 69 | Calling Conventions |
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| 70 | =================== |
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| 71 | |
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[f233256] | 72 | The MC68xxx architecture supports a simple yet effective call and return |
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| 73 | mechanism. A subroutine is invoked via the branch to subroutine (``bsr``) or |
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| 74 | the jump to subroutine (``jsr``) instructions. These instructions push the |
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| 75 | return address on the current stack. The return from subroutine (``rts``) |
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| 76 | instruction pops the return address off the current stack and transfers control |
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| 77 | to that instruction. It is is important to note that the MC68xxx call and |
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| 78 | return mechanism does not automatically save or restore any registers. It is |
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| 79 | the responsibility of the high-level language compiler to define the register |
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| 80 | preservation and usage convention. |
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[d755cbd] | 81 | |
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| 82 | Calling Mechanism |
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| 83 | ----------------- |
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| 84 | |
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[f233256] | 85 | All RTEMS directives are invoked using either a ``bsr`` or ``jsr`` instruction |
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| 86 | and return to the user application via the rts instruction. |
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[d755cbd] | 87 | |
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| 88 | Register Usage |
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| 89 | -------------- |
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| 90 | |
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[f233256] | 91 | As discussed above, the ``bsr`` and ``jsr`` instructions do not automatically |
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| 92 | save any registers. RTEMS uses the registers D0, D1, A0, and A1 as scratch |
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| 93 | registers. These registers are not preserved by RTEMS directives therefore, |
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| 94 | the contents of these registers should not be assumed upon return from any |
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| 95 | RTEMS directive. |
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[d755cbd] | 96 | |
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| 97 | Parameter Passing |
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| 98 | ----------------- |
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| 99 | |
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[f233256] | 100 | RTEMS assumes that arguments are placed on the current stack before the |
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| 101 | directive is invoked via the bsr or jsr instruction. The first argument is |
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| 102 | assumed to be closest to the return address on the stack. This means that the |
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| 103 | first argument of the C calling sequence is pushed last. The following |
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| 104 | pseudo-code illustrates the typical sequence used to call a RTEMS directive |
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| 105 | with three (3) arguments: |
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| 106 | |
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| 107 | .. code-block:: c |
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[d755cbd] | 108 | |
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| 109 | push third argument |
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| 110 | push second argument |
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| 111 | push first argument |
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| 112 | invoke directive |
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| 113 | remove arguments from the stack |
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| 114 | |
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| 115 | The arguments to RTEMS are typically pushed onto the stack using a move |
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[f233256] | 116 | instruction with a pre-decremented stack pointer as the destination. These |
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| 117 | arguments must be removed from the stack after control is returned to the |
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| 118 | caller. This removal is typically accomplished by adding the size of the |
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| 119 | argument list in bytes to the current stack pointer. |
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[d755cbd] | 120 | |
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| 121 | Memory Model |
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| 122 | ============ |
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| 123 | |
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[f233256] | 124 | The MC68xxx family supports a flat 32-bit address space with addresses ranging |
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| 125 | from 0x00000000 to 0xFFFFFFFF (4 gigabytes). Each address is represented by a |
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| 126 | 32-bit value and is byte addressable. The address may be used to reference a |
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| 127 | single byte, word (2-bytes), or long word (4 bytes). Memory accesses within |
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| 128 | this address space are performed in big endian fashion by the processors in |
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| 129 | this family. |
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| 130 | |
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| 131 | Some of the MC68xxx family members such as the MC68020, MC68030, and MC68040 |
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| 132 | support virtual memory and segmentation. The MC68020 requires external |
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| 133 | hardware support such as the MC68851 Paged Memory Management Unit coprocessor |
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| 134 | which is typically used to perform address translations for these systems. |
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| 135 | RTEMS does not support virtual memory or segmentation on any of the MC68xxx |
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| 136 | family members. |
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[d755cbd] | 137 | |
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| 138 | Interrupt Processing |
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| 139 | ==================== |
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| 140 | |
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[f233256] | 141 | Discussed in this section are the MC68xxx's interrupt response and control |
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| 142 | mechanisms as they pertain to RTEMS. |
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[d755cbd] | 143 | |
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| 144 | Vectoring of an Interrupt Handler |
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| 145 | --------------------------------- |
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| 146 | |
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[f233256] | 147 | Depending on whether or not the particular CPU supports a separate interrupt |
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| 148 | stack, the MC68xxx family has two different interrupt handling models. |
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[d755cbd] | 149 | |
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| 150 | Models Without Separate Interrupt Stacks |
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| 151 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 152 | |
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| 153 | Upon receipt of an interrupt the MC68xxx family members without separate |
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[f233256] | 154 | interrupt stacks automatically use software to switch stacks. |
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[d755cbd] | 155 | |
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| 156 | Models With Separate Interrupt Stacks |
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| 157 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 158 | |
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[f233256] | 159 | Upon receipt of an interrupt the MC68xxx family members with separate interrupt |
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| 160 | stacks automatically perform the following actions: |
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[d755cbd] | 161 | |
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| 162 | - saves the current status register (SR), |
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| 163 | |
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[f233256] | 164 | - clears the master/interrupt (M) bit of the SR to indicate the switch from |
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| 165 | master state to interrupt state, |
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[d755cbd] | 166 | |
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| 167 | - sets the privilege mode to supervisor, |
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| 168 | |
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| 169 | - suppresses tracing, |
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| 170 | |
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[f233256] | 171 | - sets the interrupt mask level equal to the level of the interrupt being |
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| 172 | serviced, |
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[d755cbd] | 173 | |
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[f233256] | 174 | - pushes an interrupt stack frame (ISF), which includes the program counter |
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| 175 | (PC), the status register (SR), and the format/exception vector offset (FVO) |
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| 176 | word, onto the supervisor and interrupt stacks, |
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[d755cbd] | 177 | |
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[f233256] | 178 | - switches the current stack to the interrupt stack and vectors to an interrupt |
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| 179 | service routine (ISR). If the ISR was installed with the interrupt_catch |
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| 180 | directive, then the RTEMS interrupt handler will begin execution. The RTEMS |
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| 181 | interrupt handler saves all registers which are not preserved according to |
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[d389819] | 182 | the calling conventions and invokes the application's ISR. |
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[d755cbd] | 183 | |
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[f233256] | 184 | A nested interrupt is processed similarly by these CPU models with the |
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| 185 | exception that only a single ISF is placed on the interrupt stack and the |
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| 186 | current stack need not be switched. |
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[d755cbd] | 187 | |
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[f233256] | 188 | The FVO word in the Interrupt Stack Frame is examined by RTEMS to determine |
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| 189 | when an outer most interrupt is being exited. Since the FVO is used by RTEMS |
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| 190 | for this purpose, the user application code MUST NOT modify this field. |
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[d755cbd] | 191 | |
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[f233256] | 192 | The following shows the Interrupt Stack Frame for MC68xxx CPU models with |
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| 193 | separate interrupt stacks: |
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[d755cbd] | 194 | |
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| 195 | +----------------------+-----+ |
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| 196 | | Status Register | 0x0 | |
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| 197 | +----------------------+-----+ |
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| 198 | | Program Counter High | 0x2 | |
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| 199 | +----------------------+-----+ |
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| 200 | | Program Counter Low | 0x4 | |
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| 201 | +----------------------+-----+ |
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| 202 | | Format/Vector Offset | 0x6 | |
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| 203 | +----------------------+-----+ |
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| 204 | |
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| 205 | |
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| 206 | CPU Models Without VBR and RAM at 0 |
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| 207 | ----------------------------------- |
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| 208 | |
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[f233256] | 209 | This is from a post by Zoltan Kocsi <zoltan@bendor.com.au> and is a nice trick |
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| 210 | in certain situations. In his words: |
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[d755cbd] | 211 | |
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[f233256] | 212 | I think somebody on this list asked about the interupt vector handling w/o VBR |
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| 213 | and RAM at 0. The usual trick is to initialise the vector table (except the |
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| 214 | first 2 two entries, of course) to point to the same location BUT you also add |
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| 215 | the vector number times 0x1000000 to them. That is, bits 31-24 contain the |
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| 216 | vector number and 23-0 the address of the common handler. Since the PC is 32 |
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| 217 | bit wide but the actual address bus is only 24, the top byte will be in the PC |
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| 218 | but will be ignored when jumping onto your routine. |
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[d755cbd] | 219 | |
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[f233256] | 220 | Then your common interrupt routine gets this info by loading the PC into some |
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| 221 | register and based on that info, you can jump to a vector in a vector table |
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| 222 | pointed by a virtual VBR: |
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| 223 | |
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| 224 | .. code-block:: c |
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[d755cbd] | 225 | |
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| 226 | // |
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| 227 | // Real vector table at 0 |
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| 228 | // |
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| 229 | .long initial_sp |
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| 230 | .long initial_pc |
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| 231 | .long myhandler+0x02000000 |
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| 232 | .long myhandler+0x03000000 |
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| 233 | .long myhandler+0x04000000 |
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| 234 | ... |
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| 235 | .long myhandler+0xff000000 |
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| 236 | // |
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| 237 | // This handler will jump to the interrupt routine of which |
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| 238 | // the address is stored at VBR[ vector_no ] |
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| 239 | // The registers and stackframe will be intact, the interrupt |
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| 240 | // routine will see exactly what it would see if it was called |
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| 241 | // directly from the HW vector table at 0. |
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| 242 | // |
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[f233256] | 243 | .comm VBR,4,2 // This defines the 'virtual' VBR |
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| 244 | // From C: extern void *VBR; |
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[d755cbd] | 245 | myhandler: // At entry, PC contains the full vector |
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[f233256] | 246 | move.l %d0,-(%sp) // Save d0 |
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| 247 | move.l %a0,-(%sp) // Save a0 |
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| 248 | lea 0(%pc),%a0 // Get the value of the PC |
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| 249 | move.l %a0,%d0 // Copy it to a data reg, d0 is VV?????? |
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| 250 | swap %d0 // Now d0 is ????VV?? |
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| 251 | and.w #0xff00,%d0 // Now d0 is ????VV00 (1) |
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| 252 | lsr.w #6,%d0 // Now d0.w contains the VBR table offset |
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| 253 | move.l VBR,%a0 // Get the address from VBR to a0 |
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| 254 | move.l (%a0,%d0.w),%a0 // Fetch the vector |
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| 255 | move.l 4(%sp),%d0 // Restore d0 |
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| 256 | move.l %a0,4(%sp) // Place target address to the stack |
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| 257 | move.l (%sp)+,%a0 // Restore a0, target address is on TOS |
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| 258 | ret // This will jump to the handler and |
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[d755cbd] | 259 | // restore the stack |
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[f233256] | 260 | |
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| 261 | (1) If 'myhandler' is guaranteed to be in the first 64K, e.g. just |
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[d755cbd] | 262 | after the vector table then that insn is not needed. |
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| 263 | |
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[f233256] | 264 | There are probably shorter ways to do this, but it I believe is enough to |
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| 265 | illustrate the trick. Optimisation is left as an exercise to the reader :-) |
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[d755cbd] | 266 | |
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| 267 | Interrupt Levels |
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| 268 | ---------------- |
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| 269 | |
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[f233256] | 270 | Eight levels (0-7) of interrupt priorities are supported by MC68xxx family |
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| 271 | members with level seven (7) being the highest priority. Level zero (0) |
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| 272 | indicates that interrupts are fully enabled. Interrupt requests for interrupts |
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| 273 | with priorities less than or equal to the current interrupt mask level are |
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| 274 | ignored. |
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[d755cbd] | 275 | |
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[f233256] | 276 | Although RTEMS supports 256 interrupt levels, the MC68xxx family only supports |
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| 277 | eight. RTEMS interrupt levels 0 through 7 directly correspond to MC68xxx |
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| 278 | interrupt levels. All other RTEMS interrupt levels are undefined and their |
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| 279 | behavior is unpredictable. |
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[d755cbd] | 280 | |
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| 281 | Default Fatal Error Processing |
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| 282 | ============================== |
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| 283 | |
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| 284 | The default fatal error handler for this architecture disables processor |
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[f233256] | 285 | interrupts to level 7, places the error code in D0, and executes a ``stop`` |
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| 286 | instruction to simulate a halt processor instruction. |
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[d755cbd] | 287 | |
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| 288 | Symmetric Multiprocessing |
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| 289 | ========================= |
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| 290 | |
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| 291 | SMP is not supported. |
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| 292 | |
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| 293 | Thread-Local Storage |
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| 294 | ==================== |
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| 295 | |
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| 296 | Thread-local storage is supported. |
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| 297 | |
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| 298 | Board Support Packages |
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| 299 | ====================== |
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| 300 | |
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| 301 | System Reset |
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| 302 | ------------ |
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| 303 | |
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| 304 | An RTEMS based application is initiated or re-initiated when the MC68020 |
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[f233256] | 305 | processor is reset. When the MC68020 is reset, the processor performs the |
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| 306 | following actions: |
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[d755cbd] | 307 | |
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[f233256] | 308 | - The tracing bits of the status register are cleared to disable tracing. |
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[d755cbd] | 309 | |
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[f233256] | 310 | - The supervisor interrupt state is entered by setting the supervisor (S) bit |
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| 311 | and clearing the master/interrupt (M) bit of the status register. |
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[d755cbd] | 312 | |
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[f233256] | 313 | - The interrupt mask of the status register is set to level 7 to effectively |
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| 314 | disable all maskable interrupts. |
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[d755cbd] | 315 | |
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| 316 | - The vector base register (VBR) is set to zero. |
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| 317 | |
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[f233256] | 318 | - The cache control register (CACR) is set to zero to disable and freeze the |
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| 319 | processor cache. |
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[d755cbd] | 320 | |
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[f233256] | 321 | - The interrupt stack pointer (ISP) is set to the value stored at vector 0 |
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| 322 | (bytes 0-3) of the exception vector table (EVT). |
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[d755cbd] | 323 | |
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[f233256] | 324 | - The program counter (PC) is set to the value stored at vector 1 (bytes 4-7) |
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| 325 | of the EVT. |
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[d755cbd] | 326 | |
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[f233256] | 327 | - The processor begins execution at the address stored in the PC. |
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[d755cbd] | 328 | |
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| 329 | Processor Initialization |
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| 330 | ------------------------ |
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| 331 | |
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[f233256] | 332 | The address of the application's initialization code should be stored in the |
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| 333 | first vector of the EVT which will allow the immediate vectoring to the |
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| 334 | application code. If the application requires that the VBR be some value |
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| 335 | besides zero, then it should be set to the required value at this point. All |
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| 336 | tasks share the same MC68020's VBR value. Because interrupts are enabled |
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| 337 | automatically by RTEMS as part of the context switch to the first task, the VBR |
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| 338 | MUST be set by either RTEMS of the BSP before this occurs ensure correct |
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| 339 | interrupt vectoring. If processor caching is to be utilized, then it should be |
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| 340 | enabled during the reset application initialization code. |
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| 341 | |
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| 342 | In addition to the requirements described in the Board Support Packages chapter |
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| 343 | of the Applications User's Manual for the reset code which is executed before |
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| 344 | the call to initialize executive, the MC68020 version has the following |
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[d755cbd] | 345 | specific requirements: |
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| 346 | |
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[f233256] | 347 | - Must leave the S bit of the status register set so that the MC68020 remains |
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| 348 | in the supervisor state. |
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[d755cbd] | 349 | |
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[f233256] | 350 | - Must set the M bit of the status register to remove the MC68020 from the |
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| 351 | interrupt state. |
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[d755cbd] | 352 | |
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[f233256] | 353 | - Must set the master stack pointer (MSP) such that a minimum stack size of |
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| 354 | MINIMUM_STACK_SIZE bytes is provided for the initialize executive directive. |
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[d755cbd] | 355 | |
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[d389819] | 356 | - Must initialize the MC68020's vector table. |
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