1 | .. comment SPDX-License-Identifier: CC-BY-SA-4.0 |
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2 | |
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3 | .. COMMENT: Copyright (c) 2014 embedded brains GmbH. All rights reserved. |
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4 | |
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5 | Lattice Mico32 Specific Information |
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6 | *********************************** |
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7 | |
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8 | This chaper discusses the Lattice Mico32 architecture dependencies in this port |
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9 | of RTEMS. The Lattice Mico32 is a 32-bit Harvard, RISC architecture "soft" |
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10 | microprocessor, available for free with an open IP core licensing |
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11 | agreement. Although mainly targeted for Lattice FPGA devices the microprocessor |
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12 | can be implemented on other vendors' FPGAs, too. |
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13 | |
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14 | **Architecture Documents** |
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15 | |
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16 | For information on the Lattice Mico32 architecture, refer to the following |
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17 | documents available from Lattice Semiconductor http://www.latticesemi.com/. |
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18 | |
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19 | - *"LatticeMico32 Processor Reference Manual"* |
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20 | http://www.latticesemi.com/dynamic/view_document.cfm?document_id=20890 |
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21 | |
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22 | CPU Model Dependent Features |
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23 | ============================ |
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24 | |
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25 | The Lattice Mico32 architecture allows for different configurations of the |
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26 | processor. This port is based on the assumption that the following options are |
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27 | implemented: |
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28 | |
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29 | - hardware multiplier |
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30 | |
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31 | - hardware divider |
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32 | |
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33 | - hardware barrel shifter |
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34 | |
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35 | - sign extension instructions |
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36 | |
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37 | - instruction cache |
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38 | |
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39 | - data cache |
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40 | |
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41 | - debug |
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42 | |
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43 | Register Architecture |
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44 | ===================== |
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45 | |
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46 | This section gives a brief introduction to the register architecture of the |
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47 | Lattice Mico32 processor. |
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48 | |
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49 | The Lattice Mico32 is a RISC archictecture processor with a 32-register file of |
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50 | 32-bit registers. |
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51 | |
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52 | Register Name |
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53 | |
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54 | Function |
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55 | |
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56 | r0 |
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57 | |
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58 | holds value zero |
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59 | |
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60 | r1-r25 |
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61 | |
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62 | general purpose |
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63 | |
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64 | r26/gp |
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65 | |
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66 | general pupose / global pointer |
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67 | |
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68 | r27/fp |
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69 | |
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70 | general pupose / frame pointer |
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71 | |
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72 | r28/sp |
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73 | |
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74 | stack pointer |
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75 | |
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76 | r29/ra |
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77 | |
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78 | return address |
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79 | |
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80 | r30/ea |
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81 | |
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82 | exception address |
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83 | |
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84 | r31/ba |
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85 | |
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86 | breakpoint address |
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87 | |
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88 | Note that on processor startup all register values are undefined including r0, |
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89 | thus r0 has to be initialized to zero. |
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90 | |
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91 | Calling Conventions |
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92 | =================== |
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93 | |
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94 | Calling Mechanism |
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95 | ----------------- |
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96 | |
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97 | A call instruction places the return address to register r29 and a return from |
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98 | subroutine (ret) is actually a branch to r29/ra. |
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99 | |
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100 | Register Usage |
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101 | -------------- |
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102 | |
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103 | A subroutine may freely use registers r1 to r10 which are *not* preserved |
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104 | across subroutine invocations. |
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105 | |
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106 | Parameter Passing |
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107 | ----------------- |
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108 | |
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109 | When calling a C function the first eight arguments are stored in registers r1 |
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110 | to r8. Registers r1 and r2 hold the return value. |
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111 | |
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112 | Memory Model |
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113 | ============ |
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114 | |
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115 | The Lattice Mico32 processor supports a flat memory model with a 4 Gbyte |
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116 | address space with 32-bit addresses. |
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117 | |
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118 | The following data types are supported: |
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119 | |
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120 | ================== ==== ====================== |
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121 | Type Bits C Compiler Type |
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122 | ================== ==== ====================== |
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123 | unsigned byte 8 unsigned char |
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124 | signed byte 8 char |
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125 | unsigned half-word 16 unsigned short |
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126 | signed half-word 16 short |
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127 | unsigned word 32 unsigned int / unsigned long |
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128 | signed word 32 int / long |
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129 | ================== ==== ====================== |
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130 | |
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131 | Data accesses need to be aligned, with unaligned accesses result are undefined. |
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132 | |
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133 | Interrupt Processing |
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134 | ==================== |
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135 | |
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136 | The Lattice Mico32 has 32 interrupt lines which are however served by only one |
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137 | exception vector. When an interrupt occurs following happens: |
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138 | |
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139 | - address of next instruction placed in r30/ea |
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140 | |
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141 | - IE field of IE CSR saved to EIE field and IE field cleared preventing further |
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142 | exceptions from occuring. |
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143 | |
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144 | - branch to interrupt exception address EBA CSR + 0xC0 |
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145 | |
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146 | The interrupt exception handler determines from the state of the interrupt |
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147 | pending registers (IP CSR) and interrupt enable register (IE CSR) which |
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148 | interrupt to serve and jumps to the interrupt routine pointed to by the |
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149 | corresponding interrupt vector. |
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150 | |
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151 | For now there is no dedicated interrupt stack so every task in the system MUST |
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152 | have enough stack space to accommodate the worst case stack usage of that |
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153 | particular task and the interrupt service routines COMBINED. |
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154 | |
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155 | Nested interrupts are not supported. |
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156 | |
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157 | Default Fatal Error Processing |
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158 | ============================== |
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159 | |
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160 | Upon detection of a fatal error by either the application or RTEMS during |
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161 | initialization the ``rtems_fatal_error_occurred`` directive supplied by the |
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162 | Fatal Error Manager is invoked. The Fatal Error Manager will invoke the |
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163 | user-supplied fatal error handlers. If no user-supplied handlers are |
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164 | configured or all of them return without taking action to shutdown the |
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165 | processor or reset, a default fatal error handler is invoked. |
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166 | |
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167 | Most of the action performed as part of processing the fatal error are |
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168 | described in detail in the Fatal Error Manager chapter in the User's Guide. |
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169 | However, the if no user provided extension or BSP specific fatal error handler |
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170 | takes action, the final default action is to invoke a CPU architecture specific |
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171 | function. Typically this function disables interrupts and halts the processor. |
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172 | |
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173 | In each of the architecture specific chapters, this describes the precise |
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174 | operations of the default CPU specific fatal error handler. |
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175 | |
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176 | Symmetric Multiprocessing |
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177 | ========================= |
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178 | |
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179 | SMP is not supported. |
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180 | |
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181 | Thread-Local Storage |
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182 | ==================== |
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183 | |
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184 | Thread-local storage is not implemented. |
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185 | |
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186 | Board Support Packages |
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187 | ====================== |
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188 | |
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189 | There are no Lattice Micro32 specific notes on BSPs. |
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190 | |
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191 | System Reset |
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192 | ------------ |
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193 | |
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194 | An RTEMS based application is initiated or re-initiated when the processor is |
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195 | reset. |
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