source: rtems-docs/cpu-supplement/lattice_micro32.rst @ 67195aa

5
Last change on this file since 67195aa was c6f8e51, checked in by Joel Sherrill <joel@…>, on 10/12/17 at 23:50:59

Shorten the name of the BSP and Device Driver Development Guide

Old name:

RTEMS BSP and Device Driver Development Guide

This is long and causes problems in the PDF output. This patch
changes the name to:

RTEMS BSP and Driver Guide

Closes #3141.

  • Property mode set to 100644
File size: 5.2 KB
Line 
1.. comment SPDX-License-Identifier: CC-BY-SA-4.0
2
3.. COMMENT: Copyright (c) 2014 embedded brains GmbH.  All rights reserved.
4
5Lattice Mico32 Specific Information
6***********************************
7
8This chaper discusses the Lattice Mico32 architecture dependencies in this port
9of RTEMS. The Lattice Mico32 is a 32-bit Harvard, RISC architecture "soft"
10microprocessor, available for free with an open IP core licensing
11agreement. Although mainly targeted for Lattice FPGA devices the microprocessor
12can be implemented on other vendors' FPGAs, too.
13
14**Architecture Documents**
15
16For information on the Lattice Mico32 architecture, refer to the following
17documents available from Lattice Semiconductor http://www.latticesemi.com/.
18
19- *"LatticeMico32 Processor Reference Manual"*
20  http://www.latticesemi.com/dynamic/view_document.cfm?document_id=20890
21
22CPU Model Dependent Features
23============================
24
25The Lattice Mico32 architecture allows for different configurations of the
26processor. This port is based on the assumption that the following options are
27implemented:
28
29- hardware multiplier
30
31- hardware divider
32
33- hardware barrel shifter
34
35- sign extension instructions
36
37- instruction cache
38
39- data cache
40
41- debug
42
43Register Architecture
44=====================
45
46This section gives a brief introduction to the register architecture of the
47Lattice Mico32 processor.
48
49The Lattice Mico32 is a RISC archictecture processor with a 32-register file of
5032-bit registers.
51
52Register Name
53
54Function
55
56r0
57
58holds value zero
59
60r1-r25
61
62general purpose
63
64r26/gp
65
66general pupose / global pointer
67
68r27/fp
69
70general pupose / frame pointer
71
72r28/sp
73
74stack pointer
75
76r29/ra
77
78return address
79
80r30/ea
81
82exception address
83
84r31/ba
85
86breakpoint address
87
88Note that on processor startup all register values are undefined including r0,
89thus r0 has to be initialized to zero.
90
91Calling Conventions
92===================
93
94Calling Mechanism
95-----------------
96
97A call instruction places the return address to register r29 and a return from
98subroutine (ret) is actually a branch to r29/ra.
99
100Register Usage
101--------------
102
103A subroutine may freely use registers r1 to r10 which are *not* preserved
104across subroutine invocations.
105
106Parameter Passing
107-----------------
108
109When calling a C function the first eight arguments are stored in registers r1
110to r8. Registers r1 and r2 hold the return value.
111
112Memory Model
113============
114
115The Lattice Mico32 processor supports a flat memory model with a 4 Gbyte
116address space with 32-bit addresses.
117
118The following data types are supported:
119
120================== ==== ======================
121Type               Bits C Compiler Type
122================== ==== ======================
123unsigned byte      8    unsigned char
124signed byte        8    char
125unsigned half-word 16   unsigned short
126signed half-word   16   short
127unsigned word      32   unsigned int / unsigned long
128signed word        32   int / long
129================== ==== ======================
130
131Data accesses need to be aligned, with unaligned accesses result are undefined.
132
133Interrupt Processing
134====================
135
136The Lattice Mico32 has 32 interrupt lines which are however served by only one
137exception vector. When an interrupt occurs following happens:
138
139- address of next instruction placed in r30/ea
140
141- IE field of IE CSR saved to EIE field and IE field cleared preventing further
142  exceptions from occuring.
143
144- branch to interrupt exception address EBA CSR + 0xC0
145
146The interrupt exception handler determines from the state of the interrupt
147pending registers (IP CSR) and interrupt enable register (IE CSR) which
148interrupt to serve and jumps to the interrupt routine pointed to by the
149corresponding interrupt vector.
150
151For now there is no dedicated interrupt stack so every task in the system MUST
152have enough stack space to accommodate the worst case stack usage of that
153particular task and the interrupt service routines COMBINED.
154
155Nested interrupts are not supported.
156
157Default Fatal Error Processing
158==============================
159
160Upon detection of a fatal error by either the application or RTEMS during
161initialization the ``rtems_fatal_error_occurred`` directive supplied by the
162Fatal Error Manager is invoked.  The Fatal Error Manager will invoke the
163user-supplied fatal error handlers.  If no user-supplied handlers are
164configured or all of them return without taking action to shutdown the
165processor or reset, a default fatal error handler is invoked.
166
167Most of the action performed as part of processing the fatal error are
168described in detail in the Fatal Error Manager chapter in the User's Guide.
169However, the if no user provided extension or BSP specific fatal error handler
170takes action, the final default action is to invoke a CPU architecture specific
171function.  Typically this function disables interrupts and halts the processor.
172
173In each of the architecture specific chapters, this describes the precise
174operations of the default CPU specific fatal error handler.
175
176Symmetric Multiprocessing
177=========================
178
179SMP is not supported.
180
181Thread-Local Storage
182====================
183
184Thread-local storage is not implemented.
185
186Board Support Packages
187======================
188
189There are no Lattice Micro32 specific notes on BSPs.
190
191System Reset
192------------
193
194An RTEMS based application is initiated or re-initiated when the processor is
195reset.
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